CN114337643A - Pulse signal output circuit - Google Patents
Pulse signal output circuit Download PDFInfo
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- CN114337643A CN114337643A CN202210195075.4A CN202210195075A CN114337643A CN 114337643 A CN114337643 A CN 114337643A CN 202210195075 A CN202210195075 A CN 202210195075A CN 114337643 A CN114337643 A CN 114337643A
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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Abstract
The application discloses a pulse signal output circuit, which comprises a first control circuit and a second control circuit, wherein the first control circuit enables a first output signal output by the first control circuit to be a reverse signal of a pulse signal based on the pulse signal and the first signal input to the first control circuit, and can be butted with an external PNP receiving circuit; the second control circuit enables the second output signal output by the second control circuit to be a same-direction signal of the pulse signal based on the first output signal and the second signal input to the second control circuit, and can be connected with an external NPN receiving circuit in a butt joint mode. In addition, the first output end and the second output end respectively output signals with the polarity opposite to or the same as that of the pulse signals, so that differential signal output is formed between the first output end and the second output end, and an external differential signal receiving circuit can be connected in an abutting mode. Therefore, the pulse signal output circuit can be compatible with a differential signal receiving circuit, and therefore the pulse signal output circuit can be compatible with various different pulse signal receiving circuits.
Description
Technical Field
The present application relates to the field of electronic technology, and more particularly, to a pulse signal output circuit.
Background
With the development of automatic industrial equipment and the wide application of servo, in many industrial applications, the servo needs to send a pulse signal to an upper computer, or the upper computer sends the pulse signal to a servo driver.
However, the conventional pulse signal receiving circuits are different from each other, and there are a single-ended PNP receiving circuit, a single-ended NPN receiving circuit, a differential signal receiving circuit, and the like. Different types of pulse signal receiving circuits need to be connected with their corresponding pulse signal output circuits in a butt joint mode when working normally, so that in the prior art, when the pulse signal output circuits are applied, a plurality of different circuits need to be designed to be matched with and connected with the different types of pulse receiving circuits in a butt joint mode, and the situation brings inconvenience to practical use.
Therefore, it is important to design a pulse signal output circuit to be compatible with various types of pulse signal receiving circuits.
Disclosure of Invention
In view of the above, the present application provides a pulse signal output circuit for being compatible with various types of pulse signal receiving circuits.
In order to achieve the above object, the following solutions are proposed:
a pulse signal output circuit comprising:
the first control circuit is used for controlling the output end of the first control circuit to output a first output signal based on the pulse signal and the first signal, and the first output signal is a reverse signal of the pulse signal;
the first end of the second control circuit is connected with a power supply voltage, the first control end of the second control circuit is connected with the output end of the first control circuit and inputs the first output signal, the second control end of the second control circuit inputs a second signal, the second control circuit is used for controlling the output end of the second control circuit to output a second output signal based on the first output signal and the second signal, and the second output signal is a reverse signal of the first output signal;
the second signal is a reverse signal of the first signal, the output end of the first control circuit is a first output end of the pulse signal output circuit, and the output end of the second control circuit is a second output end of the pulse signal output circuit.
Preferably, the first control circuit includes: the circuit comprises a first switch tube, a first resistor and a pull-up resistor; wherein:
the input end of the first switch tube is connected with a power supply voltage through the first resistor, the output end of the first switch tube is grounded, and a control end of the first switch tube inputs a pulse signal;
one end of the pull-up resistor is connected with the input end of the first switching tube, and the other end of the pull-up resistor is connected with a power supply voltage;
the output end of the first switch tube is the output end of the first control circuit, the end of the pull-up resistor connected with the power voltage is the second control end of the first control circuit, when the pulse signal is at a high level, the first switch tube is switched on, the output end of the first control circuit outputs a low level, when the pulse signal is at a low level, the first switch tube is switched off, and the output end of the first control circuit outputs a high level.
Preferably, the second control circuit includes: the second switch tube, the second resistor and the pull-down resistor; wherein:
the input end of the second switching tube is connected with a power supply voltage, and the control end of the second switching tube is connected with the output end of the first control circuit through the second resistor;
one end of the pull-down resistor is connected with the output end of the second switch tube, and the other end of the pull-down resistor is grounded;
the input end of the second switch tube is the first end of the second control circuit, the control end of the second switch tube is the first control end of the second control circuit, the output end of the second switch tube is the output end of the second control circuit, the grounded end of the pull-down resistor is the second control end of the second control circuit, when the pulse signal is at a high level, the first switch tube and the second switch tube are switched on, the output end of the second control circuit outputs a high level, when the pulse signal is at a low level, the first switch tube and the second switch tube are switched off, and the output end of the second control circuit outputs a low level.
Preferably, the first control circuit further comprises:
and one end of the current-limiting resistor is connected with the control end of the first switch tube, and a pulse signal is input into the control end of the first switch tube through the current-limiting resistor.
Preferably, the first control circuit further comprises:
and one end of the safety pull-down resistor is connected with the control end of the first switch tube, and the other end of the safety pull-down resistor is connected with the ground, so that the control end of the first switch tube is ensured to be in a low level state when the pulse signal is in a suspended state, and the first switch tube is prevented from being conducted.
Preferably, the first switching tube is an NPN-type triode;
the control end of the first switching tube is a base electrode of the NPN type triode, the output end of the first switching tube is an emitting electrode of the NPN type triode, and the input end of the first switching tube is a collector electrode of the NPN type triode;
or the like, or, alternatively,
the first switch tube is an NMOS tube;
the control end of the first switch tube is the grid electrode of the NMOS tube, the output end of the first switch tube is the source electrode of the NMOS tube, and the input end of the first switch tube is the drain electrode of the NMOS tube.
Preferably, the second switching tube is a PNP type triode;
the control end of the second switching tube is the base electrode of the PNP type triode, the output end of the second switching tube is the collector electrode of the PNP type triode, and the input end of the second switching tube is the emitting electrode of the PNP type triode;
or the like, or, alternatively,
the second switch tube is a PMOS tube;
the control end of the second switch tube is the grid electrode of the PMOS tube, the output end of the second switch tube is the drain electrode of the PMOS tube, and the input end of the second switch tube is the source electrode of the PMOS tube.
Preferably, the first control circuit further comprises:
the first diode is connected between the input end of the first switch tube and the pull-up resistor, and the direction of current flowing to the input end of the first switch tube is the forward conduction direction of the first diode;
the common end of the first diode and the pull-up resistor is connected with one end of the first positive temperature coefficient thermistor, and the other end of the first positive temperature coefficient thermistor is used as the output end of the first control circuit;
and the first capacitor is connected in parallel with two ends of the pull-up resistor.
Preferably, the second control circuit further comprises:
the second diode is connected between the output end of the second switch tube and the pull-down resistor, and the direction of current flowing out of the output end of the second switch tube is the forward conduction direction of the second diode;
the common end of the second diode and the pull-down resistor is connected with one end of the second positive temperature coefficient thermistor, and the other end of the second positive temperature coefficient thermistor is used as the output end of the second control circuit;
and the second capacitor is connected in parallel with two ends of the pull-down resistor.
Preferably, the method further comprises the following steps:
and one end of the third capacitor is connected with the power supply voltage, and the other end of the third capacitor is grounded.
According to the scheme, the pulse signal output circuit comprises two control circuits, wherein the first end of the first control circuit is connected with a power supply voltage, the second end of the first control circuit is grounded, and a first signal is input by the second control end; when the first output signal is input from the output end of the first control circuit to the first control end of the second control circuit, the output end of the second control circuit can output a second output signal with the polarity opposite to that of the first signal, namely a signal with the same polarity as the pulse signal, and the output end of the second control circuit can be in butt joint with an external NPN receiving circuit.
In addition, the output end of the first control circuit and the output end of the second control circuit respectively output signals with the polarity opposite to or the same as that of the pulse signals, so that differential signal output can be formed between the output ends of the first control circuit and the second control circuit, and the output end of the first control circuit and the output end of the second control circuit can be connected with an external differential signal receiving circuit in an abutting mode. Therefore, the pulse signal output circuit can be compatible with the differential signal receiving circuit under the condition of being compatible with the PNP receiving circuit and the NPN receiving circuit, so that the pulse signal output circuit can be compatible with various different pulse signal receiving circuits.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a pulse signal output circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another pulse signal output circuit disclosed in the embodiment of the present application.
Fig. 3 is a waveform diagram of signals at each end of a pulse signal output circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pulse signal output circuit provided in an embodiment of the present application, where the pulse signal output circuit includes a first control circuit and a second control circuit, where:
a first control circuit, which may include a plurality of terminals, each of which may be connected to a different electronic component or input signal.
Specifically, the first end of the first control circuit may be connected to a power supply voltage, the second end may be grounded, the first control end may input a pulse signal, the second control end may input a first signal, and based on the connection relationship and the input signal, the first control circuit may control the output end thereof to output a first output signal based on the pulse signal and the first signal, where the first output signal is an inverted signal of the pulse signal, that is, when the pulse signal is at a low level, the first output signal may be at a high level, and when the pulse signal is at a high level, the first output signal may be at a low level.
A second control circuit, which may include a plurality of terminals, each of which may be connected to a different electronic component or input signal.
Specifically, the first end of the second control circuit may be connected to a power supply voltage, the first control end may be connected to an output end of the first control circuit, and may further input a first output signal, the second control end may input a second signal, and based on the connection relationship and the input signal, the second control circuit may control an output end thereof to output a second output signal based on the first output signal and the second signal, where the second output signal is a reverse signal of the first output signal, and because the first output signal is a direction signal of the pulse signal, the second output signal is a same-direction signal of the pulse signal, that is, when the pulse signal is at a low level, the second output signal may be at a low level, and when the pulse signal is at a high level, the second output signal may be at a high level.
In the above-described pulse signal output circuit, the second signal may be an inverted signal of the first signal, the output terminal of the first control circuit may be a first output terminal of the pulse signal output circuit, and the output terminal of the second control circuit may be a second output terminal of the pulse signal output circuit.
It should be noted that the amplitude of the power supply voltage may be adjusted and converted according to a practical application scenario, so that the pulse signal output circuit of the embodiment of the present application may output pulse signals with different voltage amplitudes, that is, may be compatible with a plurality of pulse signal receiving circuits with different voltages.
In some embodiments of the present application, a first control circuit of the pulse signal output circuit is introduced, and a specific structure of the first control circuit will be further described below, with reference to fig. 2 for details.
Specifically, the first control circuit may include: a first switch tube Q1, a first resistor R1 and a pull-up resistor R3.
The input end of the first switch tube Q1 can be connected to the power supply voltage VCC through the first resistor R1, the output end can be grounded, and the control end can input a pulse signal.
One end of the pull-up resistor can be connected with the input end of the first switching tube Q1, and the other end of the pull-up resistor can be connected with a power supply voltage VCC;
specifically, one end of the first resistor R1, which is far away from the first switch tube Q1, may be a first end of the first control circuit, an output end of the first switch tube may be a second end of the first control circuit, a control end of the first switch tube Q1 may be a first control end of the first control circuit, an input end of the first switch tube Q1 may be an output end of the first control circuit, and an end of the pull-up resistor R1, which is connected to the power supply voltage VCC, may be a second control end of the first control circuit.
When a high-level pulse signal is input from the control terminal of the first switching transistor Q1, the first switching transistor Q1 is turned on, and a current of the power supply voltage VCC is input from the input terminal of the first switching transistor Q1 to the first switching transistor Q1 after passing through the first resistor R1, and then flows into the ground from the output terminal of the first switching transistor Q1. If the input terminal of the first switch Q1 is used as the output terminal of the first control circuit and is externally connected to an external circuit, the current of the external circuit enters the first switch Q1 from the input terminal of the first switch Q1 and flows into the ground from the output terminal of the first switch Q1, and the first output signal received by the external circuit is at a low level, so that when the pulse signal is at a high level, the first output signal output by the input terminal of the first switch Q1 as the output terminal of the first control circuit may be at a low level.
When a low-level pulse signal is input from the control terminal of the first switch Q1, the first switch is turned off, if the input terminal of the first switch Q1 is used as the output terminal of the first control circuit and is externally connected to an external circuit, a current passes through the pull-up resistor from a power voltage to input the first signal from the input terminal of the first switch Q1 to the external circuit, and the first output signal received by the external circuit is high level, so that when the pulse signal is low level, the first output signal output by the input terminal of the first switch Q1 as the output terminal of the first control circuit can be high level.
The first switch Q1 is introduced in some embodiments of the present application, and the first switch Q1 will be further described below.
Specifically, the first switching transistor Q1 may be an NPN transistor.
The control terminal of the first switch Q1 may be a base of an NPN transistor, the output terminal of the first switch Q1 may be an emitter of the NPN transistor, and the input terminal of the first switch Q1 may be a collector of the NPN transistor.
The NPN transistor is turned on when the high-level pulse signal enters the NPN transistor from the base, and the NPN transistor is turned off when the pulse signal is at the low level, and the working principle of the first control circuit when the NPN transistor is turned on or off may refer to the foregoing embodiments, which are not described herein again.
Specifically, the first switching tube Q1 may also be an NMOS tube, and may be used in an application scenario where a requirement on the frequency of the pulse signal is high.
The control terminal of the first switch Q1 may be a gate of an NMOS transistor, the output terminal of the first switch Q1 may be a source of the NMOS transistor, and the input terminal of the first switch Q1 may be a drain of the NMOS transistor.
Similarly, when the NMOS transistor is turned on or off, the operation principle of the first control circuit may refer to the foregoing embodiments, and will not be described herein again.
In order to increase the stability of the pulse signal output circuit of the embodiment of the present application, the first control circuit may further include: a first diode D1, a first positive temperature coefficient thermistor RT1 and a first capacitor C1.
Specifically, a first diode D1 may be connected between the input terminal of the first switch Q1 and the pull-up resistor R3, wherein the forward conducting direction of the first diode D1 may be a direction in which a current flows to the input terminal of the first switch Q1. When the external reverse circuit is misconnected, the first diode D1 can prevent the external reverse voltage from entering the first control circuit and damaging other electronic elements.
One end of the first positive temperature coefficient thermistor RT1 may be connected to a common terminal of the first diode D1 and the pull-up resistor R3, and the other end may serve as an output terminal of the first control circuit. Therefore, the current flowing into the external circuit or the current flowing out of the external circuit is required to pass through the first positive temperature coefficient thermistor RT1, so that the phenomenon that other electronic elements are burnt due to excessive current can be avoided.
And the first capacitor C1 may be connected in parallel across the pull-up resistor R3 and may be used for filtering the supply voltage VCC connected to the pull-up resistor R3.
In order to avoid the pulse signal current from being too large to burn out the first switch Q1, the first control circuit of the embodiment of the present application may further include a current limiting resistor R5.
Specifically, one end of the current limiting resistor R5 may be connected to the control terminal of the first switch transistor Q1, and the pulse signal may be input to the control terminal of the first switch transistor Q1 through the current limiting resistor R5, so as to avoid the pulse signal current from being too large and burning the first switch transistor Q1 and other circuit elements.
In order to avoid the first switch Q1 being turned on by mistake, the first control circuit of the embodiment of the present application may further include a safety pull-down resistor R6.
Specifically, one end of the safety pull-down circuit R6 may be connected to the control end of the first switch tube Q1, and the other end may be grounded, so that when the pulse signal is in a suspension state, the control end of the first switch tube Q1 is in a low level state, thereby preventing the first switch tube Q1 from being turned on by mistake.
In some embodiments of the present application, a second control circuit of the pulse signal output circuit is introduced, and a specific structure of the second control circuit will be further described, and please refer to fig. 2 for details.
Specifically, the second control circuit may include: a second switch transistor Q2, a second resistor R2 and a pull-down resistor R4.
The input terminal of the second switch Q2 may be connected to the power supply voltage VCC, and the control terminal may be connected to the output terminal of the first control circuit through the second resistor R2.
One end of the pull-down resistor R4 may be connected to the output terminal of the second switch transistor Q2, and the other end may be grounded.
Specifically, the input terminal of the second switch Q2 may serve as the first terminal of the second control circuit, the control terminal of the second switch may serve as the first control terminal of the second control circuit, the output terminal of the second switch may serve as the output terminal of the second control circuit, and the grounded terminal of the pull-down resistor R4 may serve as the second control terminal of the second control circuit.
When a high-level pulse signal is input from the control terminal of the first switch Q1, the first switch Q1 is turned on, and a low-level first output signal enters the control terminal of the second switch Q2, so that the second switch Q2 is also turned on. If the output terminal of the second switch Q2 is used as the output terminal of the second control circuit and is externally connected to an external circuit, the current of the power voltage VCC may be input into the second switch Q2 through the input terminal of the second switch Q2, and then may be input into the external circuit from the output terminal of the second switch Q2, and the second output signal received by the external circuit is the inverse signal of the first output signal, i.e. the high level.
When a low-level pulse signal is input from the control terminal of the first switch Q1, the first switch Q1 is turned off, and a high-level first output signal cannot enter the control terminal of the second switch Q2, so that the second switch Q2 is also turned off. If the output terminal of the second switch Q2 is used as the output terminal of the second control circuit and is externally connected to an external circuit, the current of the external circuit can flow into the ground through the pull-down resistor R4, and the second output signal received by the external circuit is the inverse signal of the first output signal, i.e., the low level.
In order to increase the stability of the pulse signal output circuit of the embodiment of the present application, the second control circuit may further include: a second diode D2, a second ptc thermistor RT2, and a second capacitor C2.
Specifically, a second diode D2 may be connected between the output terminal of the second switch Q2 and the pull-down resistor R4, wherein the forward conducting direction of the second diode D2 may be the direction of current flowing out of the output terminal of the second switch Q2. When the external reverse circuit is mistakenly connected, the second diode D2 can prevent the external reverse voltage from entering the second control circuit and damaging other electronic components.
One end of the second ptc thermistor RT2 may be connected to the common terminal of the second diode D2 and the pull-down resistor R4, and the other end may serve as an output terminal of the second control circuit. Therefore, the current flowing into the external circuit or the current flowing out of the external circuit is required to pass through the second positive temperature coefficient thermistor RT2, so that the current is prevented from being too large to burn other electronic elements.
And a second capacitor C2 may be connected in parallel across the pull-down resistor R4 and may be used for filtering the ground connected to the pull-down resistor R4.
In some embodiments of the present application, a second switch Q2 is introduced, and the second switch Q2 will be further described.
Specifically, the second switching tube Q2 may be a PNP transistor.
The control terminal of the second switch Q2 may be a base of a PNP transistor, the output terminal of the second switch Q2 may be a collector of the PNP transistor, and the input terminal of the second switch Q2 may be an emitter of the PNP transistor.
When a high-level pulse signal is input from the first control terminal of the first switch tube Q1, the first switch tube Q1 is turned on, and since the base of the PNP type triode is connected to the input terminal of the first switch tube Q1, the PNP type triode is also turned on, and when the pulse signal is low, the first switch tube Q1 is turned off, the first output signal output from the input terminal of the first switch tube Q1 cannot enter the base of the PNP type triode, and the PNP type triode is also turned off. The working principle of the second control circuit when the PNP type triode is turned on or off can refer to the foregoing embodiments, and details are not described here.
Specifically, the second switching tube Q2 may also be a PMOS tube, and may be used in an application scenario where the requirement on the frequency of the pulse signal is high.
The control terminal of the second switch transistor Q2 may be a gate of a PMOS transistor, the output terminal of the second switch transistor Q2 may be a drain of an NMOS transistor, and the input terminal of the second switch transistor Q2 may be a source of the NMOS transistor.
Similarly, when the PMOS transistor is turned on or off, the working principle of the second control circuit can refer to the foregoing embodiments, and will not be described herein again.
In order to reduce the influence of the power supply voltage on the pulse signal output circuit of the present application, the pulse signal output circuit of the embodiment of the present application may further be connected to a third capacitor C3, one end of the third capacitor C3 may be connected to the power supply voltage VCC, the other end of the third capacitor C3 may be grounded, and the third capacitor C3 may be configured to filter the power supply voltage VCC.
Next, waveforms of signals at respective ends of the pulse signal output circuit shown in fig. 2 when operating will be described, and details will be described with reference to fig. 3.
Specifically, the power supply voltage VCC may be connected to voltages with different amplitudes according to an actual situation, and here, taking the power supply voltage VCC as 5V as an example, the waveforms of signals at each port of the pulse output current of the present application may refer to fig. 3. Wherein, VP1 is the waveform of the pulse signal input by the first control terminal of the first control circuit; VP2 is the waveform of the first output terminal to ground; VP3 is the differential signal waveform of the second output terminal to the first output terminal; VP4 is the waveform of the second output terminal to ground.
Obviously, the pulse signal output circuit provided by the present application includes a first control circuit and a second control circuit, where a first switch Q1 of the first control circuit is turned on when the pulse signal is at a high level, the first output terminal can output a low level, a first switch Q1 is turned off when the pulse signal is at a low level, the pull-up resistor R3 provides the high level to the first output terminal, the first output terminal can output a pulse signal with a polarity opposite to that of the pulse signal, and can be externally connected with a PNP receiving circuit; when the first switch Q1 is turned on, the second switch Q2 is also turned on, the second output terminal can output a high level, when the first switch Q1 is turned off, the second switch Q2 is also turned off, the pull-down resistor R4 provides a low level to the second output terminal, and the second output terminal can output a pulse signal with the same polarity as the pulse signal, and can be externally connected with an NPN receiving circuit.
The first output end and the second output end can respectively output pulse signals with the same or opposite polarities to the pulse signals, namely the NPN receiving circuit and the PNP receiving circuit can be compatible, and the two output ends can also be used as two interface ends of the differential signals to be connected with the external differential signal receiving circuit.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A pulse signal output circuit, comprising:
the first control circuit is used for controlling the output end of the first control circuit to output a first output signal based on the pulse signal and the first signal, and the first output signal is a reverse signal of the pulse signal;
the first end of the second control circuit is connected with a power supply voltage, the first control end of the second control circuit is connected with the output end of the first control circuit and inputs the first output signal, the second control end of the second control circuit inputs a second signal, the second control circuit is used for controlling the output end of the second control circuit to output a second output signal based on the first output signal and the second signal, and the second output signal is a reverse signal of the first output signal;
the second signal is a reverse signal of the first signal, the output end of the first control circuit is a first output end of the pulse signal output circuit, and the output end of the second control circuit is a second output end of the pulse signal output circuit.
2. The pulse signal output circuit according to claim 1, wherein the first control circuit comprises: the circuit comprises a first switch tube, a first resistor and a pull-up resistor; wherein:
the input end of the first switch tube is connected with a power supply voltage through the first resistor, the output end of the first switch tube is grounded, and a control end of the first switch tube inputs a pulse signal;
one end of the pull-up resistor is connected with the input end of the first switching tube, and the other end of the pull-up resistor is connected with a power supply voltage;
the output end of the first switch tube is the output end of the first control circuit, the end of the pull-up resistor connected with the power voltage is the second control end of the first control circuit, when the pulse signal is at a high level, the first switch tube is switched on, the output end of the first control circuit outputs a low level, when the pulse signal is at a low level, the first switch tube is switched off, and the output end of the first control circuit outputs a high level.
3. The pulse signal output circuit according to claim 2, wherein the second control circuit comprises: the second switch tube, the second resistor and the pull-down resistor; wherein:
the input end of the second switching tube is connected with a power supply voltage, and the control end of the second switching tube is connected with the output end of the first control circuit through the second resistor;
one end of the pull-down resistor is connected with the output end of the second switch tube, and the other end of the pull-down resistor is grounded;
the input end of the second switch tube is the first end of the second control circuit, the control end of the second switch tube is the first control end of the second control circuit, the output end of the second switch tube is the output end of the second control circuit, the grounded end of the pull-down resistor is the second control end of the second control circuit, when the pulse signal is at a high level, the first switch tube and the second switch tube are switched on, the output end of the second control circuit outputs a high level, when the pulse signal is at a low level, the first switch tube and the second switch tube are switched off, and the output end of the second control circuit outputs a low level.
4. The pulse signal output circuit according to claim 2, wherein the first control circuit further comprises:
and one end of the current-limiting resistor is connected with the control end of the first switch tube, and a pulse signal is input into the control end of the first switch tube through the current-limiting resistor.
5. The pulse signal output circuit according to claim 2, wherein the first control circuit further comprises:
and one end of the safety pull-down resistor is connected with the control end of the first switch tube, and the other end of the safety pull-down resistor is connected with the ground, so that the control end of the first switch tube is ensured to be in a low level state when the pulse signal is in a suspended state, and the first switch tube is prevented from being conducted.
6. The pulse signal output circuit according to claim 2, wherein the first switching transistor is an NPN-type transistor;
the control end of the first switching tube is a base electrode of the NPN type triode, the output end of the first switching tube is an emitting electrode of the NPN type triode, and the input end of the first switching tube is a collector electrode of the NPN type triode;
or the like, or, alternatively,
the first switch tube is an NMOS tube;
the control end of the first switch tube is the grid electrode of the NMOS tube, the output end of the first switch tube is the source electrode of the NMOS tube, and the input end of the first switch tube is the drain electrode of the NMOS tube.
7. The pulse signal output circuit according to claim 3, wherein the second switching tube is a PNP type triode;
the control end of the second switching tube is the base electrode of the PNP type triode, the output end of the second switching tube is the collector electrode of the PNP type triode, and the input end of the second switching tube is the emitting electrode of the PNP type triode;
or the like, or, alternatively,
the second switch tube is a PMOS tube;
the control end of the second switch tube is the grid electrode of the PMOS tube, the output end of the second switch tube is the drain electrode of the PMOS tube, and the input end of the second switch tube is the source electrode of the PMOS tube.
8. The pulse signal output circuit according to claim 2, wherein the first control circuit further comprises:
the first diode is connected between the input end of the first switch tube and the pull-up resistor, and the direction of current flowing to the input end of the first switch tube is the forward conduction direction of the first diode;
the common end of the first diode and the pull-up resistor is connected with one end of the first positive temperature coefficient thermistor, and the other end of the first positive temperature coefficient thermistor is used as the output end of the first control circuit;
and the first capacitor is connected in parallel with two ends of the pull-up resistor.
9. The pulse signal output circuit according to claim 3, wherein the second control circuit further comprises:
the second diode is connected between the output end of the second switch tube and the pull-down resistor, and the direction of current flowing out of the output end of the second switch tube is the forward conduction direction of the second diode;
the common end of the second diode and the pull-down resistor is connected with one end of the second positive temperature coefficient thermistor, and the other end of the second positive temperature coefficient thermistor is used as the output end of the second control circuit;
and the second capacitor is connected in parallel with two ends of the pull-down resistor.
10. The pulse signal output circuit according to claim 1, further comprising:
and one end of the third capacitor is connected with the power supply voltage, and the other end of the third capacitor is grounded.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210195075.4A CN114337643B (en) | 2022-03-02 | 2022-03-02 | Pulse signal output circuit |
| PCT/CN2023/078970 WO2023165508A1 (en) | 2022-03-02 | 2023-03-01 | Pulse signal output circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210195075.4A CN114337643B (en) | 2022-03-02 | 2022-03-02 | Pulse signal output circuit |
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| CN114337643A true CN114337643A (en) | 2022-04-12 |
| CN114337643B CN114337643B (en) | 2022-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210195075.4A Active CN114337643B (en) | 2022-03-02 | 2022-03-02 | Pulse signal output circuit |
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| CN (1) | CN114337643B (en) |
| WO (1) | WO2023165508A1 (en) |
Cited By (1)
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|---|---|---|---|---|
| WO2023165508A1 (en) * | 2022-03-02 | 2023-09-07 | 广东科伺智能科技有限公司 | Pulse signal output circuit |
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|---|---|
| WO2023165508A1 (en) | 2023-09-07 |
| CN114337643B (en) | 2022-05-17 |
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