CN117348664A - LDO circuit and chip - Google Patents
LDO circuit and chip Download PDFInfo
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- CN117348664A CN117348664A CN202311414104.2A CN202311414104A CN117348664A CN 117348664 A CN117348664 A CN 117348664A CN 202311414104 A CN202311414104 A CN 202311414104A CN 117348664 A CN117348664 A CN 117348664A
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- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007664 blowing Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention discloses an LDO circuit and a chip, wherein the LDO circuit comprises: the differential amplifier, the first power tube, the voltage control circuit, the feedback circuit, the second power tube and the voltage division control circuit. According to the LDO circuit and the chip, in the power supply voltage powering-on stage, the voltage control circuit controls the voltage of the control end of the first power tube to turn off the first power tube along with the power supply voltage powering-on variation, so that the output voltage output by the LDO circuit is prevented from being powered on to overshoot, and meanwhile, the voltage division control circuit is turned off through the control signal so that the second power tube is turned off and does not participate in the powering-on stage; the voltage control circuit is turned off after the power supply voltage is powered on, and meanwhile, when the power supply voltage is subjected to linear transient change, the voltage division control circuit is turned on through a control signal so that the second power tube is turned on, and the functions of resetting, soft starting and the like are prevented from being triggered due to output power failure caused by mistaken turning off of the first power tube of the LDO circuit when the power supply voltage is subjected to linear transient change.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to an LDO circuit and a chip.
Background
The LDO circuitry inside the chip needs to power the fuse blowing, thus taking into account the high current (about 20 mA) and low on-resistance Rdson (about 10Ω), resulting in a very large size power transistor. The large-size power tube can introduce the problem of rapid power-up overshoot, especially for the rapid power-up (such as the power-up rate of 1V/1 us) of the vehicle product, so a protection circuit for preventing the power-up overshoot is needed.
As shown in fig. 1, the conventional scheme adopts an RC circuit composed of a resistor R3, a capacitor C1 and a pull-up tube Q2, wherein the delay of the RC circuit is directly related to the power-up slope of the power supply voltage VIN, and when the power supply voltage VIN is rapidly powered up, the gate of the pull-up tube Q2 is continuously kept low due to the delay, so that the pull-up tube Q2 is turned on first, the gate G1 of the power tube Q1 is pulled up to the power supply voltage VIN, and the power tube Q1 is turned off, so that the voltage VCC output by the output terminal Vout does not overshoot.
However, when the power supply voltage VIN is normally powered on, the voltage VCC output by the output terminal Vout is also stabilized at an expected value, and the chip operates normally, and when the power supply voltage VIN has a line transient (linear transient change), the power-on protection circuit senses the change slope of the power supply voltage VIN to turn on the pull-up tube Q2 and turn off the power tube Q1, so that the short-term power failure of the voltage VCC is caused, the severity depends on the slope of the line transient, and further logic errors, such as triggering a reset POR and restarting, are all undesirable for the system, due to the power failure time. Fig. 2 shows that the voltage VCC generates a severe power loss when the power supply voltage VIN is changed from 3V to 45V at a rate of 1V/1 us.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide an LDO circuit and a chip, which can prevent the output voltage of the LDO circuit from generating power-on overshoot when the power supply voltage is powered on, and can also ensure that the output voltage of the LDO circuit does not generate power failure when the power supply voltage generates linear transient change.
To achieve the above object, an embodiment of the present invention provides an LDO circuit, including: the differential amplifier, the first power tube, the voltage control circuit, the feedback circuit, the second power tube and the voltage division control circuit;
the control end of the first power tube is connected with the output end of the differential amplifier, the second end of the first power tube is connected with the power supply voltage, the first end of the first power tube is connected with the feedback circuit to generate output voltage, the feedback circuit generates feedback voltage based on the output voltage, the first input end of the differential amplifier is used for receiving the reference voltage, and the second input end of the differential amplifier is used for receiving the feedback voltage;
the voltage control circuit is connected with the control end of the first power tube and the power supply voltage, the voltage control circuit is used for controlling the voltage of the control end of the first power tube to follow the change of the power supply voltage, the first end of the second power tube is connected with the first end of the first power tube, the second end of the second power tube is connected with the power supply voltage, the control end of the second power tube is connected with the voltage division control circuit, and the voltage division control circuit is used for generating the control voltage for controlling the second power tube based on the control signal.
In one or more embodiments of the invention, the second power tube has a greater aspect ratio than the first power tube.
In one or more embodiments of the present invention, the aspect ratio of the second power tube is 7 to 12 times that of the first power tube.
In one or more embodiments of the present invention, the voltage division control circuit includes a voltage division unit and a switching unit, the switching unit is connected to the voltage division unit, the switching unit is used for controlling the on and off of the voltage division unit, the voltage division unit is connected to the power supply voltage and the control terminal of the second power tube, and the voltage division unit is used for generating the first control voltage and the second control voltage to the control terminal of the second power tube based on the on and off of the voltage division unit so as to turn on or off the second power tube.
In one or more embodiments of the present invention, the voltage dividing unit includes a first voltage dividing resistor and a second voltage dividing resistor, a first end of the first voltage dividing resistor is connected to a power supply voltage, a second end of the first voltage dividing resistor is connected to a control end of the second power tube, the second voltage dividing resistor is connected in series with the switch unit and is connected between the control end of the second power tube and a ground voltage, and the switch unit is used for controlling connection and disconnection of a current path between the second voltage dividing resistor and the control end of the second power tube; or alternatively
The first voltage dividing resistor is connected in series with the switch unit and is connected between the power supply voltage and the control end of the second power tube, the switch unit is used for controlling the connection and disconnection of a current path between the first voltage dividing resistor and the control end of the second power tube, the first end of the second voltage dividing resistor is connected with the control end of the second power tube, and the second end of the second voltage dividing resistor is connected with the ground voltage.
In one or more embodiments of the present invention, the switching unit includes a switching tube, and a control terminal of the switching tube receives a control signal to turn on or off the voltage dividing unit.
In one or more embodiments of the present invention, the voltage control circuit includes a current mirror and a controllable current source, the controllable current source is used for generating a compensation current based on the second control signal, the current mirror is connected with the controllable current source, the power supply voltage and the control end of the first power tube, and the current mirror is used for injecting the compensation current into the control end of the first power tube when the power supply voltage is powered up.
In one or more embodiments of the present invention, the voltage control circuit further includes a first capacitor, a first end of the first capacitor is connected to the control end of the first power tube, and a second end of the first capacitor is connected to the second end of the first power tube.
In one or more embodiments of the invention, the LDO circuit further includes a second capacitor, a first end of the second capacitor being connected to a first end of the second power tube, and a second end of the second capacitor being connected to a ground voltage.
The invention also discloses a chip comprising the LDO circuit.
Compared with the prior art, according to the LDO circuit and the chip provided by the embodiment of the invention, in the power supply voltage powering-on stage, the voltage control circuit controls the voltage of the control end of the first power tube to turn off the first power tube along with the power supply voltage powering-on variation, so that the output voltage output by the LDO circuit is prevented from being powered on to overshoot, and meanwhile, the voltage division control circuit is turned off through the control signal so that the second power tube is turned off and does not participate in the powering-on stage; and when the power supply voltage is powered on, the voltage control circuit is turned off, and meanwhile, when the power supply voltage is subjected to linear transient change or strong driving capability is required to be provided by the LDO circuit, the voltage division control circuit is turned on through a control signal so as to enable the second power tube to be turned on, and the functions of resetting, soft starting and the like are prevented from being triggered due to output power failure caused by mistakenly turning off the first power tube of the LDO circuit when the power supply voltage is subjected to linear transient change.
Drawings
Fig. 1 is a circuit schematic of an LDO circuit according to the prior art.
Fig. 2 is a waveform diagram of the voltage at each node and the output voltage of an LDO circuit according to the prior art.
Fig. 3 is a circuit schematic of an LDO circuit according to an embodiment of the invention.
FIG. 4 is a waveform diagram of the voltage at each node and the output voltage of an LDO circuit according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
As shown in fig. 3, an LDO circuit includes: the differential amplifier OPAMP, the first power transistor Q1, the voltage control circuit 10, the feedback circuit 20, the second power transistor Q2, and the voltage division control circuit 30.
The control end of the first power tube Q1 is connected to the output end of the differential amplifier OPAMP, the second end of the first power tube Q1 is connected to the power voltage VIN, the first end of the first power tube Q1 is connected to the feedback circuit 20 to form the output end VOUT of the LDO circuit, so as to generate the output voltage VCC, and the feedback circuit 20 generates the feedback voltage based on the output voltage VCC. The first input terminal of the differential amplifier OPAMP is for receiving the reference voltage and the second input terminal of the differential amplifier OPAMP is for receiving the feedback voltage.
The feedback circuit 20 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected with the first end of the first power tube Q1, the second end of the first resistor R1 is connected with the first end of the second resistor R2 to generate feedback voltage based on the output voltage VCC, and the second end of the second resistor R2 is connected with the ground voltage.
In one embodiment, the first power transistor Q1 is a P-channel MOS transistor, the first end of the first power transistor Q1 is a drain electrode, the second end of the first power transistor Q1 is a source electrode, and the control end of the first power transistor Q1 is a gate electrode, and in other embodiments, the first power transistor Q1 may be an N-channel MOS transistor.
The voltage control circuit 10 is connected to the control terminal of the first power transistor Q1 and the power voltage VIN, and the voltage control circuit 10 is configured to control the voltage of the control terminal of the first power transistor Q1 to follow the power voltage VIN when the power voltage VIN is powered on. The first end of the second power tube Q2 is connected with the first end of the first power tube Q1, the second end of the second power tube Q2 is connected with the power voltage VIN, the control end of the second power tube Q2 is connected with the voltage division control circuit 30, and the voltage division control circuit 30 is used for generating control voltage based on control signals after the power voltage VIN is electrified so that the second power tube Q2 is started.
In one embodiment, the second power transistor Q2 is a P-channel MOS transistor, the first end of the second power transistor Q2 is a drain, the second end of the second power transistor Q2 is a source, and the control end of the second power transistor Q2 is a gate, and in other embodiments, the second power transistor Q2 and the first power transistor Q1 may be the same N-channel MOS transistor.
The first power tube Q1 and the second power tube Q2 are P-channel MOS tubes, or the first power tube Q1 and the second power tube Q2 may be N-channel MOS tubes. The MOS tubes with the same type channels are adopted, so that the MOS tubes have good matching degree when the first power tube Q1 and the second power tube Q2 are simultaneously started.
As shown in fig. 3, the voltage control circuit 10 includes a current mirror, a controllable current source I1, and a first capacitor C1. The controllable current source I1 is configured to generate a compensation current based on the second control signal, and in a power-up stage of the power supply voltage VIN, the controllable current source I1 is turned on by the second control signal to generate the compensation current, and after the power-up is finished, the controllable current source I1 is turned off by the second control signal, that is, the voltage control circuit 10 can be turned on and off by the second control signal. The current mirror is connected with the controllable current source I1, the power voltage VIN and the control end of the first power tube Q1, and is used for injecting compensation current into the control end of the first power tube Q1 when the power voltage VIN is powered on. The first end of the first capacitor C1 is connected with the control end of the first power tube Q1, and the second end of the first capacitor C1 is connected with the second end of the first power tube Q1.
The current mirror comprises a first MOS tube Q4 and a second MOS tube Q5. The control end of the first MOS tube Q4 is connected with the control end of the second MOS tube Q5, the control end of the first MOS tube Q4 is connected with the drain electrode of the first MOS tube Q4 and the controllable current source I1, and the second end of the first MOS tube Q4 is connected with the second end of the second MOS tube Q5 and the power supply voltage VIN.
In one embodiment, the width-to-length ratio of the first MOS transistor Q4 and the second MOS transistor Q5 is the same, and the compensation current is one hundred to four hundred milliamperes. In the power-on stage of the power supply voltage VIN, the first MOS transistor Q4 is used as a pull-up MOS transistor to enable the voltage of the control end of the first power transistor Q1 to rise along with the rising of the power supply voltage VIN, so as to avoid the overshoot of the output voltage VCC of the output end VOUT, and the voltage control circuit 10 is turned off when the power supply voltage VIN is stable; the coupling capability between the control end of the first power tube Q1 and the power voltage VIN is increased through the first capacitor C1, so that the first power tube Q1 is turned off in the power-on stage of the power voltage VIN, and the overshoot of the output voltage VCC of the output end VOUT is avoided. In other embodiments, the first capacitor C1 may not be provided.
As shown in fig. 3, the voltage division control circuit 30 includes a voltage division unit 31 and a switching unit 32. The switching unit 32 is connected to the voltage dividing unit 31, the switching unit 32 is used for controlling the voltage dividing unit 31 to be turned on and off, the voltage dividing unit 31 is connected to the power voltage VIN and the control end of the second power tube Q2, and the voltage dividing unit 31 is used for generating a first control voltage and a second control voltage to the control end of the second power tube Q2 based on the turn-on and turn-off of the voltage dividing unit 31 to turn on or turn off the second power tube Q2.
Specifically, the voltage dividing unit 31 includes a first voltage dividing resistor R3 and a second voltage dividing resistor R4, a first end of the first voltage dividing resistor R3 is connected to the power supply voltage VIN, a second end of the first voltage dividing resistor R3 is connected to the control end of the second power tube Q2, the second voltage dividing resistor R4 is connected in series with the switch unit 32 and is connected between the control end of the second power tube Q2 and the ground voltage, and the switch unit 32 is used for controlling the connection and disconnection of the current path between the second voltage dividing resistor R4 and the control end of the second power tube Q2.
In other embodiments, the first voltage dividing resistor R3 may be connected in series with the switching unit 32 and connected between the power supply voltage VIN and the control terminal of the second power tube Q2, where the switching unit 32 is configured to control the connection and disconnection of the current path between the first voltage dividing resistor R3 and the control terminal of the second power tube Q2, and the first terminal of the second voltage dividing resistor R4 is connected to the control terminal of the second power tube Q2, and the second terminal of the second voltage dividing resistor R4 is connected to the ground voltage.
In an embodiment, the switching unit 32 includes a switching tube Q3, a first end of the switching tube Q3 is connected to a second end of the second voltage dividing resistor R4, a second end of the switching tube Q3 is connected to the ground voltage, a control end of the switching tube Q3 receives the first control signal VCTRL to turn on or off the voltage dividing unit 31, and the switching tube Q3 may also be connected in series between the control end of the second power tube Q2 and the first end of the second voltage dividing resistor R4. The switching tube Q3 is an N-channel MOS tube, the first end of the switching tube Q3 is a drain electrode, the second end of the switching tube Q3 is a source electrode, and the control end of the switching tube Q3 is a grid electrode. In other embodiments, the switching transistor Q3 may be a P-channel MOS transistor.
The LDO circuit further comprises a second capacitor C2, a first end of the second capacitor C2 is connected with a first end of the second power tube Q2, and a second end of the second capacitor C2 is connected with a ground voltage. The second capacitor C2 is used as a load capacitor for filtering the ripple of the output voltage VCC of the output terminal VOUT.
In one embodiment, the width-to-length ratio of the second power transistor Q2 is greater than the width-to-length ratio of the first power transistor Q1. The width-to-length ratio of the second power tube Q2 is 7-12 times that of the first power tube Q1, and preferably, the width-to-length ratio of the second power tube Q2 is 9 times that of the first power tube Q1.
Therefore, the driving capability of the second power tube Q2 is stronger than that of the first power tube Q1, the first power tube Q1 is a small power tube for power-up, and the second power tube Q2 is a large power tube for strong driving to cope with the line transient and the situation of requiring large current.
Specifically, in the power-on stage of the power supply voltage VIN, the first control signal VCTRL is at a low level, so that the control end of the second power transistor Q2 is pulled up to the power supply voltage VIN through the first voltage dividing resistor R3, and the second power transistor Q2 is in an off state and does not participate in the power-on overshoot. In the power-up phase of the power supply voltage VIN, the first power transistor Q1 is turned off under the control of the voltage control circuit 10, so as to prevent power-up overshoot.
When the power-on of the power supply voltage VIN is completed and a stronger driving capability is required or the power supply voltage VIN generates line transient, for example, when a fuse is burned or more current is required to be driven, the corresponding first control signal VCTRL jumps to be high, the first control signal VCTRL controls the high-voltage switch Q3 to be turned on, the voltage of the control end of the second power transistor Q2 at this time is determined by the first voltage dividing resistor R3 and the second voltage dividing resistor R4, and since the resistance value of the second voltage dividing resistor R4 is stronger (the resistance value of the second voltage dividing resistor R4 is about 1/10 times that of the first voltage dividing resistor R3, for example, r4=20k, r3=200k), the second power transistor Q2 is turned on to participate in the output of the LDO circuit, and the output of the LDO circuit cannot generate a power failure condition.
As shown in fig. 4, in the power-up stage of the power supply voltage VIN, the output voltage VCC generated by the LDO circuit does not overshoot, and in the power supply voltage VIN, the output voltage VCC does not generate power down, and the power tube in the LDO circuit is not turned off.
The invention also discloses a chip comprising the LDO circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. An LDO circuit, comprising: the differential amplifier, the first power tube, the voltage control circuit, the feedback circuit, the second power tube and the voltage division control circuit;
the control end of the first power tube is connected with the output end of the differential amplifier, the second end of the first power tube is connected with the power supply voltage, the first end of the first power tube is connected with the feedback circuit to generate output voltage, the feedback circuit generates feedback voltage based on the output voltage, the first input end of the differential amplifier is used for receiving the reference voltage, and the second input end of the differential amplifier is used for receiving the feedback voltage;
the voltage control circuit is connected with the control end of the first power tube and the power supply voltage, the voltage control circuit is used for controlling the voltage of the control end of the first power tube to follow the change of the power supply voltage, the first end of the second power tube is connected with the first end of the first power tube, the second end of the second power tube is connected with the power supply voltage, the control end of the second power tube is connected with the voltage division control circuit, and the voltage division control circuit is used for generating the control voltage for controlling the second power tube based on the first control signal.
2. The LDO circuit of claim 1, wherein the second power transistor has a greater aspect ratio than the first power transistor.
3. The LDO circuit of claim 2, wherein the second power transistor has a width to length ratio of 7-12 times that of the first power transistor.
4. The LDO circuit of claim 1, wherein the voltage division control circuit comprises a voltage division unit and a switching unit, the switching unit is connected with the voltage division unit, the switching unit is used for controlling the opening and closing of the voltage division unit, the voltage division unit is connected with the power supply voltage and the control end of the second power tube, and the voltage division unit is used for generating the first control voltage and the second control voltage to the control end of the second power tube based on the opening and closing of the voltage division unit so as to open or close the second power tube.
5. The LDO circuit of claim 4, wherein the voltage dividing unit comprises a first voltage dividing resistor and a second voltage dividing resistor, a first end of the first voltage dividing resistor is connected with a power supply voltage, a second end of the first voltage dividing resistor is connected with a control end of the second power tube, the second voltage dividing resistor is connected in series with the switching unit and is connected between the control end of the second power tube and the ground voltage, and the switching unit is used for controlling the connection and disconnection of a current path between the second voltage dividing resistor and the control end of the second power tube; or alternatively
The first voltage dividing resistor is connected in series with the switch unit and is connected between the power supply voltage and the control end of the second power tube, the switch unit is used for controlling the connection and disconnection of a current path between the first voltage dividing resistor and the control end of the second power tube, the first end of the second voltage dividing resistor is connected with the control end of the second power tube, and the second end of the second voltage dividing resistor is connected with the ground voltage.
6. The LDO circuit of claim 4, wherein the switching unit comprises a switching tube, a control terminal of the switching tube receiving a first control signal to turn on or off a voltage dividing unit.
7. The LDO circuit of claim 1, wherein the voltage control circuit comprises a current mirror and a controllable current source, the controllable current source to generate the compensation current based on the second control signal, the current mirror coupled to the controllable current source, the supply voltage, and the control terminal of the first power transistor, the current mirror to inject the compensation current into the control terminal of the first power transistor when the supply voltage is powered up.
8. The LDO circuit of claim 7, wherein the voltage control circuit further comprises a first capacitor, a first terminal of the first capacitor being coupled to the control terminal of the first power tube, a second terminal of the first capacitor being coupled to the second terminal of the first power tube.
9. The LDO circuit of claim 1, further comprising a second capacitor, a first terminal of the second capacitor connected to a first terminal of a second power transistor, a second terminal of the second capacitor connected to a ground voltage.
10. A chip comprising an LDO circuit according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311414104.2A CN117348664A (en) | 2023-10-27 | 2023-10-27 | LDO circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311414104.2A CN117348664A (en) | 2023-10-27 | 2023-10-27 | LDO circuit and chip |
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| Publication Number | Publication Date |
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| CN117348664A true CN117348664A (en) | 2024-01-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311414104.2A Pending CN117348664A (en) | 2023-10-27 | 2023-10-27 | LDO circuit and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118363420A (en) * | 2024-06-20 | 2024-07-19 | 上海芯炽科技集团有限公司 | Turnover type voltage follower control type LDO |
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2023
- 2023-10-27 CN CN202311414104.2A patent/CN117348664A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118363420A (en) * | 2024-06-20 | 2024-07-19 | 上海芯炽科技集团有限公司 | Turnover type voltage follower control type LDO |
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