CN113470720B - Discharge circuit and discharge control circuit system of memory - Google Patents
Discharge circuit and discharge control circuit system of memory Download PDFInfo
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- CN113470720B CN113470720B CN202110733219.2A CN202110733219A CN113470720B CN 113470720 B CN113470720 B CN 113470720B CN 202110733219 A CN202110733219 A CN 202110733219A CN 113470720 B CN113470720 B CN 113470720B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Abstract
The application provides a discharge circuit and a discharge control circuit system. The discharge circuit includes: the common-gate input module comprises a first input branch and a second input branch, wherein the first end of the first input branch is connected to the discharge power supply end, and the first end of the second input branch is connected to the power supply end; a driving current module configured to provide a first driving current to the first branch and a second driving current to the second branch; a first resistor connected between a power supply terminal and a discharge power terminal; and a control end of the discharge switch tube is connected to the second end of the first input branch, the first end of the discharge switch tube is connected to a discharge power supply end, and the second end of the discharge switch tube is connected to a grounding end. The discharge current and discharge control circuit system can ensure that the device at the power supply end is in a safe working area, and can avoid influencing the voltage stability of the power supply end in the discharge process of the power supply end.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and more particularly, to a discharge circuit and a discharge control circuitry of a memory.
Background
In a flash memory, in order to implement operations such as programming or reading of memory cells, a programming voltage or a reading voltage higher than a power supply voltage is generally applied to a control line of a memory cell such as a Word Line (WL) or a Bit Line (BL) by using, for example, a charge pump circuit, so as to implement the operations such as programming or reading of the memory cell corresponding to the control line. Accordingly, after the memory cell performs a program or read operation, a corresponding control line of the memory cell needs to be discharged.
In the conventional memory, the discharge operation of the control line is mostly passive discharge, and in this discharge operation, the control line (e.g., word line) is directly connected to the power supply terminal, so that the control line is discharged to the same target voltage value as the voltage value of the power supply terminal. However, during the discharge operation, since the control line is directly connected to the power supply terminal, the voltage at the power supply terminal may fluctuate, and at the same time, the device at the power supply terminal may be separated from its Safe Operating Area (SOA), thereby affecting the device reliability at the power supply terminal.
Therefore, how to solve the above problems of the control line in the discharging process is one of the problems that the skilled person has been trying to solve.
Disclosure of Invention
One aspect of the present application provides a discharge circuit. The discharge circuit includes: the common-gate input mirror module comprises a first input branch and a second input branch, wherein the first end of the first input branch is connected to a discharge power supply end, and the first end of the second input branch is connected to a power supply end; a driving current module configured to provide a first driving current to the first branch and a second driving current to the second input branch; a first resistor connected between a power supply terminal and a discharge power terminal; and a control end of the discharge switch tube is connected to the second end of the first input branch, the first end of the discharge switch tube is connected to a discharge power supply end, and the second end of the discharge switch tube is connected to a grounding end.
In some embodiments, the discharge circuit further comprises a second resistor connected between the first terminal of the first input branch and the discharge power supply terminal.
In some embodiments, the resistance value of the second resistor is adjustable and configured to discharge the discharge power terminal to a target voltage value according to the resistance value thereof.
In some embodiments, the discharge switching tube is configured to discharge the discharge power terminal to a voltage value of the power supply terminal.
In some embodiments, the discharge switching tube is configured to connect the discharge power terminal and the ground terminal in a case where the voltage value Vdis of the discharge power terminal, the voltage value Vdd of the power supply power terminal, the current value I1 of the first driving current, and the resistance value R2 of the second resistor satisfy Vdis > Vdd + I1 × R2.
In some embodiments, the first input branch comprises a first transistor, and the second input branch comprises a second transistor, wherein the control terminals of the first transistor and the second transistor are connected, and the control terminal of the second transistor is connected with the second terminal of the second transistor; the first end of the first transistor is connected to the second resistor, and the first end of the second transistor is connected to a power supply end; the second terminal of the first transistor is applied with a first driving current, and the second terminal of the second transistor is applied with a second driving current.
In some embodiments, the first transistor and the second transistor are both PMOS transistors or PNP transistors.
In some embodiments, the discharge switch tube is an NMOS transistor or an NPN transistor.
In some embodiments, the drive current module includes a current mirror.
In some embodiments, the drive current module includes: and the second ends of the third transistor and the fourth transistor are grounded, the control ends of the third transistor and the fourth transistor are connected with each other and used for receiving a control voltage, the first end of the fourth transistor is connected with the second end of the second transistor, and the first end of the third transistor is connected with the second end of the first transistor.
In some embodiments, the third transistor and the fourth transistor are both NMOS transistors or NPN transistors.
Another aspect of the present application provides a discharge control circuit system of a memory, including: the discharge circuit as described in any of the above embodiments, wherein the driving current module of the discharge circuit has an input control terminal; and the master control switch tube is connected between the discharge power supply end and the discharge circuit, and the control end of the master control switch tube is connected with the input control end, wherein the power supply end is the power supply end of the memory, and the discharge power supply end is the control line of the memory.
According to the discharge circuit and the discharge control circuit system of the memory, the discharge path is provided for the discharge power supply end, active discharge of the discharge power supply end can be achieved, and the discharge intensity of the discharge power supply end depends on the equivalent resistance of the control line. In addition, the resistors are arranged at the discharging power supply end and the power supply end, so that the discharging power supply end is prevented from being directly connected with the power supply end in the discharging process, the device at the power supply end is ensured to be in a safe working area, and the influence on the voltage stability of the power supply end in the discharging process of the discharging power supply end can be avoided.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a block diagram of a discharge circuit according to an embodiment of the present application;
FIG. 2 is a circuit diagram of the exemplary discharge circuit shown in FIG. 1;
FIG. 3 is a block diagram of a discharge circuit according to another embodiment of the present application;
FIG. 4 is a circuit diagram of a discharge circuit of the exemplary memory shown in FIG. 3; and
fig. 5 is a circuit diagram of discharge control circuitry according to an embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.
The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.
This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a block diagram of a discharge circuit 100 according to an embodiment of the present application. As shown in fig. 1, the discharge circuit 100 includes: the driving circuit comprises a common gate input module 110, a driving current module 120, a first resistor R1 and a discharge switching tube Qdis.
The common gate input module 110 includes a first input branch 111 and a second input branch 112. The first terminal of the first input branch 111 is connected to the discharge power supply terminal Vdis, and the first terminal of the second input branch 112 is connected to the supply power supply terminal Vdd. The power supply terminal Vdd may be a power supply terminal of the memory and supply a power supply voltage to a control line such as a word line or a bit line. The discharge power source terminal Vdis may be a control line, such as a word line or a bit line, corresponding to a memory cell in the memory. After a high voltage is applied to the memory cell through the control line to perform, for example, a programming operation, the control line corresponding to the memory cell needs to be discharged, and thus the control line corresponding to the memory cell can be equivalent to a discharging power source terminal. And in the discharging process of the discharging power supply end Vdis, the discharging power supply end Vdis can be equivalent to a capacitor and a resistor which are connected in series.
The driving current module 120 provides a first driving current I1 for the first input branch 111 and a second driving current I2 for the second input branch 112 in the common-gate input module 110. For example, the driving current module 120 may be connected between the common-gate input module 110 and a ground terminal, and may enable the first driving current I1 and the second driving current I2 to respectively flow through the first input branch 111 and the second input branch 112 in the common-gate input module 110. In other words, the common-gate input module 110 can ground the first input branch 111 and the second input branch 112 through the driving current module 120, so that the first input branch 111 and the second input branch 112 form a circuit loop with a ground terminal.
The first resistor R1 is connected between the power supply end Vdd and the discharge end Vdis, so that a circuit loop with impedance can be formed between the discharge end Vdis and the power supply end Vdd under the condition that the discharge switching tube Qdis is switched on, the direct connection between the power supply end Vdd and the discharge end Vdis is avoided, the device of the power supply end Vdd is ensured to be in a safe working area, and the voltage stability of the power supply end Vdd can be prevented from being influenced in the discharge process of the discharge end Vdis.
The control terminal of the discharge switching tube Qdis is connected to the second terminal of the first input branch 111, the first terminal thereof is connected to the discharge power terminal Vdis, the second terminal thereof is connected to the ground terminal, and is configured to control the connection of the discharge power terminal Vdis and the ground terminal. Illustratively, the control terminal of the discharge switching tube Qdis may be connected between the second terminal of the first input branch 111 and the driving current module 120, and control the connection of the discharge power terminal Vdis and the ground terminal according to the voltage of the second terminal of the first input branch 111. In other words, when the discharge switching tube Qdis is turned on, the discharge power source terminal Vdis is grounded through the discharge switching tube Qdis, thereby discharging the discharge power source terminal Vdis.
It is understood that the second input branch 112 of the common-gate input module 110 is connected to the power supply terminal Vdd, so that the power supply terminal Vdd, the second input branch 112 and the driving current module 120 form a circuit loop. In the process of performing the discharging operation on the discharging power source terminal Vdis, since the first input branch 111 and the second input branch 112 are a common-gate input pair, and the voltage value of the discharging power source terminal Vdis and the voltage value of the power supply terminal Vdd satisfy the predetermined condition, the discharging power source terminal Vdis, the first input branch 111 and the driving current module 120 can form a circuit loop, so that the voltage value of the control terminal of the discharging switching tube Qdis connected to the second terminal of the first input branch 111 is changed, and the discharging switching tube Qdis can be turned on, so that the discharging power source terminal Vdis connected to the ground terminal Vss, and the active discharging of the discharging power source terminal Vdis is realized.
According to the discharge circuit provided in the embodiment of the present application, the active discharge of the discharge power source terminal can be achieved by providing the discharge path for the discharge power source terminal, and since the discharge power source terminal is directly connected to the ground terminal through the discharge path, the discharge intensity of the discharge power source terminal depends on the equivalent resistance of the load and the control line of the discharge path. In addition, the resistors are arranged at the discharging power supply end and the power supply end, so that the discharging power supply end is prevented from being directly connected with the power supply end in the discharging process, the device at the power supply end is ensured to be in a safe working area, and the influence on the voltage stability of the power supply end in the discharging process of the discharging power supply end can be avoided.
In some embodiments, in case that the voltage value of the discharging power source terminal Vdis and the voltage value of the power source terminal Vdd satisfy Vdis > Vdd, the discharging power source terminal Vdis may form a circuit loop through the first input branch 111 and the driving current module 120, thereby turning on the discharging switching tube Qdis and connecting the discharging power source terminal Vdis and the ground terminal Vss. In this embodiment, the voltage value of the first terminal of the first input branch 111 should be greater than the voltage value of the first terminal of the second input branch 112. In other words, when the first input branch 111 of the common-gate input module 110 is turned on, the voltage value of the first end of the first input branch 111 should be greater than the voltage value of the power supply terminal Vdd, and it is ensured that the first input branch 111 of the common-gate input module 110 is turned on, so as to ensure that the discharging power terminal Vdis forms a circuit loop through the first branch 111 and the driving current module 120.
Fig. 2 is an exemplary circuit diagram of the discharge circuit 100 shown in fig. 1. As shown in fig. 2, the first input branch 111 of the common-gate input module 110 may include a first transistor Q1, and the second input branch 112 may include a second transistor Q2. The control terminals of the first transistor Q1 and the second transistor Q2 are connected, and the control terminal of the second transistor Q2 is connected with the second terminal of the second transistor Q2. A first terminal of the first transistor Q1 is connected to the discharge power supply terminal Vdis, and a first terminal of the second transistor Q2 is connected to the power supply terminal Vdd. The first driving current I1 is applied to the second terminal of the first transistor Q1, and the second driving current I2 is applied to the second terminal of the second transistor Q2. Optionally, the first transistor Q1 and the second transistor Q2 are matched PMOS transistors or PNP transistors. The first transistor Q1 and the second transistor Q2 in the embodiment of the present application are implemented by using CMOS devices, because CMOS matching is superior. And first terminals of the first and second transistors Q1 and Q2 are source terminals, and second terminals of the first and second transistors Q1 and Q2 are drain terminals.
In some embodiments, the driving current module 120 may include: a third transistor Q3 and a fourth transistor Q4. Second terminals of the third transistor Q3 and the fourth transistor Q4 are connected to a ground terminal Vss, control terminals of the third transistor Q3 and the fourth transistor Q4 are connected to each other and used to receive a control voltage, a first terminal of the fourth transistor Q4 is connected to a second terminal of the second transistor Q2, and a first terminal of the third transistor Q3 is connected to a second terminal of the first transistor Q1. Alternatively, the third transistor Q3 and the fourth transistor Q4 are both NMOS transistors or NPN transistors. Similarly, the third transistor Q3 and the fourth transistor Q4 in the embodiment of the present application are implemented by CMOS devices because the matching of the complementary metal oxide semiconductors is superior. And first terminals of the third transistor Q3 and the fourth transistor Q4 are drain terminals and second terminals of the third transistor Q3 and the fourth transistor Q4 are source terminals. After the control voltage is applied to the control terminals of the third and fourth transistors Q3 and Q4, the third and fourth transistors Q3 and Q4 may be turned on and the first and second driving currents I1 and I2 may be supplied.
In some embodiments, the driving current module 120 may further be implemented by any one of current mirror circuits to provide the first driving current I1 for the first transistor Q1 and provide the second driving current I2 for the second transistor Q2, and the current mirror structure in the driving current module 120 is not specifically limited in this application. It is understood that, in the case that the driving current module 120 is implemented by using a current mirror circuit, the first driving current I1 and the second driving current I2 may be mirror currents of the reference current. When the first transistor Q1 in the first input branch 111 is turned on, the discharge power source terminal Vdis may be connected to the ground terminal through the first transistor Q1 and the third transistor Q3, thereby forming a circuit loop. The voltage value of the discharge power supply end Vdis divided by the first transistor Q1 can turn on the discharge switching tube Qdis, so that the discharge power supply end Vdis is connected with the ground terminal Vss through the discharge switching tube Qdis, and active discharge of the discharge power supply end Vdis further realized.
It should be understood that the current values of the first driving circuit I1 and the second driving circuit I2 may be the same or different, and the present application is not particularly limited thereto. And the current values of the first and second driving currents I1 and I2 can be made different by selecting the third and fourth transistors Q3 and Q4 with different performance parameters.
In some embodiments, the discharge switching tube Qdis may be an NMOS transistor or an NPN transistor. The discharge switching tube Qdis in the embodiment of the present application is implemented by a CMOS device. And the source terminal of the discharge switching tube Qdis is grounded, and the drain terminal of the discharge switching tube Qdis is connected to the discharge power source terminal Vdis. Under the condition that the discharge power source terminal Vdis is connected to the ground terminal through the first transistor Q1 and the third transistor Q3 to form a circuit loop, a difference between a voltage value of the discharge power source terminal Vdis divided by the first transistor Q1 (a voltage value of a gate terminal of the discharge switching tube Qdis) and a voltage value of a source terminal of the discharge switching tube Qdis may be greater than a threshold voltage of the discharge switching tube Qdis, so that the discharge switching tube Qdis is turned on, and the discharge power source terminal Vdis is connected to the ground terminal through the discharge switching tube Qdis to discharge the discharge power source terminal Vdis.
It is understood that the specific circuit structures and the types of the components of the common-gate input module 110, the driving current module 120 and the main control switch Qdis in the embodiment of the present application are not specifically limited, and it is within the protection scope of the present application as long as the voltage value divided by the first input branch 111 of the common-gate input module 110 is satisfied to enable the main control switch Qdis to control the connection between the discharging power terminal Vdis and the ground terminal Vss.
Fig. 3 is a block diagram of a discharge circuit 100' according to another embodiment of the present application. As shown in fig. 3, the discharge circuit 100' of the present embodiment further includes a second resistor R2, as compared to the discharge circuit 100. Since other circuit structures in the discharge circuit 100 'are completely the same as those described in the discharge circuit 100, descriptions of other circuit structures in the discharge circuit 100' are omitted and the same reference numerals are used to refer to the same circuit structures.
The second resistor R2 is connected between the first terminal of the first input branch 111 and the discharge power terminal Vdis. In other words, the first input branch 111 is connected to the discharge power terminal Vdis through the second resistor R2. Specifically, one end of the second resistor R2 is connected to the discharge power source terminal Vdis, and the other end of the second resistor R2 is connected to the first branch 111.
Similarly, in the discharging operation performed by the discharging power terminal Vdis, since the first input branch 111 and the second input branch 112 are a common-gate input pair, the voltage value of the discharging power terminal Vdis, the voltage value of the power supply terminal Vdd, the first driving current I1 and the second resistor R2 can make the discharging power terminal Vdis, the first input branch 111 and the driving current module 120 form a circuit loop under the condition that a predetermined condition is satisfied, so that the voltage value of the control terminal of the discharging switch tube Qdis connected to the second terminal of the first input branch 111 changes, and the discharging switch tube Qdis can be turned on, so that the discharging power terminal Vdis connected to the ground terminal Vss, thereby implementing the active discharging of the discharging power terminal Vdis.
In some embodiments, in the case that the voltage value of the discharge power terminal Vdis, the voltage value of the power supply power terminal Vdd, the current value of the first driving current I1, and the resistance value of the second resistor R2 satisfy Vdis > Vdd + I1 × R2, the discharge power terminal Vdis may form a circuit loop through the second resistor R2, the first input branch 111, and the driving current module 120, so as to turn on the discharge switching tube Qdis and connect the discharge power terminal Vdis and the ground terminal Vss. In this embodiment, the voltage value of the end of the first input branch 111 connected to the second resistor R2 should be greater than the voltage value of the end of the second branch 112 connected to the supply terminal Vdd. In other words, when the first input branch 111 of the common-gate input module 110 is turned on, the voltage value of the end of the first input branch 111 connected to the second resistor R2 should be greater than the voltage value of the power supply terminal Vdd, and it is ensured that the first input branch 111 of the common-gate input module 110 is turned on, so as to ensure that the discharge power terminal Vdis forms a circuit loop through the second resistor R2, the first input branch 111 and the driving current module 120. In a case that the discharging power source terminal Vdis forms a circuit loop through the second resistor R2, the first input branch 111 and the driving current module 120, since the driving current module 120 applies the first driving current I1 to the first input branch 111, a current flowing through the second resistor R2 should also be the first driving current I1, and a voltage division of the second resistor R2 should be I1 × R2. Therefore, the voltage value of the end of the second resistor R2 connected to the discharge power source terminal Vdis should be greater than Vdd + I1 × R2, in other words, under the condition that the conditional expression Vdis > Vdd + I1 × R2 is satisfied, the first input branch 111 of the common-gate input module 110 is turned on, so that the discharge power source terminal Vdis forms a circuit loop through the second resistor R2, the first input branch 111, and the driving current module 120, and the discharge switch is turned on, and active discharge of the discharge power source terminal Vdis is realized.
In some embodiments, the resistance of the second resistor R2 may be adjusted according to the specific value of the discharge power source terminal Vdis that needs to be discharged to the target voltage value. Based on the conditional expression described above that the voltage value of the discharge power source terminal Vdis needs to satisfy, the discharge power source terminal Vdis can be discharged to a required target voltage value by appropriately setting the resistance value of the second resistor R2. It should be noted that the discharging power source terminal Vdis can be discharged to the required target voltage value by properly setting the current value of the first driving current I1.
In the conventional method of directly connecting the discharge power terminal and the power supply power terminal, so that the discharge capability of the discharge power terminal is relatively fixed, the target voltage value of discharge of the discharge power terminal cannot be adaptively adjusted according to process variations of devices on a discharge path, and the discharge intensity of the discharge power terminal depends on the on-resistance of the devices on the discharge path. The discharge circuit provided by the embodiment of the application can at least partially solve the technical problem, and the discharge power supply end Vdis can discharge to the preset target voltage value by adjusting the resistance value of the second resistor R2, so that the adaptability of the target voltage value to the process deviation of the device is improved. Meanwhile, the reliability of the memory cell corresponding to the discharge power source terminal (control line) can be improved by adjusting the target voltage value of the discharge power source terminal.
For example, the resistance value of the second resistor R2 may be 0-20K Ω, so that the discharge power source terminal Vdis is discharged to a target voltage value in a corresponding voltage interval of 2.2-2.5V. It should be noted that, when the resistance value of the second resistor R2 is zero, the discharge circuit 100' in the embodiment of the present application may have the same circuit structure as the discharge circuit 100.
Fig. 4 is an exemplary circuit diagram of the discharge circuit 100' shown in fig. 3. As shown in fig. 4, the first input branch 111 of the common-gate input module 110 may include a first transistor Q1, and the second input branch 112 may include a second transistor Q2. The control terminals of the first transistor Q1 and the second transistor Q2 are connected, and the control terminal of the second transistor Q2 is connected to the second terminal of the second transistor Q2. A first terminal of the first transistor Q1 is connected to the second resistor R2, and a first terminal of the second transistor Q2 is connected to the power supply terminal Vdd. The first driving current I1 is applied to the second terminal of the first transistor Q1, and the second driving current I2 is applied to the second terminal of the second transistor Q2. Optionally, the first transistor Q1 and the second transistor Q2 are matched PMOS transistors or PNP transistors. The first transistor Q1 and the second transistor Q2 in the embodiment of the present application are implemented by using CMOS devices, because CMOS matching is superior. First terminals of the first transistor Q1 and the second transistor Q2 are source terminals, and second terminals of the first transistor Q1 and the second transistor Q2 are drain terminals.
In some embodiments, the driving current module 120 may include: a third transistor Q3 and a fourth transistor Q4. Second terminals of the third transistor Q3 and the fourth transistor Q4 are connected to a ground terminal Vss, control terminals of the third transistor Q3 and the fourth transistor Q4 are connected to each other and receive a control voltage, a first terminal of the fourth transistor Q4 is connected to a second terminal of the second transistor Q2, and a first terminal of the third transistor Q3 is connected to a second terminal of the first transistor Q1. Alternatively, the third transistor Q3 and the fourth transistor Q4 are both NMOS transistors or NPN transistors. Similarly, the third transistor Q3 and the fourth transistor Q4 in the embodiment of the present application are implemented by CMOS devices because the matching of the complementary metal oxide semiconductors is superior. And first terminals of the third transistor Q3 and the fourth transistor Q4 are drain terminals and second terminals of the third transistor Q3 and the fourth transistor Q4 are source terminals. After the control voltage is applied to the control terminals of the third transistor Q3 and the fourth transistor Q4, the third transistor Q3 and the fourth transistor Q4 may be turned on and the first driving current I1 and the second driving current I2 may be provided, respectively.
In some embodiments, the driving current module 120 may further be implemented by any one of the current mirror circuits to provide the first driving current I1 to the second terminal of the first transistor Q1 and provide the second driving current I2 to the second terminal of the second transistor Q2, and the current mirror structure in the driving current module 120 is not specifically limited in this application. It is understood that, in the case that the driving current module 120 is implemented by using a current mirror circuit, the first driving current I1 and the second driving current I2 may be mirror currents of the reference current source. When the first transistor Q1 in the first input branch 111 is turned on, the discharge power terminal Vdis can be connected to the ground terminal through the second resistor R2, the first transistor Q1 and the third transistor Q3, thereby forming a circuit loop. The voltage value of the discharge power supply end Vdis after voltage division through the second resistor R2 and the first transistor Q1 can enable the discharge switching tube Qdis to be conducted, so that the discharge power supply end Vdis is connected with the ground end Vss through the discharge switching tube Qdis, and active discharge of the discharge power supply end Vdis is further achieved.
In some embodiments, the discharge switching tube Qdis may be an NMOS transistor or an NPN transistor. The discharge switching tube Qdis in the embodiment of the present application is implemented by a CMOS device. And the source terminal of the discharge switching tube Qdis is grounded, and the drain terminal of the discharge switching tube Qdis is connected to the discharge power source terminal Vdis. Under the condition that the discharge power source terminal Vdis is connected to the ground terminal through the second resistor R2, the first transistor Q1 and the third transistor Q3 to form a circuit loop, a difference between a voltage value of the discharge power source terminal Vdis divided by the second resistor R2 and the first transistor Q1 (a voltage value of a gate terminal of the discharge switching tube Qdis) and a voltage value of a source terminal of the discharge switching tube Qdis may be greater than a threshold voltage of the discharge switching tube, so that the discharge switching tube Qdis is turned on, and the discharge power source terminal Vdis is connected to the ground terminal through the discharge switching tube Qdis to discharge the discharge power source terminal Vdis.
Fig. 5 is a block diagram of the discharge control circuitry 10 according to an embodiment of the present application. As shown in fig. 5, the discharge control circuit system 10 includes the discharge circuit 100' and the main control switch tube Qmc as described above. Since the structure and principle of the discharge circuit 100' are described in detail above, the present application is not repeated herein. Furthermore, it should be understood that the discharge circuit 100' in the discharge control circuitry 10 may be replaced by the discharge circuit described in any of the embodiments above, and the present application is not limited thereto in particular.
In this embodiment, the driving current module 120 may have an input control terminal SW. For example, referring to fig. 4, the control terminal of the fourth transistor Q4 and/or the third transistor Q3 in the driving current module 120 may be an input control terminal SW (not shown) of the driving current module 120.
The main control switch tube Qmc is connected between the discharging power end Vdis and the discharging circuit 100', and the control end of the main control switch tube Qmc is connected with the input control end SW. The input control terminal SW can be used to trigger the driving current module 120 to provide the first driving current I1 for the first input branch 111 and provide the second driving current I2 for the second input branch 112, so as to control the discharging power terminal Vdis to realize active discharging through the discharging circuit 100'.
The above description is meant as an illustration of preferred embodiments of the application and of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (12)
1. A discharge circuit, comprising:
the common-gate input module comprises a first input branch and a second input branch, wherein the first end of the first input branch is connected to a discharge power supply end, the first end of the second input branch is connected to a power supply end, and the discharge power supply end is a control line of the memory;
a drive current module configured to provide a first drive current to the first input branch and a second drive current to the second input branch;
a first resistor connected between the power supply terminal and the discharge terminal; and
and a control end of the discharge switch tube is connected to the second end of the first input branch, a first end of the discharge switch tube is connected to the discharge power supply end, and a second end of the discharge switch tube is connected to the ground end.
2. The discharge circuit of claim 1, further comprising: and the second resistor is connected between the first end of the first input branch and the discharge power supply end.
3. The discharge circuit according to claim 2, wherein the second resistor has an adjustable resistance value and is configured to discharge the discharge power terminal to a target voltage value in accordance with the resistance value thereof.
4. The discharge circuit according to claim 1, wherein said discharge switching tube is configured to discharge said discharge power supply terminal to a voltage value of said power supply terminal.
5. The discharge circuit according to claim 3, wherein the discharge switch tube controls the discharge power terminal and the ground terminal to be connected in a case where a voltage value Vdis of the discharge power terminal, a voltage value Vdd of the power supply power terminal, a current value I1 of the first drive current, and a resistance value R2 of the second resistor satisfy Vdis > Vdd + I1 × R2.
6. The discharge circuit of claim 3, wherein the first input branch comprises a first transistor and the second input branch comprises a second transistor, wherein,
the control ends of the first transistor and the second transistor are connected, and the control end of the second transistor is connected with the second end of the second transistor;
a first end of the first transistor is connected to the second resistor, and a first end of the second transistor is connected to the power supply end;
the first drive current is applied to a second terminal of the first transistor, and the second drive current is applied to a second terminal of the second transistor.
7. The discharge circuit of claim 6, wherein the first transistor and the second transistor are both PMOS transistors or PNP type transistors.
8. The discharge circuit of claim 1 or 6, wherein the discharge switch tube is an NMOS transistor or an NPN transistor.
9. The discharge circuit of claim 6, wherein the drive current module comprises a current mirror.
10. The discharge circuit of claim 6, wherein the drive current module comprises: a third transistor and a fourth transistor, wherein,
second terminals of the third transistor and the fourth transistor are grounded, control terminals of the third transistor and the fourth transistor are connected to each other and used for receiving a control voltage, a first terminal of the fourth transistor is connected to the second terminal of the second transistor, and a first terminal of the third transistor is connected to the second terminal of the first transistor.
11. The discharge circuit of claim 10 wherein the third transistor and the fourth transistor are both NMOS transistors or NPN transistors.
12. Discharge control circuitry for a memory, comprising:
the discharge circuit of any of claims 1 to 11, wherein a drive current module of the discharge circuit has an input control terminal; and
and the master control switch tube is connected between the discharge power supply end and the discharge circuit, and the control end of the master control switch tube is connected with the input control end, wherein the power supply end is the power supply end of the memory.
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| CN202110733219.2A CN113470720B (en) | 2021-06-29 | 2021-06-29 | Discharge circuit and discharge control circuit system of memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9715245B2 (en) * | 2015-01-20 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company Limited | Circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator |
| CN107274920B (en) * | 2016-04-08 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Voltage maintaining circuit for memory, memory and electronic equipment |
| US9747957B1 (en) * | 2016-05-31 | 2017-08-29 | Micron Technology, Inc. | Power delivery circuitry |
| US10692581B2 (en) * | 2017-01-18 | 2020-06-23 | Microchip Technology Incorporated | Circuits for bleeding supply voltage from a device in a power down state |
| CN109427403B (en) * | 2017-09-01 | 2020-11-06 | 西安格易安创集成电路有限公司 | Discharge circuit and memory |
| CN108322030A (en) * | 2018-01-25 | 2018-07-24 | 郑州云海信息技术有限公司 | A kind of novel discharge circuit and method |
| CN109377964B (en) * | 2018-12-20 | 2021-03-19 | 惠科股份有限公司 | Discharge circuit, drive circuit and display device |
| CN110855277B (en) * | 2019-12-02 | 2021-07-23 | 思瑞浦微电子科技（苏州）股份有限公司 | Adjustable clamping circuit |
| CN111130340B (en) * | 2020-01-14 | 2021-08-17 | Oppo广东移动通信有限公司 | Power supply device, electronic equipment and power supply method |
| CN112599107A (en) * | 2020-12-11 | 2021-04-02 | 昆山国显光电有限公司 | Power supply discharge circuit, display module and display device |
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