CN114337563B - Current detection amplifier with configurable common mode rejection ratio and configurable gain error and method - Google Patents
Current detection amplifier with configurable common mode rejection ratio and configurable gain error and method Download PDFInfo
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- CN114337563B CN114337563B CN202111670259.3A CN202111670259A CN114337563B CN 114337563 B CN114337563 B CN 114337563B CN 202111670259 A CN202111670259 A CN 202111670259A CN 114337563 B CN114337563 B CN 114337563B
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Abstract
The invention relates to a current detection amplifier with configurable common mode rejection ratio and gain error and a method thereof. The equivalent resistance R1 'and the equivalent resistance R3' matched with the inverting terminal of the high-precision operational amplifier U1 can be obtained through the first configurable resistance unit so as to obtain a first equivalent resistance reference ratio; the equivalent resistance R2 'and the equivalent resistance R4' matched with the same-phase end of the high-precision operational amplifier U1 can be obtained through the second configurable resistance unit, so that a second equivalent resistance reference ratio can be obtained; the common mode rejection ratio and the gain error of the current detection amplifier are configured at the same time, the application range of the current detection amplifier is widened, and the current detection amplifier is safe and reliable.
Description
Technical Field
The invention relates to a current detection amplifier and a method, in particular to a current detection amplifier with configurable common mode rejection ratio and gain error and a method.
Background
The current detection amplifier is widely applied to the fields of welding equipment, computers, mobile phones, telecommunication equipment, automobiles, power management, battery chargers and the like, and can better monitor the torque of a motor, the stress of a solenoid, the LED density, the light receiving quantity of a solar battery, the electric quantity of the battery and the like by monitoring the current magnitude and the flowing direction.
The current detection amplifier can detect the very small voltage of the precise current detection resistor bridged at the differential input end of the current detection amplifier, the input end of the current detection amplifier receives the differential input voltage, the output of the differential input voltage is a single-ended signal, and the output single-ended signal is precisely in direct proportion to the differential input voltage. At present, the current detection amplifier is required to have precise gain and a high common mode rejection ratio in a use scene, which requires that the ratio of resistors in a resistor network is very precise, but the required precise level is difficult to achieve at present, so that the use and popularization of the current detection amplifier are influenced, and the requirement of practical application is difficult to meet.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a current detection amplifier with configurable common mode rejection ratio and gain error and a method thereof.
According to the technical scheme provided by the invention, the current detection amplifier with the configurable common mode rejection ratio and gain error comprises a high-precision operational amplifier U1, an inverting terminal resistance unit and a non-inverting terminal resistance unit, wherein the inverting terminal resistance unit is in adaptive connection with an inverting terminal of the high-precision operational amplifier U1, the non-inverting terminal resistance unit is in adaptive connection with a non-inverting terminal of the high-precision operational amplifier U1, the inverting terminal resistance unit comprises a resistor R1 and a resistor R3, a first end of the resistor R1 is connected with a differential input terminal INN, and a first end of the resistor R3 is connected with an output terminal of the high-precision operational amplifier U1; the in-phase end resistor unit comprises a resistor R2 and a resistor R4, the first end of the resistor R2 is connected with the differential input end INP, and the first end of the resistor R4 is connected with the reference connection end REF;
the circuit also comprises a first configurable resistance unit and a second configurable resistance unit, wherein the first configurable resistance unit is connected with the second end of the resistor R1, the inverting end of the high-precision operational amplifier U1 and the second end of the resistor R3 in a matched manner, and the second configurable resistance unit is connected with the second end of the resistor R2, the inverting end of the high-precision operational amplifier U1 and the second end of the resistor R4 in a matched manner;
the first configurable resistance unit comprises a first resistance unit reference resistance part and a first switch array matched with the first resistance unit reference resistance part, wherein the first resistance unit reference resistance part comprises a plurality of first resistance unit reference resistances, the connection states of the first resistance unit reference resistances in the first resistance unit reference resistance part, the corresponding connection states of the resistors R1, R3 and the inverting end of the high-precision operational amplifier U1 are configured through the first switch array, so that an equivalent resistor R1 'matched and connected with the differential input end INN and the inverting end of the high-precision operational amplifier U1 is obtained, meanwhile, an equivalent resistor R3' matched and connected with the output end of the high-precision operational amplifier U1 and the inverting end of the high-precision operational amplifier U1 is obtained, and R3'/R1' is set as a first equivalent resistor reference ratio;
the second configurable resistance unit comprises a second resistance unit reference resistance part and a second switch array matched with the second resistance unit reference resistance part, wherein the second resistance unit reference resistance part comprises a plurality of second resistance unit reference resistances, the connection states of the second configuration reference resistances in the second resistance unit reference resistance part, the resistors R2, R4 and the high-precision operational amplifier U1 are configured through the second switch array, so that an equivalent resistor R2 'matched and connected with the differential input end INP and the high-precision operational amplifier U1 are obtained, meanwhile, an equivalent resistor R4' matched and connected with the reference connection end REF and the high-precision operational amplifier U1 are obtained, and R4'/R2' is set as a second equivalent resistance reference ratio;
when the common mode rejection ratio and the gain error of the current detection amplifier are configured, the first switch array and the second switch array are respectively configured in corresponding working states, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are both matched with a target gain error.
When configuring the common mode rejection ratio and the gain error of the current detection amplifier, the method comprises a common mode rejection ratio initial configuration step, a gain error configuration step and a common mode rejection ratio final configuration step which are sequentially executed;
executing a common mode rejection ratio initial configuration step, and configuring corresponding working states of the first switch array and the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio;
when the step of gain error configuration is executed, the corresponding working states of the first switch array and the second switch array are configured, so that the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with a target gain error;
and when the common mode rejection ratio final configuration step is executed, only configuring the corresponding working state of the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio.
The first resistance unit reference resistance part comprises a first resistance unit reference resistance R00, the first resistance unit reference resistance R00 is connected with the second end of the resistance R1 through n first resistance unit reference resistances which are sequentially connected in series, the first resistance unit reference resistance R00 is connected with one end of a resistance Radd through n first resistance unit reference resistances which are sequentially connected in series, and the other end of the resistance Radd is connected with the second end of the resistance R3;
the first switch array comprises m rows of switch groups which are sequentially connected and matched, and n =2 m -1, the switch groups are numbered one by one in a direction pointing to the first configurable resistance unit along the inverting terminal of the high precision operational amplifier U1, wherein the switch group numbered i has 2 within it i The switch in the ith row of switch group is any two adjacent switches, and the switch states of the two switches are controlled by two non-overlapping control signals;
the n first resistance unit reference resistors are connected between the second ends of the first resistance unit reference resistor R00 and the resistor R1 in series, the n first resistance unit reference resistors are connected between the first resistance unit reference resistor R00 and the resistor Radd in series, and two ends of any first resistance unit reference resistor are distributed at one end of a switch in the m-th row of switch group for adaptive connection;
configuring first switch control information of a switch array of a switch group of m rows of the first switch array, and configuring the working state of a corresponding switch group in the first switch array according to the first switch control information of the configured switch array to obtain an equivalent resistor R1' and an equivalent resistor R3', wherein for the equivalent resistor R1', the resistor R1 is formed by matching a first resistor unit reference resistor correspondingly connected to an inverting end of a high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by the first switch array; the equivalent resistor R3' is formed by matching the resistor R3, the resistor Radd and a first resistor unit reference resistor which is correspondingly connected to the inverting terminal of the high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by a first switch array.
When the target gain error of the current sense amplifier is G, the resistance value of the resistor Radd is Radd = (G-1) × R00 = (n + 1).
The switch control information generating circuit comprises a configuration signal control logic circuit, a shift register, a control word programming circuit and an adder which are sequentially connected, wherein the adder loads first switch control information of the switch array into the first switch array, and loads second switch control information of the switch array required in the second switch array.
The adder comprises a switch array first switch control information generation part and a switch array second switch control information part, wherein the switch array first switch control information generation part comprises a first addition unit, and the switch array second switch control information part comprises a second addition unit and a third addition unit matched with the second addition unit.
A method for configuring a common mode rejection ratio and a gain error is provided, and a current detection amplifier to be configured is provided, wherein the current detection amplifier comprises a high-precision operational amplifier U1, an inverting terminal resistance unit which is in adaptive connection with an inverting terminal of the high-precision operational amplifier U1, and a non-inverting terminal resistance unit which is in adaptive connection with a non-inverting terminal of the high-precision operational amplifier U1, the inverting terminal resistance unit comprises a resistor R1 and a resistor R3, a first terminal of the resistor R1 is connected with a differential input terminal INN, and a first terminal of the resistor R3 is connected with an output terminal of the high-precision operational amplifier U1; the in-phase terminal resistor unit comprises a resistor R2 and a resistor R4, wherein the first end of the resistor R2 is connected with the differential input terminal INP, and the first end of the resistor R4 is connected with the reference connection terminal REF; the method is characterized in that:
the circuit also comprises a first configurable resistance unit and a second configurable resistance unit, wherein the first configurable resistance unit is connected with the second end of the resistor R1, the inverting end of the high-precision operational amplifier U1 and the second end of the resistor R3 in a matched manner, and the second configurable resistance unit is connected with the second end of the resistor R2, the inverting end of the high-precision operational amplifier U1 and the second end of the resistor R4 in a matched manner;
the first configurable resistance unit comprises a first resistance unit reference resistance part and a first switch array matched with the first resistance unit reference resistance part, wherein the first resistance unit reference resistance part comprises a plurality of first resistance unit reference resistances, the connection state of the first resistance unit reference resistance in the first resistance unit reference resistance part, corresponding to the resistors R1, R3 and the inverting end of the high-precision operational amplifier U1, is configured through the first switch array, so that the equivalent resistance R1 'matched and connected with the differential input end INN and the inverting end of the high-precision operational amplifier U1 is obtained, meanwhile, the equivalent resistance R3' matched and connected with the output end of the high-precision operational amplifier U1 and the inverting end of the high-precision operational amplifier U1 is obtained, and R3'/R1' is set as a first equivalent resistance reference ratio;
the second configurable resistance unit comprises a second resistance unit reference resistance part and a second switch array matched with the second resistance unit reference resistance part, wherein the second resistance unit reference resistance part comprises a plurality of second resistance unit reference resistances, the connection states of the second configuration reference resistances in the second resistance unit reference resistance part, the resistors R2, R4 and the high-precision operational amplifier U1 are configured through the second switch array, so that an equivalent resistor R2 'matched and connected with the differential input end INP and the high-precision operational amplifier U1 are obtained, meanwhile, an equivalent resistor R4' matched and connected with the reference connection end REF and the high-precision operational amplifier U1 are obtained, and R4'/R2' is set as a second equivalent resistance reference ratio;
when the common mode rejection ratio and the gain error of the current detection amplifier are configured, the first switch array and the second switch array are respectively configured in corresponding working states, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are both matched with a target gain error.
When configuring the common mode rejection ratio and the gain error of the current detection amplifier, the method comprises a common mode rejection ratio initial configuration step, a gain error configuration step and a common mode rejection ratio final configuration step which are executed in sequence;
executing a common mode rejection ratio initial configuration step, and configuring corresponding working states of the first switch array and the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio;
when the step of gain error configuration is executed, the corresponding working states of the first switch array and the second switch array are configured, so that the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with a target gain error;
and when the common mode rejection ratio final configuration step is executed, only configuring the corresponding working state of the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio.
The first resistance unit reference resistance part comprises a first resistance unit reference resistance R00, the first resistance unit reference resistance R00 is connected with the second end of the resistance R1 through n first resistance unit reference resistances which are sequentially connected in series, the first resistance unit reference resistance R00 is connected with one end of a resistance Radd through n first resistance unit reference resistances which are sequentially connected in series, and the other end of the resistance Radd is connected with the second end of the resistance R3;
the first switch array comprises m rows of switch groups which are sequentially connected and matched, and n =2 m -1, inverting along the high precision operational amplifier U1The serial numbers of the switch groups are increased one by one in the direction that the end points to the first configurable resistance unit, wherein the switch group with the serial number of i rows has 2 i The switch in the ith row of switch group is any two adjacent switches, and the switch states of the two switches are controlled by two non-overlapping control signals;
the n first resistance unit reference resistors are connected between the second ends of the first resistance unit reference resistor R00 and the resistor R1 in series, the n first resistance unit reference resistors are connected between the first resistance unit reference resistor R00 and the resistor Radd in series, and two ends of any first resistance unit reference resistor are distributed at one end of a switch in the m-th row of switch group for adaptive connection;
configuring first switch control information of a switch array of a switch group of m rows of the first switch array, and configuring the working state of a corresponding switch group in the first switch array according to the first switch control information of the configured switch array to obtain an equivalent resistor R1' and an equivalent resistor R3', wherein for the equivalent resistor R1', the resistor R1 and a first resistor unit reference resistor correspondingly connected to the inverting end of a high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by the first switch array are matched to form the equivalent resistor R1; the equivalent resistor R3' is formed by matching the resistor R3, the resistor Radd and a first resistor unit reference resistor which is correspondingly connected to the inverting terminal of the high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by a first switch array.
The switch control information generating circuit comprises a configuration signal control logic circuit, a shift register, a control word programming circuit and an adder which are sequentially connected, wherein the adder loads first switch control information of the switch array into the first switch array, and loads second switch control information of the switch array required in the second switch array.
The invention has the advantages that: the equivalent resistance R1 'and the equivalent resistance R3' matched with the inverting terminal of the high-precision operational amplifier U1 can be obtained through the first configurable resistance unit so as to obtain a first equivalent resistance reference ratio; the equivalent resistance R2 'and the equivalent resistance R4' matched with the in-phase end of the high-precision operational amplifier U1 can be obtained through the second configurable resistance unit, so that a second equivalent resistance reference ratio can be obtained; the common mode rejection ratio and the gain error of the current detection amplifier are configured at the same time, the application range of the current detection amplifier is widened, and the current detection amplifier is safe and reliable.
Drawings
FIG. 1 is a schematic diagram of a circuit sense amplifier of the present invention.
Fig. 2 is a schematic diagram of the first configurable resistance unit of the present invention in cooperation with a high precision operational amplifier U1.
FIG. 3 is a flow chart of the present invention during configuration.
FIG. 4 is a schematic diagram of an adder according to the present invention.
Description of reference numerals: the circuit comprises a 1-configuration signal control logic circuit, a 2-shift register, a 3-control word programming circuit, a 4-adder, a 5-first configurable resistance unit, a 6-second configurable resistance unit, a 7-first addition unit, an 8-second addition unit and a 9-third addition unit.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1: in order to simultaneously configure the common mode rejection ratio and the gain error of the current detection amplifier and improve the application range of the current detection amplifier, the current detection amplifier comprises a high-precision operational amplifier U1, an inverting terminal resistance unit which is in adaptive connection with an inverting terminal of the high-precision operational amplifier U1 and a non-inverting terminal resistance unit which is in adaptive connection with a non-inverting terminal of the high-precision operational amplifier U1, wherein the inverting terminal resistance unit comprises a resistor R1 and a resistor R3, the first terminal of the resistor R1 is connected with a differential input terminal INN, and the first terminal of the resistor R3 is connected with the output terminal of the high-precision operational amplifier U1; the in-phase terminal resistor unit comprises a resistor R2 and a resistor R4, wherein the first end of the resistor R2 is connected with the differential input terminal INP, and the first end of the resistor R4 is connected with the reference connection terminal REF;
the circuit further comprises a first configurable resistance unit 5 and a second configurable resistance unit 6, wherein the first configurable resistance unit 5 is in adaptive connection with a second end of the resistor R1, an inverting end of the high-precision operational amplifier U1 and a second end of the resistor R3, and the second configurable resistance unit 6 is in adaptive connection with a second end of the resistor R2, an inverting end of the high-precision operational amplifier U1 and a second end of the resistor R4;
the first configurable resistance unit 5 comprises a first resistance unit reference resistance part and a first switch array adaptive to the first resistance unit reference resistance part, wherein the first resistance unit reference resistance part comprises a plurality of first resistance unit reference resistances, and the connection states of the first resistance unit reference resistances in the first resistance unit reference resistance part, the resistances R1 and the resistors R3 and the inverting ends of the high-precision operational amplifier U1 are configured through the first switch array so as to obtain an equivalent resistance R1 'adaptively connected with the differential input end INN and the inverting end of the high-precision operational amplifier U1, and simultaneously obtain an equivalent resistance R3' adaptively connected with the output end of the high-precision operational amplifier U1 and the inverting end of the high-precision operational amplifier U1, and set R3'/R1' as a first equivalent resistance reference ratio;
the second configurable resistance unit 6 comprises a second resistance unit reference resistance part and a second switch array adapted to the second resistance unit reference resistance part, wherein the second resistance unit reference resistance part comprises a plurality of second resistance unit reference resistances, and the second switch array is used for configuring the connection state of the second configuration reference resistance in the second resistance unit reference resistance part, corresponding to the in-phase ends of the resistance R2, the resistance R4 and the high-precision operational amplifier U1, so as to obtain an equivalent resistance R2 'adapted to the in-phase ends of the differential input end INP and the high-precision operational amplifier U1, and simultaneously obtain an equivalent resistance R4' adapted to the in-phase ends of the reference connection end REF and the high-precision operational amplifier U1, and set R4'/R2' as a second equivalent resistance reference ratio;
when the common mode rejection ratio and the gain error of the current detection amplifier are configured, the first switch array and the second switch array are respectively configured in corresponding working states, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are both matched with a target gain error.
Specifically, the current detection amplifier comprises a high-precision operational amplifier U1, the high-precision operational amplifier U1 may specifically adopt an existing common form, generally, an inverting terminal of the high-precision operational amplifier U1 is in adaptive connection with an inverting terminal resistance unit, and a non-inverting terminal of the high-precision operational amplifier U1 is in adaptive connection with a non-inverting terminal resistance unit, wherein the inverting terminal resistance unit comprises a resistance R1 and a resistance R3, the non-inverting terminal resistance unit comprises a resistance R2 and a resistance R4, a first terminal of the resistance R1 is connected to a differential input terminal INN, and a first terminal of the resistance R3 is connected to an output terminal of the high-precision operational amplifier U1; the in-phase terminal resistor unit comprises a resistor R2 and a resistor R4, wherein the first terminal of the resistor R2 is connected with the differential input terminal INP, the first terminal of the resistor R4 is connected with the reference connection terminal REF, a reference voltage required by the working of the current detection amplifier can be provided through the reference connection terminal REF, and the function and the mode of the provided reference voltage are consistent with those of the prior art.
It can be known from the background art that when R3/R1 and R4/R2 are equal or close to equal, the whole current sense amplifier has a high common mode rejection ratio, and when R3/R1 and R4/R2 are equal or close to the target gain error, the whole current sense amplifier has a gain error adapted to the target gain error. However, in actual production, the corresponding resistance values of the resistors R1 to R4 may have a large deviation due to conditions such as a process, so that the common mode rejection ratio and the gain error of the whole current detection amplifier have a large difference from an expected state, and the application range of the current detection amplifier is limited.
In the embodiment of the present invention, the first configurable resistor unit 5 is connected to the second end of the resistor R1, the inverting end of the high-precision operational amplifier U1, and the second end of the resistor R3 in an adaptive manner, and the second configurable resistor unit 6 is connected to the second end of the resistor R2, the inverting end of the high-precision operational amplifier U1, and the second end of the resistor R4 in an adaptive manner, that is, the first configurable resistor unit 5 is matched to the resistor R1, the resistor R3, and the inverting end of the high-precision operational amplifier U1, and the second configurable resistor unit 6 is matched to the resistor R2, the resistor R4, and the inverting end of the high-precision operational amplifier U1, so as to configure the common mode rejection ratio and the gain error of the whole current detection amplifier.
Specifically, for the first configurable resistance unit 5, the first configurable resistance unit includes a first resistance unit reference resistance part and a first switch array adapted to the first resistance unit reference resistance part, where the first resistance unit reference resistance part includes a plurality of first resistance unit reference resistances, and the first switch array is used to configure a connection state of the first resistance unit reference resistance in the first resistance unit reference resistance part, the resistance R1, the resistance R3, and the inverting terminal of the high-precision operational amplifier U1, so as to obtain an equivalent resistance R1 'adapted to the differential input terminal INN and the inverting terminal of the high-precision operational amplifier U1, and at the same time, obtain an equivalent resistance R3' adapted to the output terminal of the high-precision operational amplifier U1 and the inverting terminal of the high-precision operational amplifier U1, and set R3'/R1' as a first equivalent resistance reference ratio, that is, a ratio of R3/R1 is represented by the first equivalent resistance reference ratio.
Similarly, for the second configurable resistance unit 6, through the second switch array and the second resistance unit reference resistance portion in the second configurable resistance unit 6, the equivalent resistance R2 'adaptively connected to the differential input terminal INP and the non-inverting terminal of the high-precision operational amplifier U1 can be obtained, and at the same time, the equivalent resistance R4' adaptively connected to the reference connection terminal REF and the non-inverting terminal of the high-precision operational amplifier U1 can be obtained, and R4'/R2' is set as a second equivalent resistance reference ratio, that is, the value of R4/R2 is represented by the second equivalent resistance reference ratio.
In specific implementation, the corresponding working state of the first switch array may be configured as required to obtain the required first equivalent resistance reference ratio, and the corresponding working state of the second switch array may be configured to obtain the required second equivalent resistance reference ratio. When the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio through configuration, the whole current detection amplifier has a high common mode rejection ratio; and when the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with the target gain error, the gain error of the whole current detection amplifier can be configured and then matched with the target gain error.
Specifically, the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, specifically, the difference between the first equivalent resistance reference ratio and the second equivalent resistance reference ratio is equal to or within an allowable range, and the allowable range may be determined according to actual situations such as an application scenario of the current detection amplifier, which is well known to those skilled in the art. Similarly, the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are both matched with the target gain error, specifically, when it is determined that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, the first equivalent resistance reference ratio, the second equivalent resistance reference ratio and the target gain error are equal or the corresponding difference is within an allowable range, and the allowable range may be determined specifically as needed, which is well known to those skilled in the art and will not be described herein again.
As shown in fig. 3, when configuring the common mode rejection ratio and the gain error of the current detection amplifier, the method includes a common mode rejection ratio initial configuration step, a gain error configuration step, and a common mode rejection ratio final configuration step that are sequentially executed;
executing a common mode rejection ratio initial configuration step, and configuring corresponding working states of the first switch array and the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio;
when the step of gain error configuration is executed, the corresponding working states of the first switch array and the second switch array are configured, so that the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with the target gain error;
and when the common mode rejection ratio final configuration step is executed, only configuring the corresponding working state of the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio.
Specifically, since the common-mode rejection ratio and the gain error of the current detection amplifier can be configured separately, according to the characteristics of the common-mode rejection ratio and the gain error, it is necessary to sequentially perform the initial configuration step of the common-mode rejection ratio, the configuration step of the gain error, and the final configuration step of the common-mode rejection ratio during the specific configuration.
In specific implementation, a step of initially configuring the common mode rejection ratio is performed, and the corresponding working states of the first switch array and the second switch array are configured, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio.
After the common mode rejection ratio of the current detection amplifier is preliminarily configured, a specific ratio of a first equivalent resistance reference ratio and a second equivalent resistance reference ratio needs to be configured through the first switch array and the second switch array until the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with a target gain error, and then the gain error configuration of the current detection amplifier is realized.
As will be appreciated by those skilled in the art, the accuracy of the common mode rejection ratio configuration adjustment is greater than that of the gain error configuration adjustment, and the influence of the resistance value variation on the gain error is relatively small, so that the common mode rejection ratio final configuration step needs to be performed after the gain error configuration.
In specific implementation, when the common mode rejection ratio final configuration step is executed, the working state of the first switch array during gain error configuration is maintained, and only the corresponding working state of the second switch array is configured, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and the current detection amplifier can be further ensured to have a high common mode rejection ratio.
As shown in fig. 2, which is a schematic diagram of a specific implementation of the connection coordination between the first configurable resistance unit 5 and the inverting terminal of the high-precision operational amplifier U1, the resistor R1, and the resistor R3 according to the present invention, specifically, the first resistance unit reference resistance portion includes a first resistance unit reference resistor R00, the first resistance unit reference resistor R00 is connected to the second terminal of the resistor R1 through n first resistance unit reference resistors sequentially connected in series, the first resistance unit reference resistor R00 is connected to one end of the resistor Radd through n first resistance unit reference resistors sequentially connected in series, and the other end of the resistor Radd is connected to the second terminal of the resistor R3;
the first switch array comprises m rows of switch groups which are sequentially connected and matched, and n =2 m -1, the switch groups are numbered one by one in the direction pointing to the first configurable resistance unit 5 along the inverting terminal of the high precision operational amplifier U1, wherein the switch group numbered i has 2 in it i The switch in the ith row of switch group is any two adjacent switches, and the switch states of the two switches are controlled by two non-overlapping control signals;
the n first resistance unit reference resistors are connected between the second ends of the first resistance unit reference resistor R00 and the resistor R1 in series, the n first resistance unit reference resistors are connected between the first resistance unit reference resistor R00 and the resistor Radd in series, and two ends of any first resistance unit reference resistor are distributed at one end of a switch in the m-th row of switch group for adaptive connection;
configuring first switch control information of a switch array of a switch group of m rows of the first switch array, and configuring the working state of a corresponding switch group in the first switch array according to the first switch control information of the configured switch array to obtain an equivalent resistor R1' and an equivalent resistor R3', wherein for the equivalent resistor R1', the resistor R1 is formed by matching a first resistor unit reference resistor correspondingly connected to an inverting end of a high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by the first switch array; and for the equivalent resistor R3', the resistor Radd and a first resistor unit reference resistor which is correspondingly connected to the inverting terminal of the high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by a first switch array are matched to form the equivalent resistor R3'.
Specifically, the first resistor unit reference resistor portion includes a first resistor unit reference resistor R00 therein, the first resistor unit reference resistor R00 is connected to the second end of the resistor R1 through n first resistor unit reference resistors connected in series in sequence, the resistance values of the n first resistor unit reference resistors connected in series in sequence may be the same as the first resistor unit reference resistor R00, the specific size of the first resistor unit reference resistor R00 may generally be determined by process accuracy and the like, generally, the resistance value of the resistor R3 is greater than the resistance value of the resistor R1, and the resistance value of the resistor R1 is greater than the resistance value of the first resistor unit reference resistor R00. In fig. 2, n first resistor unit reference resistors connected in series in sequence, specifically, a first resistor unit reference resistor R11 and a first resistor unit reference resistor R12, \8230areconnected to the second ends of the first resistor unit reference resistor R00 and the resistor R1, respectively, where the first resistor unit reference resistor R1n, i.e., n first resistor unit reference resistor numbers connected in series, are sequentially increased, one end of the first resistor unit reference resistor R1n is connected to the second end of the resistor R1, the other end of the first resistor unit reference resistor R1n is connected to the resistor R1n-1, one end of the first resistor unit reference resistor R11 is connected to one end of the first resistor unit reference resistor R00, and the other end of the first resistor unit reference resistor R11 is connected to the first resistor unit reference resistor R12.
Similarly, between the first resistance unit reference resistor R00 and the resistor R3, specifically, the other end of the first resistance unit reference resistor R00 is connected to one end of the resistor Radd through n first resistance unit reference resistors sequentially connected in series, and the other end of the resistor Radd is connected to the second end of the resistor R3, wherein the n first resistance unit reference resistors sequentially connected in series are respectively the first resistance unit reference resistor R01, the first resistance unit reference resistor R02, \ 8230:, the first resistance unit reference resistor R0n-1, the first resistance unit reference resistor R01, the first resistance unit reference resistor R02, \ 8230:, the corresponding resistance value of the first resistance unit reference resistor R0n-1 is consistent with the resistance value of the first resistance unit reference resistor R00, one end of the first resistance unit reference resistor R01 is connected to the other end of the first resistance unit reference resistor R00, the other end of the first resistance unit reference resistor R01 is connected to one end of the first resistance unit reference resistor R02, and the other ends of the first resistance unit reference resistors R1 are connected to the other ends of the first resistance unit reference resistors Radd, and the other ends of the first resistance unit reference resistors R3 are connected to the other ends of the Radd.
In specific implementation, when the target gain error of the current detection amplifier is G, the resistance value of the resistor Radd is Radd = (G-1) × R00 = (n + 1), that is, after the target gain error G and n are determined, the resistance value of the resistor Radd can be obtained. The resistor Radd is formed by connecting a plurality of first resistor unit reference resistors R00 in series, and can be specifically selected according to needs; the requirement for gain error configuration can be met through the resistor Radd.
In the embodiment of the invention, the first switch array comprises m rows of switch groups which are sequentially connected and matched, and n =2 m -1, the switch groups are numbered one by one in the direction of pointing to the first configurable resistance unit 5 along the inverting terminal of the high precision operational amplifier U1, where the switch group numbered i has 2 in it i A switch. Specifically, the switches in the switch group may adopt an existing commonly-used controllable switch form, such as a MOSFET device, and may be specifically selected as needed, i is 1 to m, when i is 1, that is, two switches are provided in the switch group in the first row, as shown in fig. 2, as the number of the switches in the switch group increases, the number of the switches in the adjacent switch group is equal, and when i is 2, four switches are provided in the switch group in the second row.
In fig. 2, specifically, n first resistor unit reference resistors serially connected between the first resistor unit reference resistor R00 and the second end of the resistor R1, and n first resistor unit reference resistors serially connected between the first resistor unit reference resistor R00 and the resistor Radd, where two ends of any first resistor unit reference resistor are distributed at one end of a switch in the mth row switch group for adaptive connection.
And the switch in the ith row of switch group comprises any two adjacent switches, the switch states of the two switches are controlled by two non-overlapping control signals, for example, the switch state of one switch is controlled by a first control signal, the switch state of the other switch is controlled by a second control signal, and the first control signal and the second control signal are two non-overlapping control signals. In fig. 2, in the direction from the resistor R1 to the resistor R3, the first control signal and the second control signal alternately control the corresponding switches in the same switch group, and the specific situation and the actual configuration of the control signal in each switch group are selected. In FIG. 2, for the switch set in row m, bit1 may be the first control signal! bit1 is a second control signal; for line 1, then bit m may be the first control signal! And bit m is a second control signal, and the specific conditions in the rest row switch groups can be selected according to actual needs, which are not described in detail.
In specific implementation, when determining the specific form of the first switch array and the matching between the first switch array and the corresponding first resistance unit reference resistance, setting first switch control information of the switch array configuring the m rows of switch groups of the first switch array, so as to obtain an equivalent resistance R1' and an equivalent resistance R3' according to the configured switch control information, wherein for the equivalent resistance R1', the resistance R1 is formed by matching the first switch array with the first resistance unit reference resistance correspondingly connected to the inverting terminal of the high-precision operational amplifier U1 in the first resistance unit reference resistance part configured by the first switch array; and for the equivalent resistor R3', the resistor Radd and a first resistor unit reference resistor which is correspondingly connected to the inverting terminal of the high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by a first switch array are matched to form the equivalent resistor R3'.
In addition, for the second configurable resistance unit 6, the specific configuration description of the first configurable resistance unit 5 may be specifically referred to, that is, for the second configurable resistance unit 6, the second configurable resistance unit 6 is configured to cooperate with the resistor R2, the non-inverting terminal of the high-precision operational amplifier U1, and the resistor R4, to specifically obtain the equivalent resistor R2 'and the equivalent resistor R4', and finally obtain the second equivalent resistance reference ratio, which is not described herein again for specific situations.
During specific implementation, the working state of the first switch array is configured to obtain a first equivalent resistance reference ratio, the working state of the second switch array is configured, after a second equivalent resistance reference ratio is obtained, a corresponding differential signal can be loaded on the current detection amplifier, whether the current first equivalent resistance reference ratio and the current second equivalent resistance reference ratio can meet specific configuration requirements of a specific common mode rejection ratio and a gain error or not is judged according to an output signal, and if the current first equivalent resistance reference ratio and the current second equivalent resistance reference ratio cannot meet the specific configuration requirements of the specific common mode rejection ratio and the gain error, the corresponding working states of the first switch array and the second switch array are continuously adjusted until the specific configuration requirements of the common mode rejection ratio and the gain error are met.
Of course, in practical implementation, the first configurable resistance unit 5 and the second configurable resistance unit 6 may also take other required forms, and may be specifically selected according to needs so as to satisfy the requirement of obtaining the first equivalent resistance reference ratio and the second equivalent resistance reference ratio, which is not described herein.
Further, the switch control information generating circuit is further included for generating switch control information of m rows of switch groups, and the switch control information generating circuit includes a configuration signal control logic circuit 1, a shift register 2, a control word programming circuit 3 and an adder 4 which are connected in sequence, wherein a first switch control information of a switch array is loaded into the first switch array through the adder 4, and a second switch control information of a switch array required is loaded into the second switch array through the adder 4.
Specifically, the configuration signal control logic circuit 1, the shift register 2, the control word programming circuit 3, and the adder 4 may all adopt the existing commonly used form, generally, the configuration signal control logic circuit 1, the shift register 2, the control word programming circuit 3, the adder 4, the first configurable resistance unit 5, the second configurable resistance unit 6, the resistor R1, the resistor R2, the resistor R3, and the resistor R4 are integrated by an integrated circuit process, a programming control PIN terminal is arranged on the integrated circuit, and the programming control PIN terminal is connected with the configuration signal control logic circuit 1.
During specific implementation, the programming control PIN code can be received by the configuration signal control logic circuit 1, shift register is carried out by the shift register 2, the configuration control signal is generated by the control word programming circuit 3, the configuration control signal is subjected to logical operation by the adder 4, and finally, the first switch control information of the switch array and the second switch control information of the switch array are obtained, the switch state of the switch in the first switch array is controlled by the first switch control information of the switch array, the switch state of the switch in the second switch array is controlled by the second switch control information of the switch array, and the common mode rejection ratio and the gain error configuration of the current detection amplifier are finally realized.
Fig. 4 is a schematic diagram of an implementation of the adder 4, where the adder 4 includes a switch array first switch control information generating unit and a switch array second switch control information generating unit, where the switch array first switch control information generating unit includes a first adding unit 7, and the switch array second switch control information generating unit includes a second adding unit 8 and a third adding unit 9 adapted to the second adding unit 8.
Specifically, as can be seen from the above description, when configuring the common mode rejection ratio and the gain error, a common mode rejection ratio initial configuration step, a gain error configuration step, and a common mode rejection ratio final configuration step need to be sequentially executed, where each step generates an individual control word signal, and the adder 4 adds the control word signals of the three stages to obtain an actual control signal, that is, the first switch control information of the switch array and the second switch control information of the switch array can be obtained. The adder 4 is in particular an m-bit adder with a sign bit.
When the common mode rejection ratio initial configuration step is executed, the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and therefore the configuration of the common mode rejection ratio is achieved; when the gain error configuration step is executed, on the basis of executing the preliminary configuration of the common mode rejection ratio, the first configurable resistance unit 5 and the second configurable resistance unit 6 are respectively connected to the inverting terminal and the non-inverting terminal of the high-precision operational amplifier U1, and simultaneously move leftwards or rightwards, so that the first equivalent resistance reference ratio is approximately equal to the second equivalent resistance reference ratio and approximately equal to the target gain error, and the configuration of the gain error is realized. When the common mode rejection ratio final configuration step is executed, the state of the first configurable resistance unit 5 after the gain error configuration step is executed is kept, and the corresponding connection matching state between the second configurable resistance unit 6 and the in-phase end, the differential input end INP and the reference connection end REF of the high-precision operational amplifier U1 is finely adjusted, so that the matching precision between the first equivalent resistance reference ratio and the second equivalent resistance reference ratio can be improved.
In fig. 4, D <1> is a control word signal at the time of the initial configuration step of the common mode rejection ratio, where D <1> m > is applied to the input terminal of the first adding unit 7, and D < m +1> is applied to the input terminal of the second adding unit 8. D <2m + 1).
D <3m + 1; q1< 1. Q2< 1. Q2"< 1.
Because the configuration of the common mode rejection ratio needs to be relatively more accurate, the configuration precision requirement of the gain error is smaller, and in specific implementation, when the gain error configuration step is executed, the configuration can be performed without using m-bit control words, and only the null position needs to be filled with zero when the addition operation is performed, namely D <2m + 1; similarly, when the final common mode rejection ratio configuration step is executed, the adjustment of the second configurable resistance unit 6 is also in a small range, and it is also unnecessary to use m-bit control words for configuration, at this time, D <3m +1 4m > may be selected according to actual needs, and in the specific implementation, it is known to those skilled in the art to meet the requirements of specific design circuits, and details are not described here.
D <1 >. Before the chip select signal corresponding to each bit of control word does not come, the control word is default to 0, d < -z < +1> is a trimming locking control signal, that is, the common-mode rejection ratio and the gain error configured for the current detection amplifier can be locked through the trimming locking control signal, and the specific trimming locking manner and process are consistent with those in the prior art and are well known to those skilled in the art, and are not described herein again.
In summary, a method for configuring a common mode rejection ratio and a gain error is provided, in which a current detection amplifier to be configured is provided, the current detection amplifier includes a high-precision operational amplifier U1, an inverting terminal resistance unit adaptively connected to an inverting terminal of the high-precision operational amplifier U1, and an inverting terminal resistance unit adaptively connected to an inverting terminal of the high-precision operational amplifier U1, the inverting terminal resistance unit includes a resistor R1 and a resistor R3, a first terminal of the resistor R1 is connected to a differential input terminal INN, and a first terminal of the resistor R3 is connected to an output terminal of the high-precision operational amplifier U1; the in-phase end resistor unit comprises a resistor R2 and a resistor R4, the first end of the resistor R2 is connected with the differential input end INP, and the first end of the resistor R4 is connected with the reference connection end REF;
the circuit further comprises a first configurable resistance unit 5 and a second configurable resistance unit 6, wherein the first configurable resistance unit 5 is in adaptive connection with a second end of the resistor R1, an inverting end of the high-precision operational amplifier U1 and a second end of the resistor R3, and the second configurable resistance unit 6 is in adaptive connection with a second end of the resistor R2, an inverting end of the high-precision operational amplifier U1 and a second end of the resistor R4;
the first configurable resistance unit 5 comprises a first resistance unit reference resistance part and a first switch array adaptive to the first resistance unit reference resistance part, wherein the first resistance unit reference resistance part comprises a plurality of first resistance unit reference resistances, and the connection states of the first resistance unit reference resistances in the first resistance unit reference resistance part, the resistances R1 and the resistors R3 and the inverting ends of the high-precision operational amplifier U1 are configured through the first switch array so as to obtain an equivalent resistance R1 'adaptively connected with the differential input end INN and the inverting end of the high-precision operational amplifier U1, and simultaneously obtain an equivalent resistance R3' adaptively connected with the output end of the high-precision operational amplifier U1 and the inverting end of the high-precision operational amplifier U1, and set R3'/R1' as a first equivalent resistance reference ratio;
the second configurable resistance unit 6 comprises a second resistance unit reference resistance part and a second switch array matched with the second resistance unit reference resistance part, wherein the second resistance unit reference resistance part comprises a plurality of second resistance unit reference resistances, and the second switch array is used for configuring the connection states of the second configuration reference resistances in the second resistance unit reference resistance part, the resistances R2, R4 and the high-precision operational amplifier U1 in the same-phase ends, so as to obtain an equivalent resistance R2 'matched and connected with the differential input end INP and the high-precision operational amplifier U1 in the same-phase ends, and simultaneously obtain an equivalent resistance R4' matched and connected with the reference connection end REF and the high-precision operational amplifier U1 in the same-phase ends, and set the R4'/R2' as a second equivalent resistance reference ratio;
when the common mode rejection ratio and the gain error of the current detection amplifier are configured, the first switch array and the second switch array are respectively configured in corresponding working states, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are both matched with a target gain error.
Specifically, the specific configuration manner and process of the common mode rejection ratio and the gain error, which are realized by the specific coordination of the first configurable resistance unit 5 and the inverting terminal of the high-precision operational amplifier U1, the specific coordination of the resistance R1 and the resistance R3, and the specific coordination of the second configurable resistance unit 6 and the inverting terminal of the high-precision operational amplifier U1, the specific coordination of the resistance R2 and the resistance R4, may refer to the above description, and are not repeated herein.
Claims (7)
1. A current detection amplifier with configurable common-mode rejection ratio and gain error comprises a high-precision operational amplifier U1, an inverting terminal resistance unit and a non-inverting terminal resistance unit, wherein the inverting terminal resistance unit is connected with an inverting terminal of the high-precision operational amplifier U1 in an adaptive mode, the non-inverting terminal resistance unit is connected with a non-inverting terminal of the high-precision operational amplifier U1 in an adaptive mode, the inverting terminal resistance unit comprises a resistor R1 and a resistor R3, the first terminal of the resistor R1 is connected with a differential input terminal INN, and the first terminal of the resistor R3 is connected with the output terminal of the high-precision operational amplifier U1; the in-phase end resistor unit comprises a resistor R2 and a resistor R4, the first end of the resistor R2 is connected with the differential input end INP, and the first end of the resistor R4 is connected with the reference connection end REF; the method is characterized in that:
the circuit also comprises a first configurable resistance unit (5) and a second configurable resistance unit (6), wherein the first configurable resistance unit (5) is in adaptive connection with a second end of the resistor R1, an inverting end of the high-precision operational amplifier U1 and a second end of the resistor R3, and the second configurable resistance unit (6) is in adaptive connection with a second end of the resistor R2, a non-inverting end of the high-precision operational amplifier U1 and a second end of the resistor R4;
the first configurable resistance unit (5) comprises a first resistance unit reference resistance part and a first switch array matched with the first resistance unit reference resistance part, wherein the first resistance unit reference resistance part comprises a plurality of first resistance unit reference resistances, the connection state of the first resistance unit reference resistance in the first resistance unit reference resistance part, the corresponding connection state of the resistance R1, the resistance R3 and the inverted phase end of the high-precision operational amplifier U1 are configured through the first switch array, so that an equivalent resistance R1 'matched and connected with the differential input end INN and the inverted phase end of the high-precision operational amplifier U1 is obtained, meanwhile, an equivalent resistance R3' matched and connected with the output end of the high-precision operational amplifier U1 and the inverted phase end of the high-precision operational amplifier U1 is obtained, and R3'/R1' is set as a first equivalent resistance reference ratio;
the second configurable resistance unit (6) comprises a second resistance unit reference resistance part and a second switch array matched with the second resistance unit reference resistance part, wherein the second resistance unit reference resistance part comprises a plurality of second resistance unit reference resistances, and the second switch array is used for configuring the connection state of the second configuration reference resistance in the second resistance unit reference resistance part, the resistance R2, the resistance R4 and the high-precision operational amplifier U1 in the same-phase end manner so as to obtain an equivalent resistance R2 'matched and connected with the differential input end INP and the high-precision operational amplifier U1 in the same-phase end manner, and simultaneously obtain an equivalent resistance R4' matched and connected with the reference connection end REF and the high-precision operational amplifier U1 in the same-phase end manner, and set the resistance R4'/R2' as a second equivalent resistance reference ratio;
when the common mode rejection ratio and the gain error of the current detection amplifier are configured, the first switch array and the second switch array are respectively configured in corresponding working states, so that the first equivalent resistance reference ratio is matched with the second equivalent resistance reference ratio, and the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are both matched with the target gain error;
the first resistance unit reference resistance part comprises a first resistance unit reference resistance R00, the first resistance unit reference resistance R00 is connected with the second end of the resistance R1 through n first resistance unit reference resistances which are sequentially connected in series, the first resistance unit reference resistance R00 is connected with one end of a resistance Radd through n first resistance unit reference resistances which are sequentially connected in series, and the other end of the resistance Radd is connected with the second end of the resistance R3;
the first switch array comprises m rows of switch groups which are sequentially connected and matched, and n =2 m -1, the switch groups are numbered one by one in a direction from the inverting terminal of the high precision operational amplifier U1 towards the first configurable resistance unit (5), wherein the switch group numbered i has 2 within it i The switch in the ith row of switch group is any two adjacent switches, and the switch states of the two switches are controlled by two non-overlapping control signals;
the n first resistance unit reference resistors are connected between the second ends of the first resistance unit reference resistor R00 and the resistor R1 in series, the n first resistance unit reference resistors are connected between the first resistance unit reference resistor R00 and the resistor Radd in series, and two ends of any first resistance unit reference resistor are distributed at one end of a switch in the m-th row of switch group for adaptive connection;
configuring first switch control information of a switch array of a switch group of m rows of the first switch array, and configuring the working state of a corresponding switch group in the first switch array according to the first switch control information of the configured switch array to obtain an equivalent resistor R1' and an equivalent resistor R3', wherein for the equivalent resistor R1', the resistor R1 is formed by matching a first resistor unit reference resistor correspondingly connected to an inverting end of a high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by the first switch array; the equivalent resistor R3' is formed by matching the resistor R3, the resistor Radd and a first resistor unit reference resistor which is correspondingly connected to the inverting terminal of the high-precision operational amplifier U1 in a first resistor unit reference resistor part configured by a first switch array.
2. The current sense amplifier of claim 1, wherein the current sense amplifier further comprises: when configuring the common mode rejection ratio and the gain error of the current detection amplifier, the method comprises a common mode rejection ratio initial configuration step, a gain error configuration step and a common mode rejection ratio final configuration step which are sequentially executed;
executing a common mode rejection ratio initial configuration step, and configuring corresponding working states of the first switch array and the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio;
when the step of gain error configuration is executed, the corresponding working states of the first switch array and the second switch array are configured, so that the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with the target gain error;
and when the common mode rejection ratio final configuration step is executed, only configuring the corresponding working state of the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio.
3. The current sense amplifier of claim 1, wherein the current sense amplifier further comprises: when the target gain error of the current detection amplifier is G, the resistance value of the resistor Radd is Radd = (G-1) × R00 = (n + 1).
4. The current sense amplifier of claim 1, wherein the current sense amplifier further comprises: the switch control information generating circuit comprises a configuration signal control logic circuit (1), a shift register (2), a control word programming circuit (3) and an adder (4) which are sequentially connected, wherein the adder (4) is used for loading first switch control information of a switch array into the first switch array, and the adder (4) is used for loading second switch control information of the switch array required in the second switch array.
5. The current sense amplifier of claim 4, wherein the current sense amplifier further comprises: the adder (4) comprises a switch array first switch control information generation part and a switch array second switch control information part, wherein the switch array first switch control information generation part comprises a first addition unit (7), and the switch array second switch control information part comprises a second addition unit (8) and a third addition unit (9) matched with the second addition unit (8).
6. A method for configuring a common mode rejection ratio and a gain error is characterized in that: for configuring the current sense amplifier of claim 1 with common mode rejection ratio and gain error,
when configuring the common mode rejection ratio and the gain error of the current detection amplifier, the method comprises a common mode rejection ratio initial configuration step, a gain error configuration step and a common mode rejection ratio final configuration step which are executed in sequence;
executing a common mode rejection ratio initial configuration step, and configuring corresponding working states of the first switch array and the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio;
when the step of gain error configuration is executed, the corresponding working states of the first switch array and the second switch array are configured, so that the first equivalent resistance reference ratio and the second equivalent resistance reference ratio are matched with a target gain error;
and when the common mode rejection ratio final configuration step is executed, only configuring the corresponding working state of the second switch array so as to enable the first equivalent resistance reference ratio to be matched with the second equivalent resistance reference ratio.
7. The method of claim 6 wherein the common-mode rejection ratio and gain error are configurable by: the multi-row switch group control circuit comprises a configuration signal control logic circuit (1), a shift register (2), a control word programming circuit (3) and an adder (4), wherein the configuration signal control logic circuit, the shift register, the control word programming circuit and the adder are sequentially connected, first switch control information of a switch array is loaded into the first switch array through the adder (4), and second switch control information of the switch array, which is needed by loading in the second switch array, is loaded through the adder (4).
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| CN111130475A (en) * | 2019-12-31 | 2020-05-08 | 江苏润石科技有限公司 | Gain error configurable instrumentation amplifier and configuration method thereof |
| CN111342786A (en) * | 2020-04-21 | 2020-06-26 | 上海类比半导体技术有限公司 | Differential amplifier common mode rejection ratio and gain trimming circuit |
| CN112019217A (en) * | 2020-10-16 | 2020-12-01 | 浙江大学 | Pipelined successive approximation analog-to-digital converter and conversion method |
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| US10979009B2 (en) * | 2017-07-12 | 2021-04-13 | Honeywell International Inc. | Non-inverting differential amplifier with configurable common-mode output signal and reduced common-mode gain |
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| CN107888151A (en) * | 2016-09-30 | 2018-04-06 | 美国亚德诺半导体公司 | Amplifier calibration |
| US10637422B1 (en) * | 2018-10-31 | 2020-04-28 | Nxp B.V. | Gain compensation for an open loop programmable amplifier for high speed applications |
| CN111030624A (en) * | 2019-12-31 | 2020-04-17 | 江苏润石科技有限公司 | Common mode rejection ratio configurable instrumentation amplifier and configuration method thereof |
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