CN116170025A - Gain calibration method and device of delta-sigma ADC, chip and electronic equipment - Google Patents
Gain calibration method and device of delta-sigma ADC, chip and electronic equipment Download PDFInfo
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- CN116170025A CN116170025A CN202211729887.9A CN202211729887A CN116170025A CN 116170025 A CN116170025 A CN 116170025A CN 202211729887 A CN202211729887 A CN 202211729887A CN 116170025 A CN116170025 A CN 116170025A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/38—Calibration
- H03M3/382—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication
- H03M3/488—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication using automatic control
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Abstract
Embodiments of the present disclosure provide a gain calibration method, apparatus, chip and electronic device for a delta-sigma ADC, the apparatus including: a PGA, a delta-sigma modulator, a digital filter, a digital multiplier/divider, a digital controller, a switching module, and a reference voltage regulating circuit for providing a reference voltage to the delta-sigma modulator, the PGA, the delta-sigma modulator, the digital filter, the digital multiplier/divider being coupled in sequence, wherein the switching module is disposed between the reference voltage regulating circuit and the PGA and is configured to regulate the voltage provided by the reference voltage regulating circuit to the PGA under control of the digital controller; the digital controller is configured to adjust the voltage supplied to the PGA by the reference voltage adjusting circuit by controlling the switching module while controlling the operation mode and the operation object of the digital multiplier/divider unit, thereby obtaining the gain calibration coefficient of the delta-sigma ADC.
Description
Technical Field
Embodiments of the present disclosure relate to the field of ADC (Analog-to-Digital Converter) technology, and in particular, to a gain calibration method, apparatus, chip and electronic device of a delta-sigma ADC.
Background
Currently, some delta-sigma ADCs add a programmable gain amplifier (PGA, programmable Gain Amplifier) module to the signal path to achieve programmable control of the input signal range. In order to facilitate the use of users, most ADCs have the gain calibration function, and the user only needs to send corresponding calibration commands, so that the ADC can internally complete the gain calibration and eliminate gain errors. To accomplish internal gain calibration, the ADC internal is required to disconnect input pins INP and INN and provide the calibrated input full scale voltage VCAL. For an ADC without a PGA module, the calibration input full scale voltage VCAL is the reference voltage, i.e., INP and INN are respectively shorted to the input pins of the two reference voltages, VREFP and VREFN pins. For an ADC incorporating a PGA module, vcal= (VREFP-VREFN)/gain_pga, where gain_pga is the Gain of PGA. However, in the prior art, it is not possible to provide a very accurate calibration input full scale voltage during the gain calibration of a delta-sigma ADC.
Disclosure of Invention
An object of an embodiment of the present disclosure is to provide a gain calibration method, apparatus, chip and electronic device for a delta-sigma ADC, which calibrate a reference voltage generated by a reference voltage adjusting circuit in advance to obtain an accurate value of the reference voltage, thereby realizing high-precision gain calibration for the delta-sigma ADC under various gains.
To achieve the above object, according to a first aspect of the present disclosure, there is provided a gain calibration device of a delta-sigma ADC, comprising: a PGA, a delta-sigma modulator, a digital filter, a digital multiplier/divider, a digital controller, a switch module, and a reference voltage regulation circuit for providing a reference voltage to the delta-sigma modulator, the PGA, the delta-sigma modulator, the digital filter, the digital multiplier/divider being coupled in sequence. Wherein the switching module is disposed between the reference voltage adjusting circuit and the PGA, and is configured to adjust a voltage supplied to the PGA by the reference voltage adjusting circuit under the control of the digital controller; the digital controller is configured to adjust the voltage supplied to the PGA by the reference voltage adjusting circuit by controlling the switching module while controlling the operation mode and the operation object of the digital multiplier/divider unit, thereby obtaining the gain calibration coefficient of the delta-sigma ADC.
In some embodiments of the present disclosure, the digital controller is configured to: setting the gain of the PGA to 1, enabling the reference voltage regulating circuit to provide the reference voltage for the PGA by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be a specified value corresponding to the reference voltage, setting the divisor to be the output result of the digital filter, and setting the obtained output result of the digital multiplier/divider to be a first calibration parameter;
the digital controller is further configured to: setting the gain of the PGA to 1, setting the voltage provided by the reference voltage regulating circuit to the PGA as a calibrated input full-scale voltage corresponding to a specified gain by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a multiplier mode, setting one multiplier of the digital multiplier/divider to be the first calibration parameter, setting the other multiplier to be the output result of the digital filter, and setting the value of the output result of the digital multiplier/divider after shifting left by a specified bit to be a second calibration parameter, wherein the specified bit is a logarithmic value of the specified gain based on 2, and the quotient of the reference voltage and the calibrated input full-scale voltage is the specified gain;
the digital controller is further configured to: setting the gain of the PGA as the specified gain, controlling the switch module to enable the voltage provided by the reference voltage regulating circuit to the PGA to be the full-scale voltage of the calibration input, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be the second calibration parameter, setting the divisor to be the output result of the digital filter, and taking the obtained output result of the digital multiplier/divider as the gain calibration coefficient of the delta-sigma ADC.
In some embodiments of the present disclosure, the switching module includes: the control ends of the switches S1 to S5 are coupled to the digital controller 35, the first ends of the switches S1 to S2 are respectively and correspondingly coupled to the first input pin and the second input pin of the delta-sigma ADC, the second ends of the switches S1 to S2 are respectively and correspondingly coupled to the first input pin and the second input pin of the PGA, the first ends of the switches S3 to S4 are respectively and correspondingly coupled to the first input pin and the second input pin of the PGA, the first end of the switch S5 is coupled to the first input pin of the PGA, and the second ends of the switches S3 to S5 are respectively and correspondingly coupled to the first output pin, the second output pin and the third output pin of the reference voltage regulating circuit.
In some embodiments of the present disclosure, the third output pin of the reference voltage regulating circuit outputs a calibrated input full scale voltage corresponding to at least two specified gains.
In some embodiments of the disclosure, the reference voltage adjustment circuit is a resistive voltage divider circuit or a current voltage divider circuit.
According to a second aspect of embodiments of the present disclosure, there is provided a gain calibration method of a delta-sigma ADC, which is applied to a gain calibration device of a delta-sigma ADC, the gain calibration device of a delta-sigma ADC including: a PGA, a delta-sigma modulator, a digital filter, a digital multiplier/divider, a digital controller, a switching module, and a reference voltage regulation circuit for providing a reference voltage to the delta-sigma modulator, the PGA, the delta-sigma modulator, the digital filter, the digital multiplier/divider being coupled in sequence, the switching module being disposed between the reference voltage regulation circuit and the PGA, the method comprising: the gain calibration coefficient of the delta-sigma ADC is obtained by controlling the switching module to adjust the voltage supplied to the PGA by the reference voltage adjusting circuit while controlling the operation mode and the operation object of the digital multiplier/divider.
In some embodiments of the present disclosure, the adjusting the voltage provided to the PGA by the reference voltage adjusting circuit by controlling the switching module while controlling the operation mode and the operation object of the digital multiplier/divider, thereby obtaining the gain calibration coefficient of the delta-sigma ADC includes:
setting the gain of the PGA to 1, enabling the reference voltage regulating circuit to provide the reference voltage for the PGA by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be a specified value corresponding to the reference voltage, setting the divisor to be the output result of the digital filter, and setting the obtained output result of the digital multiplier/divider to be a first calibration parameter;
setting the gain of the PGA to 1, setting the voltage provided by the reference voltage regulating circuit to the PGA as a calibrated input full-scale voltage corresponding to a specified gain by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a multiplier mode, setting one multiplier of the digital multiplier/divider to be the first calibration parameter, setting the other multiplier to be the output result of the digital filter, and setting the value of the output result of the digital multiplier/divider after shifting left by a specified bit to be a second calibration parameter, wherein the specified bit is a logarithmic value of the specified gain based on 2, and the quotient of the reference voltage and the calibrated input full-scale voltage is the specified gain;
setting the gain of the PGA as the specified gain, controlling the switch module to enable the voltage provided by the reference voltage regulating circuit to the PGA to be the full-scale voltage of the calibration input, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be the second calibration parameter, setting the divisor to be the output result of the digital filter, and taking the obtained output result of the digital multiplier/divider as the gain calibration coefficient of the delta-sigma ADC.
In some embodiments of the present disclosure, the voltage provided by the reference voltage adjustment circuit to the PGA includes at least two calibrated input full scale voltages corresponding to specified gains.
According to a third aspect of the present disclosure, a chip is provided. The chip comprises gain calibration means of the delta-sigma ADC according to the first aspect of the disclosure.
According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a chip according to the third aspect of the present disclosure.
According to the embodiment of the disclosure, the reference voltage generated by the reference voltage regulating circuit is pre-calibrated, so that the accuracy of the calibration input full-scale voltage obtained after the voltage division is required is not excessively divided no matter the calibration input full-scale voltage in the reference voltage is provided by adopting a resistor voltage division mode or a current voltage division mode, and the accuracy requirement on the gain accuracy of the PGA is not excessively met, the accuracy requirement on the calibration input full-scale voltage is greatly reduced, and the gain calibration of the high-accuracy delta-sigma ADC under various gains is ensured.
Additional features and advantages of embodiments of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the embodiments of the disclosure. In the drawings:
FIG. 1 is a schematic diagram of an architecture of a variable gain delta-sigma ADC;
FIG. 2 is a schematic diagram of a delta-sigma ADC gain calibration architecture of a mask PGA;
fig. 3 is a schematic architecture diagram of a gain calibration device for a delta-sigma ADC provided in accordance with an embodiment of the disclosure;
fig. 4 is another architecture schematic of a gain calibration device of a delta-sigma ADC according to an embodiment of the disclosure;
fig. 5 is a circuit schematic of the reference voltage adjustment circuit 36 in a gain calibration device of a delta-sigma ADC according to an embodiment of the disclosure;
fig. 6 is a schematic diagram of yet another architecture of a gain calibration device for a delta-sigma ADC provided in accordance with an embodiment of the disclosure.
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
Fig. 1 is a schematic diagram of an architecture of a delta-sigma ADC 100 with variable gain. In order to generate the calibration input full-scale voltage meeting the precision, the calibration input full-scale voltages required by different PGA gains can be generated by means of voltage division, and the output result of the delta-sigma ADC is directly divided by the hexadecimal value corresponding to the expected calibration input full-scale voltage, so as to obtain the gain calibration coefficient of the delta-sigma ADC. This approach can be theoretically implemented, but it is difficult to generate a calibrated input full-scale voltage that meets the accuracy in an actual circuit, either by resistive or current division.
Fig. 2 is a schematic diagram of another delta-sigma ADC gain calibration architecture 200 of a masked PGA.
The PGA is shielded in the delta-sigma ADC internal gain calibration process, and the implementation mode is the same as that of PGA without PGA, which has extremely high requirement on the gain accuracy of PGA, so that the PGA is difficult to be implemented in an actual circuit.
Therefore, the embodiments of the present disclosure provide a gain calibration method, apparatus, chip and electronic device for a delta-sigma ADC, which calibrate a reference voltage generated by a reference voltage adjusting circuit in advance to obtain an accurate value of the reference voltage, thereby realizing high-precision gain calibration for the delta-sigma ADC under various gains.
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Referring to fig. 3, an exemplary block diagram of a delta-sigma ADC gain calibration apparatus 300 is provided for embodiments of the present disclosure. As shown in fig. 3, an embodiment of the present disclosure provides a gain calibration apparatus 300 of a delta-sigma ADC, comprising: the PGA31, the delta-sigma modulator 32, the digital filter 33, the digital multiplier/divider 34, the digital controller 35, the switching module 37, and the reference voltage adjusting circuit 36 for providing the reference voltage to the delta-sigma modulator 32, the PGA31, the delta-sigma modulator 32, the digital filter 33, and the digital multiplier/divider 34 are sequentially coupled.
Wherein the switch module 37 is disposed between the reference voltage adjusting circuit 36 and the PGA31, and is configured to adjust the voltage supplied to the PGA31 by the reference voltage adjusting circuit 36 under the control of the digital controller 35; the digital controller 35 is configured to adjust the voltage supplied to the PGA31 by the reference voltage adjusting circuit 36 by controlling the switching module 37, and simultaneously control the operation mode and the operation object of the digital multiplier/divider 34, thereby obtaining the gain calibration coefficient of the delta-sigma ADC.
Specifically, as shown in fig. 4, the switch module 37 includes: switches S1 to S5. The control ends of the switches S1 to S5 are coupled to the digital controller 35, the first ends of the switches S1 to S2 are respectively coupled to the first input pin INP and the second input pin INN of the delta-sigma ADC, the second ends of the switches S1 to S2 are respectively coupled to the first input pin pga_p and the second input pin pga_n of the PGA31, the first ends of the switches S3 to S4 are respectively coupled to the first input pin pga_p and the second input pin pga_n of the PGA31, the first ends of the switches S5 are coupled to the first input pin pga_p of the PGA31, the second ends of the switches S3 to S5 are respectively coupled to the first output pin VREFP, the second output pin vrn and the third output pin VCAL of the reference voltage regulating circuit 36, and the first output pin VREFP and the second output pin VREFN of the reference voltage regulating circuit 36 are respectively coupled to the delta-sigma modulator 32. Specifically, the digital controller 35 is configured to: the gain of the PGA31 is set to 1, and the reference voltage adjusting circuit 36 is caused to supply the reference voltage to the PGA31 by controlling the switching module 37. That is, the switches S1-S2, S5 are controlled to be opened, i.e., to disconnect the first input pin INP of the delta-sigma ADC from the first input pin pga_p of the PGA31, to disconnect the second input pin INN of the delta-sigma ADC from the second input pin pga_n of the PGA31, and to disconnect the third output pin VCAL of the reference voltage regulator circuit 36 from the first input pin pga_p of the PGA 31. The switches S3 to S4 are controlled to be closed, i.e. the first input pin pga_p and the second input pin pga_n of the PGA31 are respectively coupled to the first output pin VREFP and the second output pin VREFN of the reference voltage regulator 36, and the reference voltage regulator 36 provides the reference voltage to the PGA31, i.e. the voltage difference value between the first output pin VREFP and the second output pin VREFN thereof. In addition, the operation mode of the digital multiplier/divider circuit 34 is set to a divider mode, and the dividend of the digital multiplier/divider circuit 34 is set to a specified binary value corresponding to the reference voltage, and in the embodiment of the present disclosure, taking a delta-sigma ADC of 16 bits as an example, the specified binary value corresponding to the reference voltage is 0x7FFF (i.e., theoretically, a differential pressure value between the first output pin VREFP and the second output pin VREFN of the reference voltage regulator circuit 36), the divisor is set to the output result data_ cic1 of the digital filter 33, and the obtained output result of the digital multiplier/divider circuit 34 is set to the first calibration parameter cal_data1, as shown in the following formula (1):
cal_data1=0x7fff/data_ cic1 equation (1)
After the first calibration parameter cal_data1 is obtained, the digital filter 33 is reset.
Thereafter, the digital controller 35 is further configured to: the gain of the PGA31 is set to 1, and the voltage supplied to the PGA31 by the reference voltage adjusting circuit 36 is set to the calibrated input full-scale voltage corresponding to the specified gain by controlling the switching module 37. That is, the switches S1 to S3 are controlled to be opened, i.e., to disconnect the coupling between the first input pin INP of the delta-sigma ADC and the first input pin pga_p of the PGA31, to disconnect the coupling between the second input pin INN of the delta-sigma ADC and the second input pin pga_n of the PGA31, and to disconnect the coupling between the first output pin VREFP of the reference voltage regulator circuit 36 and the first input pin pga_p of the PGA 31. The switches S4-S5 are all closed, i.e. the second input pin pga_n of PGA31 is coupled to the second output pin VREFN of reference voltage regulator circuit 36, and the first input pin pga_p of PGA31 and the third output pin VCAL of reference voltage regulator circuit 36. When the switches S4 to S5 are all closed, the voltage provided by the reference voltage adjusting circuit 36 to the PGA31 is the calibrated input full-scale voltage corresponding to the specified gain, that is, the calibrated input full-scale voltage is subjected to analog-to-digital conversion, so as to obtain the analog-to-digital conversion value corresponding to the calibrated input full-scale voltage. Meanwhile, the operation mode of the digital multiplier/divider 34 is set to a multiplier mode, one multiplier of the digital multiplier/divider 34 is set to the first calibration parameter cal_data1, the other multiplier is set to the output result data_ cic2 of the digital filter 33, and a value obtained by shifting the output result of the digital multiplier/divider 34 left by a specified bit is set to the second calibration parameter cal_data2, wherein the specified bit is a logarithmic value of the specified gain based on 2, and the quotient of the reference voltage and the calibrated input full-scale voltage is the specified gain.
In particular, the above-mentioned shift principle is implemented according to the logarithmic value of the specified gain corresponding to the calibrated input full scale voltage based on 2, for example, log when the specified gain is 1 2 1=0, meaning that bit is 0, i.e. the output result of the digital multiplier/divider 34 is directly taken as the second calibration parameter cal_data2 without shifting; when the specified gain is 2, then log 2 2=1, meaning that bit 1, i.e. the number by +.The output result of the divider 34 is shifted left by 1 bit, and one bit of 0 is added to the right after the shift, and a second calibration parameter cal_data2 is obtained after the addition; when the specified gain is 4, then log 2 4=2, namely, the bit is designated as 2, namely, the output result of the digital multiplier/divider 34 is shifted to the left by 2 bits, two bits of 0 are complemented on the right after the shift, and the second calibration parameter cal_data2 is obtained after the bit complementation; when the specified gain is 8, then log 2 8=3, which means that bit 3, i.e. the output result of the digital multiplier/divider 34 is shifted left by 3 bits, and the shifted right is complemented by three bits 0, and the complemented bit is then obtained to obtain the second calibration parameter cal_data2.
For the reference voltage adjusting circuit 36, a resistor voltage dividing circuit or a current voltage dividing circuit may be used. As shown in fig. 5, when the reference voltage adjusting circuit 36 is a resistor divider circuit, the value of the resistor R can be selected according to the power consumption and the matching requirement of the circuit layout. The third output pin VCAL of the reference voltage adjusting circuit 36 may be one or more according to the setting of the designated gain. When the selectable specified gains are 2, 4, 8, three pins VCAL2, VCAL4, VCAL8 are corresponding. As shown in fig. 6, when the specified gain is 2, the digital controller 35 controls the switch S5 to be coupled to the VCAL2 pin of the reference voltage adjusting circuit 36; when the specified gain is 4, then digital controller 35 controls switch S5 to be coupled to the VCAL4 pin of reference voltage regulation circuit 36; when the specified gain is 8, the digital controller 35 controls the switch S5 to be coupled to the VCAL8 pin of the reference voltage adjusting circuit 36.
After obtaining the first calibration parameter cal_data1 and the second calibration parameter cal_data2, the digital controller 35 is further configured to: setting the gain of the PGA31 to the specified gain, the voltage supplied to the PGA31 by the reference voltage adjusting circuit 36 is made the calibrated input full-scale voltage by controlling the switching module 37. That is, the switches S1 to S3 are controlled to be opened, i.e., to disconnect the coupling between the first input pin INP of the delta-sigma ADC and the first input pin pga_p of the PGA31, to disconnect the coupling between the second input pin INN of the delta-sigma ADC and the second input pin pga_n of the PGA31, and to disconnect the coupling between the first output pin VREFP of the reference voltage regulator circuit 36 and the first input pin pga_p of the PGA 31. The switches S4-S5 are all closed, i.e. the second input pin pga_n of PGA31 is coupled to the second output pin VREFN of reference voltage regulator circuit 36, and the first input pin pga_p of PGA31 and the third output pin VCAL of reference voltage regulator circuit 36. Meanwhile, the operation mode of the digital multiplier/divider 34 is set as a divider mode, the dividend of the digital multiplier/divider 34 is set as the second calibration parameter cal_data2, the divisor is set as the output result data_ cic3 of the digital filter, and the obtained output result of the digital multiplier/divider is used as the gain calibration coefficient coeff_gain, as shown in the following formula (2):
coeff_gain=cal_data2/data_ cic3 equation (2)
According to the embodiment of the disclosure, the reference voltage generated by the reference voltage regulating circuit is pre-calibrated, so that the accuracy of the calibrated input full-scale voltage obtained after the voltage division is not required to be excessively divided no matter whether the resistor voltage division or the current voltage division is adopted to provide the calibrated input full-scale voltage in the reference voltage, and the gain accuracy of the PGA is not excessively required.
The embodiment of the disclosure further provides a gain calibration method of a delta-sigma ADC, based on the gain calibration device 300 of the delta-sigma ADC, the gain calibration device 300 of the delta-sigma ADC includes: PGA31, delta-sigma modulator 32, digital filter 33, digital multiplier/divider 34, digital controller 35, switching module 37, and reference voltage regulating circuit 36 for providing a reference voltage to said delta-sigma modulator 32, said PGA31, said delta-sigma modulator 32, said digital filter 33, said digital multiplier/divider 34 being coupled in sequence, said switching module 37 being disposed between said reference voltage regulating circuit 36 and said PGA31, said method comprising, in connection with the description of fig. 3-6: the gain calibration coefficient of the delta-sigma ADC is obtained by controlling the switching module to adjust the voltage supplied to the PGA by the reference voltage adjusting circuit while controlling the operation mode and the operation object of the digital multiplier/divider.
Specifically, the gain calibration coefficient of the delta-sigma ADC may be obtained by:
setting the gain of the PGA31 to 1, the reference voltage adjusting circuit 36 supplies the reference voltage to the PGA31 by controlling the switch module 37, that is, the switches S1 to S2, S5 are all opened, and the switches S3 to S4 are all closed. Meanwhile, the operation mode of the digital multiplier/divider 34 is set as a divider mode, and the dividend of the digital multiplier/divider 34 is set as a specified binary value corresponding to the reference voltage. In the embodiment of the disclosure, taking a 16-bit delta-sigma ADC as an example, the designated binary value corresponding to the reference voltage is 0x7FFF (i.e., theoretically, the voltage difference value between the first output pin VREFP and the second output pin VREFN of the reference voltage regulator circuit 36). In addition, the divisor of the digital multiplier/divider 34 is set as the output data_ cic1 of the digital filter 33, and the obtained output of the digital multiplier/divider 34 is set as the first calibration parameter cal_data1 by the above formula (1).
The gain of the PGA31 is set to 1, and the switch module 37 is controlled to make the voltage provided by the reference voltage adjusting circuit 36 to the PGA31 be the calibrated input full-scale voltage corresponding to the specified gain, i.e. the switches S1 to S3 are all opened, and the switches S4 to S5 are all closed. The full-scale voltage of the calibration input is the quotient of the reference voltage and the specified gain, namely, the full-scale voltage of the calibration input is subjected to analog-to-digital conversion to obtain an analog-to-digital conversion value corresponding to the full-scale voltage of the calibration input. Meanwhile, the operation mode of the digital multiplier/divider 34 is set to a multiplier mode, one multiplier of the digital multiplier/divider 34 is set to the first calibration parameter cal_data1, the other multiplier is set to the output result data_ cic2 of the digital filter 33, and a value after shifting the output result of the digital multiplier/divider 34 left by a specified bit, which is a logarithmic value of the specified gain based on 2, is set to the second calibration parameter.
In particular, the above-mentioned shift principle is implemented according to the logarithmic value of the specified gain based on 2, for example, log when the specified gain is 1 2 1=0, meaning that bit is 0, i.e. the output result of the digital multiplier/divider 34 is directly taken as the second calibration parameter cal_data2 without shifting; when the specified gain is 2, then log 2 2=1, namely, the output result of the digital multiplier/divider 34 is shifted left by 1 bit, and then a bit of 0 is added to the right after the shift, and a second calibration parameter cal_data2 is obtained after the bit addition; when the specified gain is 4, then log 2 4=2, namely, the bit is designated as 2, namely, the output result of the digital multiplier/divider 34 is shifted to the left by 2 bits, two bits of 0 are complemented on the right after the shift, and a second calibration parameter cal_data2 is obtained after the bit complementation; when the specified gain is 8, then log 2 8=3, which means that bit 3, i.e. the output result of the digital multiplier/divider 34 is shifted left by 3 bits, and the shifted right is complemented by three bits 0, and the complemented bit is then obtained to obtain the second calibration parameter cal_data2. Referring to the reference voltage regulating circuit 36 example provided in fig. 5, the third output pin VCAL for the reference voltage regulating circuit 36 may be one or more according to the setting of the specified gain. When the selectable specified gains are 2, 4, 8, three pins VCAL2, VCAL4, VCAL8 are corresponding. That is, when the specified gain is 2, switch S5 is coupled to the VCAL2 pin, and the reference voltage regulator circuit 36 provides the PGA31 with a calibrated input full scale voltage that is one half of the reference voltage; when the specified gain is 4, switch S5 is coupled to the VCAL4 pin, and the reference voltage adjustment circuit 36 provides a calibrated input full scale voltage to PGA31 that is one quarter of the reference voltage; when the specified gain is 8, switch S5 is coupled to the VCAL8 pin, and the reference voltage regulator circuit 36 provides a calibrated input full scale voltage to the PGA31 that is one eighth of the reference voltage.
After obtaining the first calibration parameter and the second calibration parameter, obtaining a gain calibration coefficient of the delta-sigma ADC by:
setting the gain of the PGA31 to the specified gain, the reference voltage adjusting circuit 36 supplies the voltage to the PGA31 as the calibrated input full-scale voltage by controlling the switch module 37, that is, the switches S1 to S3 are all open, and the switches S4 to S5 are all closed. Meanwhile, the operation mode of the digital multiplier/divider 34 is set as a divider mode, while the dividend of the digital multiplier/divider 34 is set as the second calibration parameter cal_data2, the divisor is set as the output result data_ cic3 of the digital filter 33, and the obtained output result of the digital multiplier/divider is taken as the gain calibration coefficient coeff_gain by the above formula (2).
According to the embodiment of the disclosure, the reference voltage generated by the reference voltage regulating circuit is calibrated in advance to obtain the accurate value of the reference voltage, so that the gain calibration of the high-precision delta-sigma ADC under various gains is realized.
The embodiment of the disclosure also provides a chip. The chip comprises gain calibration means of a delta-sigma ADC according to embodiments of the disclosure. The chip is, for example, a chip for performing high-precision analog-digital signal conversion.
The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a high-precision medical device, an intelligent control device, or the like.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A gain calibration device for a delta-sigma ADC, comprising: a programmable gain amplifier PGA, a delta-sigma modulator, a digital filter, a digital multiplier/divider, a digital controller, a switching module, and a reference voltage regulation circuit for providing a reference voltage to the delta-sigma modulator, the PGA, the delta-sigma modulator, the digital filter, the digital multiplier/divider being coupled in sequence,
wherein the switching module is disposed between the reference voltage adjusting circuit and the PGA, and is configured to adjust a voltage supplied to the PGA by the reference voltage adjusting circuit under the control of the digital controller;
the digital controller is configured to adjust the voltage supplied to the PGA by the reference voltage adjusting circuit by controlling the switching module while controlling the operation mode and the operation object of the digital multiplier/divider unit, thereby obtaining the gain calibration coefficient of the delta-sigma ADC.
2. The delta-sigma ADC gain calibration device of claim 1, wherein the digital controller is configured to: setting the gain of the PGA to 1, enabling the reference voltage regulating circuit to provide the reference voltage for the PGA by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be a specified value corresponding to the reference voltage, setting the divisor to be the output result of the digital filter, and setting the obtained output result of the digital multiplier/divider to be a first calibration parameter;
the digital controller is further configured to: setting the gain of the PGA to 1, setting the voltage provided by the reference voltage regulating circuit to the PGA as a calibrated input full-scale voltage corresponding to a specified gain by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a multiplier mode, setting one multiplier of the digital multiplier/divider to be the first calibration parameter, setting the other multiplier to be the output result of the digital filter, and setting the value of the output result of the digital multiplier/divider after shifting left by a specified bit to be a second calibration parameter, wherein the specified bit is a logarithmic value of the specified gain based on 2, and the quotient of the reference voltage and the calibrated input full-scale voltage is the specified gain;
the digital controller is further configured to: setting the gain of the PGA as the specified gain, controlling the switch module to enable the voltage provided by the reference voltage regulating circuit to the PGA to be the full-scale voltage of the calibration input, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be the second calibration parameter, setting the divisor to be the output result of the digital filter, and taking the obtained output result of the digital multiplier/divider as the gain calibration coefficient of the delta-sigma ADC.
3. The delta-sigma ADC gain calibration device of claim 1, wherein the switching module comprises: the switches S1 to S5,
the control ends of the switches S1 to S5 are coupled to the digital controller 35, the first ends of the switches S1 to S2 are respectively and correspondingly coupled to a first input pin and a second input pin of the delta-sigma ADC, the second ends of the switches S1 to S2 are respectively and correspondingly coupled to a first input pin and a second input pin of the PGA, the first ends of the switches S3 to S4 are respectively and correspondingly coupled to a first input pin and a second input pin of the PGA, the first end of the switch S5 is coupled to a first input pin of the PGA, and the second ends of the switches S3 to S5 are respectively and correspondingly coupled to a first output pin, a second output pin and a third output pin of the reference voltage regulating circuit.
4. The delta-sigma ADC gain calibration apparatus of claim 1, wherein the third output pin of the reference voltage adjustment circuit outputs a calibrated input full-scale voltage corresponding to at least two specified gains.
5. The delta-sigma ADC gain calibration device of claim 1, wherein the reference voltage adjustment circuit is a resistive voltage divider circuit or a current divider circuit.
6. A gain calibration method of a delta-sigma ADC, wherein the gain calibration method of the delta-sigma ADC is applied to a gain calibration device of the delta-sigma ADC, the gain calibration device of the delta-sigma ADC comprising: a programmable gain amplifier, PGA, delta-sigma modulator, digital filter, digital multiplier/divider, digital controller, switching module, and reference voltage regulation circuit for providing a reference voltage to the delta-sigma modulator, the PGA, delta-sigma modulator, digital filter, digital multiplier/divider being coupled in sequence, the switching module being disposed between the reference voltage regulation circuit and the PGA, the method comprising:
the gain calibration coefficient of the delta-sigma ADC is obtained by controlling the switching module to adjust the voltage supplied to the PGA by the reference voltage adjusting circuit while controlling the operation mode and the operation object of the digital multiplier/divider.
7. The method according to claim 6, wherein the adjusting the voltage supplied to the PGA by the reference voltage adjusting circuit by controlling the switching module while controlling the operation mode and the operation object of the digital multiplier/divider unit, thereby obtaining the gain calibration coefficient of the delta-sigma ADC comprises:
setting the gain of the PGA to 1, enabling the reference voltage regulating circuit to provide the reference voltage for the PGA by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be a specified value corresponding to the reference voltage, setting the divisor to be the output result of the digital filter, and setting the obtained output result of the digital multiplier/divider to be a first calibration parameter;
setting the gain of the PGA to 1, setting the voltage provided by the reference voltage regulating circuit to the PGA as a calibrated input full-scale voltage corresponding to a specified gain by controlling the switch module, setting the operation mode of the digital multiplier/divider to be a multiplier mode, setting one multiplier of the digital multiplier/divider to be the first calibration parameter, setting the other multiplier to be the output result of the digital filter, and setting the value of the output result of the digital multiplier/divider after shifting left by a specified bit to be a second calibration parameter, wherein the specified bit is a logarithmic value of the specified gain based on 2, and the quotient of the reference voltage and the calibrated input full-scale voltage is the specified gain;
setting the gain of the PGA as the specified gain, controlling the switch module to enable the voltage provided by the reference voltage regulating circuit to the PGA to be the full-scale voltage of the calibration input, setting the operation mode of the digital multiplier/divider to be a divider mode, setting the divisor of the digital multiplier/divider to be the second calibration parameter, setting the divisor to be the output result of the digital filter, and taking the obtained output result of the digital multiplier/divider as the gain calibration coefficient of the delta-sigma ADC.
8. The method of claim 6, wherein the voltage provided to the PGA by the reference voltage adjustment circuit includes at least two calibrated input full scale voltages corresponding to the specified gains.
9. Chip, characterized in that it comprises a gain calibration device of a delta-sigma ADC according to any of claims 1-5.
10. An electronic device comprising a chip according to claim 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117353739A (en) * | 2023-12-04 | 2024-01-05 | 上海芯炽科技集团有限公司 | ADC full-scale calibration method for multi-gain gears |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117353739A (en) * | 2023-12-04 | 2024-01-05 | 上海芯炽科技集团有限公司 | ADC full-scale calibration method for multi-gain gears |
| CN117353739B (en) * | 2023-12-04 | 2024-03-26 | 上海芯炽科技集团有限公司 | ADC full-scale calibration method for multi-gain gears |
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