CN114334912A - Package structure and method for manufacturing the same - Google Patents
Package structure and method for manufacturing the same Download PDFInfo
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- CN114334912A CN114334912A CN202011047601.XA CN202011047601A CN114334912A CN 114334912 A CN114334912 A CN 114334912A CN 202011047601 A CN202011047601 A CN 202011047601A CN 114334912 A CN114334912 A CN 114334912A
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Abstract
A package structure and a method for manufacturing the same are provided, which includes a chip, a redistribution circuit structure, a molding material structure, and an EMI shielding structure. The redistribution circuit structure is disposed on the chip and electrically connected thereto. The molding material structure is arranged around the periphery of the chip and the redistribution circuit structure. The electromagnetic interference shielding structure is arranged around the periphery of the molding material structure. The molding material structure is arranged around the periphery of the chip and the rewiring circuit structure so as to provide multi-surface protection and reinforcement for the structure. The electromagnetic interference shielding structure is arranged around the periphery of the molding material structure so as to provide multi-surface electromagnetic interference protection for the chip and the rewiring circuit structure. Thereby achieving the purposes of improving the structural strength, using reliability and stability.
Description
Technical Field
The present invention relates to a package structure and a method for manufacturing the same, and more particularly, to a package structure and a method for manufacturing the same, which can effectively protect the strength of the package structure and prevent electromagnetic interference.
Background
In a conventional packaging method for chips, a plurality of dicing trenches are formed on the back surface of a wafer. And then forming a molding material layer on the back surface of the wafer and in the cutting groove. And arranging a rewiring circuit structure on the front surface of the wafer. And finally, cutting the wafer into a plurality of chips along the cutting grooves.
To traditional chip earlier set up the shaping precoat in the preparation, set up rewiring circuit structure again, lead to the outside that can't effectively protect rewiring circuit structure. So that the redistribution circuit structure is easily damaged in the subsequent assembly process.
In addition, the conventional chip is not provided with any structure for resisting electromagnetic interference in manufacturing, so that the chip is easily influenced by the electromagnetic interference when being used subsequently. When the influence is slight, only the chip performance may be reduced. However, if the influence is serious, the chip may be damaged and may not be used.
Disclosure of Invention
In view of the above-mentioned problems of the prior art, it is a primary object of the present invention to provide a package structure and a method for manufacturing the same, in which a molding material layer and an electromagnetic interference shielding structure are sequentially disposed on the periphery of a chip and a redistribution circuit structure disposed on the chip, so as to provide protection and reinforcement for the structure and protection against electromagnetic interference for the chip and the redistribution circuit structure. Thereby achieving the purposes of improving the structural strength, using reliability and stability.
To achieve the above object, a package structure is provided, which includes: a chip; a redistribution line structure disposed on the chip and forming an electrical connection; the molding die material structure is arranged at the periphery of the chip and the redistribution circuit structure; and the electromagnetic interference shielding structure is arranged at the periphery of the molding material structure.
Optionally, the molding material structure includes: the first molding material layer is arranged on a plurality of outer side surfaces of the chip and a plurality of outer side surfaces of the redistribution circuit structure; and the second molding material layer is arranged on the bottom surface of the chip and is connected with the first molding material layer.
Optionally, the emi shielding structure includes a first emi shielding layer disposed on the outer sides of the first molding material layer, the outer sides of the second molding material layer, and the bottom surface.
Optionally, the molding material structure includes a first molding material layer, and the first molding material layer is disposed on a plurality of outer sides of the chip and a plurality of outer sides of the redistribution circuit structure; the electromagnetic interference shielding structure comprises a first electromagnetic interference shielding layer arranged on a plurality of outer side surfaces of the first molding material layer.
Optionally, a plurality of grooves are further disposed on the bottom surface of the second molding material layer, and the plurality of grooves are filled with the second electromagnetic interference shielding layer.
Optionally, a plurality of openings penetrating through the second molding material layer are further disposed on the second molding material layer, and the first electromagnetic interference shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.
Optionally, the molding material structure includes: the first molding material layer is arranged on the plurality of outer side surfaces of the chip and the plurality of outer side surfaces and the top surface of the rewiring circuit structure, and the electric connection layer part arranged on the top surface of the rewiring circuit structure is exposed out of the first molding material layer; and the second molding material layer is arranged on the bottom surface of the chip and is connected with the first molding material layer.
Optionally, the emi shielding structure includes a first emi shielding layer disposed on the outer sides of the first molding material layer, the outer sides of the second molding material layer, and the bottom surface.
Optionally, a plurality of grooves are further disposed on the second molding material layer, and the plurality of grooves are filled with the first electromagnetic interference shielding layer.
Optionally, a plurality of openings penetrating through the second molding material layer are further disposed on the second molding material layer, and the first electromagnetic interference shielding layer fills the plurality of openings and is connected to the chip.
Optionally, the emi shielding structure comprises: the first electromagnetic interference shielding layer is arranged on the plurality of outer side surfaces of the first molding material layer, the plurality of outer side surfaces of the second molding material layer and the bottom surface; and the second electromagnetic interference shielding layer is arranged on the first molding material layer on the top surface of the redistribution circuit structure and is separated from the exposed electric connection layer.
Optionally, a plurality of grooves are further disposed on the second molding material layer, and the plurality of grooves are filled with the first electromagnetic interference shielding layer.
Optionally, a plurality of openings penetrating through the second molding material layer are further disposed on the second molding material layer, and the first electromagnetic interference shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.
To achieve the above object, a method for manufacturing a package structure includes the following steps: providing more than one wafer; forming a redistribution circuit structure on the top surface of the wafer; forming a plurality of first cutting grooves on the wafer and the corresponding redistribution circuit structure so as to form a plurality of chips provided with the corresponding redistribution circuit structure; forming a first molding material layer in a molding material structure on the wafer and the corresponding redistribution circuit structure and the corresponding first cutting groove; processing from the bottom surface of the wafer to expose the bottom surfaces of the chips of the wafer and a first molding material layer formed in a first cutting groove of the wafer, and forming a second molding material layer in the molding material structure on the bottom surfaces of the chips of the wafer and the exposed first molding material layer; forming a plurality of second cutting grooves along the first molding material layer formed in the plurality of first cutting grooves in the wafer and the corresponding second molding material layer to separate the plurality of chips; forming an electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on the chip; the redistribution circuit structure on each chip is exposed.
Optionally, in the step of exposing the redistribution routing structures on the chips, the first molding material layer and the corresponding portions of the emi shielding structures on the top surfaces of the redistribution routing structures on the chips are removed, so that the top surfaces of the redistribution routing structures on the chips are exposed, and the electrical connection layers formed on the redistribution routing structures are exposed.
Optionally, before the step of forming the electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on each chip, forming a plurality of grooves on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form the heat dissipation structure.
Optionally, before the step of forming the electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on each chip, forming a plurality of openings penetrating through the second molding material layer on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected with the bottom surface of the chip.
Optionally, in the step of exposing the redistribution structure on each of the chips, a portion of the first molding material layer and a corresponding portion of the emi shielding structure are removed, a remaining portion of the first molding material layer is covered on a top surface of the redistribution structure, and a portion of the electrical connection layer formed on the redistribution structure is exposed.
Optionally, before the step of forming the electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on each chip, forming a plurality of grooves on the second molding material layer; when the EMI shielding structure is formed, the EMI shielding structure fills the plurality of grooves.
Optionally, before the step of forming the electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on each chip, forming a plurality of openings penetrating through the second molding material layer on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected with the bottom surface of the chip.
Optionally, in the step of forming the electromagnetic interference shielding structure on the peripheries of the first molding material layer and the second molding material layer on each of the chips, a first electromagnetic interference shielding layer of the electromagnetic interference shielding structure is formed on a plurality of outer sides of the first molding material layer on each of the chips and on a plurality of outer sides and a bottom of the second molding material layer on each of the chips; and forming a second electromagnetic interference shielding layer of the electromagnetic interference shielding structure on the first molding material layer of the redistribution circuit structure of each chip, wherein the second electromagnetic interference shielding layer is arranged at a distance from the exposed electric connection layer.
Optionally, before the step of forming the electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on each chip, forming a plurality of grooves on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form the heat dissipation structure.
Optionally, before the step of forming the electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on each chip, forming a plurality of openings penetrating through the second molding material layer on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected with the bottom surface of the chip.
Optionally, when the number of the wafers is multiple; arranging the wafer on a temporary bearing plate; arranging a corresponding redistribution circuit structure on the top surface of the wafer and forming electrical connection; forming the plurality of first cutting grooves on the wafer and the corresponding redistribution routing structure so as to form a plurality of chips provided with the corresponding redistribution routing structure; arranging a first molding material layer in the molding material structure on the wafer and the corresponding redistribution circuit structure and in the corresponding first cutting groove; removing the temporary bearing plate, and processing from the bottom surface of each wafer to expose the bottom surface of the chip of each wafer and the first molding material layer arranged in the first cutting groove of each wafer, and arranging the second molding material layer in the molding material structure on the bottom surface of the chip of each wafer and the exposed first molding material layer; forming a plurality of second cutting grooves along the first molding material layer arranged in the plurality of first cutting grooves and the corresponding second molding material layer in each wafer so as to separate the plurality of chips; arranging an electromagnetic interference shielding structure on the peripheries of the first molding material layer and the second molding material layer on each chip; the redistribution circuit structure on each chip is exposed.
According to the above, the forming mold layer and the redistribution circuit structure are sequentially arranged on the periphery of the chip and the redistribution circuit structure, so as to provide multi-surface protection and reinforcement for the structure and multi-surface electromagnetic interference protection, thereby achieving the purpose of improving the structural strength, the use reliability and the stability.
For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic diagram of a first embodiment of a package structure of the present invention.
Fig. 2 is a flow chart of a method for manufacturing a first embodiment of the package structure of the present invention.
Fig. 3A is a first schematic diagram of a manufacturing process of a first embodiment of the package structure of the invention.
Fig. 3B is a second schematic diagram of a manufacturing process of the first embodiment of the package structure of the invention.
Fig. 4 is a third schematic diagram of a manufacturing process of the first embodiment of the package structure of the present invention.
Fig. 5 is a fourth schematic diagram illustrating a manufacturing process of the first embodiment of the package structure of the present invention.
Fig. 6 is a fifth schematic diagram illustrating a manufacturing process of the first embodiment of the package structure of the present invention.
Fig. 7 is a sixth schematic diagram illustrating a manufacturing process of the first embodiment of the package structure of the present invention.
Fig. 8 is a seventh schematic diagram illustrating a manufacturing process of the first embodiment of the package structure of the present invention.
Fig. 9 is an eighth schematic diagram illustrating a manufacturing process of the first embodiment of the package structure of the present invention.
Fig. 10 is a diagram of a second embodiment of the package structure of the present invention.
Fig. 11 is a schematic diagram of a third embodiment of the package structure of the present invention.
Fig. 12 is a diagram of a fourth embodiment of the package structure of the present invention.
Fig. 13 is a diagram of a fifth embodiment of the package structure of the present invention.
Fig. 14 is a schematic diagram of a sixth embodiment of the package structure of the present invention.
Fig. 15 is a diagram of a seventh embodiment of the package structure of the present invention.
Fig. 16 is a diagram illustrating an eighth embodiment of the package structure of the present invention.
Fig. 17 is a diagram of a ninth embodiment of the package structure of the present invention.
Fig. 18 is a schematic diagram of a tenth embodiment of the package structure of the present invention.
Reference numerals
10 chip
11 third bottom surface
12 lateral surface
100 wafer
101 first top surface
102 first bottom surface
103 first cutting groove
104 second cutting groove
20 redistribution routing structure
21 dielectric layer
211 second top surface
212 second bottom surface
213 outer side
22 circuit layer
23 electric connection layer
30 shaping mould material structure
31 first molding material layer
311 fourth top surface
312 lateral surface
32 second Molding Material layer
321 fourth bottom surface
322 outer side
323 recess
323A opening
40 electromagnetic interference shielding structure
41 first electromagnetic interference shielding layer
42 second electromagnetic interference shielding layer
A temporary carrier plate
S51-S58
Detailed Description
Referring to fig. 1, a first embodiment of a package structure according to the present invention includes a chip 10, a redistribution circuit structure 20, a molding compound structure 30, and an emi shielding structure 40. The redistribution routing structure 20 is disposed on the chip 10, and the redistribution routing structure 20 is electrically connected to the chip 10. The molding material structure 30 is disposed at the periphery of the chip 10 and the redistribution circuit structure 20. The emi shielding structure 40 is disposed at the periphery of the molding material structure 30.
Regarding the manufacturing method of the package structure, please refer to the flowchart shown in fig. 2, and the following description is provided.
Please refer to fig. 2, 3A, and 3B, as shown in step S51 in fig. 2. More than one wafer 100 is provided. In one example, to improve the production efficiency, a plurality of wafers 100 may be provided at a time and disposed on the temporary carrier plate a. The temporary carrier board a may be a Printed circuit board (Printed circuit board), a glass substrate, a ceramic substrate and a carrier fixture. In an example, the shape of the wafer 100 disposed on the temporary carrier plate a is not limited, and may be various shapes such as a complete circle, a semicircle, and an 1/4 circle. Therefore, the wafers 100 with different shapes can be processed at one time, and the production efficiency is greatly improved. Moreover, the manufacturing method of the conventional PCB is used to process the subsequent circuit manufacturing of the wafer 100, so that the production cost can be effectively reduced. Basically, each wafer 100 is composed of a substrate and a plurality of circuit structures disposed on the substrate at intervals. The wafer 100 has a first top surface 101 and a first bottom surface 102 opposite to each other. In one example, the first top surface 101 is an active surface of a circuit structure on the wafer 100. The first bottom surface 102 is a bottom surface of a substrate of the wafer 100. For convenience of explanation, in the following steps, a plurality of wafers 100 will be simultaneously fabricated. But may be fabricated in the same manner whether a single wafer 100 or multiple wafers 100 are fabricated. The only difference is that when step S55 is executed, since a plurality of wafers 100 are disposed on the temporary carrier plate a, the temporary carrier plate a needs to be removed first for the way of simultaneously manufacturing a plurality of wafers 100. For the manufacturing method of the single wafer 100, since the single wafer 100 is not disposed on the temporary carrier a, the step of removing the temporary carrier a is not required. In another example, if necessary, a single wafer 100 may be disposed on the temporary carrier a to improve the reliability of the fabrication, and in this example, the temporary carrier a needs to be removed. The specific application mode can be selected according to actual requirements.
Please refer to fig. 2, 3B, and 4, as shown in step S52. The redistribution structures 20 are formed on the first top surfaces 101 of the wafers 100. Each of the redistribution circuit structures 20 includes a plurality of dielectric layers 21 and a plurality of circuit layers 22. The redistribution circuit structure 20 includes a second top surface 211 and a second bottom surface 212 opposite to each other. The second bottom surface 212 of the redistribution routing structure 20 is disposed on the first top surface 101 of the wafer 100. The plurality of wiring layers 22 are respectively disposed in the corresponding dielectric layers 21. The plurality of circuit layers 22 are electrically connected to the circuit structures of the wafer 100, respectively. Also, a portion of the wiring layer 22 is exposed on the second top surface 211 of the redistribution wiring circuit structure 20. Further, an electrical connection layer 23 is provided on the second top surface 211 of the redistribution line structure 20. The electrical connection layer 23 is electrically connected to the circuit layer 22 of the redistribution circuit structure 20, which exposes the corresponding dielectric layer 21.
Wherein the second top surface 211 of the redistribution structure 20 is the top surface of the outermost dielectric layer 21. The second bottom surface 212 of the redistribution structure 20 is the bottom surface of the dielectric layer 21 contacting the wafer 100.
In one example, the electrical connection layer 23 includes a plurality of Solder balls (Solder balls) for providing better electrical connection effect when performing subsequent electrical connection.
Generally, the circuit structure on the wafer 100 has a small contact area and is not easy to connect, and the circuit layer 22 of the redistribution circuit structure 20 is used as an extension circuit, so that the expandability, accuracy and reliability of circuit connection can be improved.
After the completion of the arrangement of the redistribution routing structures 20, please refer to fig. 2 and 4. In step S53, a plurality of first cutting grooves 103 are formed on the plurality of wafers 100 and the corresponding redistribution structures 20, respectively. The plurality of first cutting trenches 103 are formed by extending the second top surface 211 of the redistribution line structure 20 to a depth towards the first bottom surface 102 of the wafer 100. In one example, the plurality of first cutting grooves 103 may be formed by a laser cutting method, a hub type cutting method, or the like.
After the plurality of first cutting grooves 103 are formed, since the plurality of first cutting grooves 103 extend only to a certain depth of the wafer 100, a plurality of the chips 10 and the corresponding redistribution circuit structures 20 that are not separated are formed on each wafer 100. Each of the chips 10 has a first top surface 101 identical to the corresponding wafer 100, a third bottom surface 11 (a passive surface of the chip 10) connected to the wafer 100, and a plurality of exposed outer side surfaces 12. Each chip 10 of the wafer 100 has a corresponding redistribution circuit structure 20, so that the circuit structure of each chip 10 is electrically connected to the corresponding redistribution circuit structure 20.
The redistribution circuit structures 20 are disposed on the first top surface 101 of the wafer 100 in a full-surface manner, and the chips 10 of the wafer 100 have corresponding circuit layers 22. The circuit layer 22 is not present on the areas other than the plurality of chips 10. That is, there is no wiring layer 22 corresponding to the region where the plurality of first cut trenches 103 are to be formed. After the first cutting trenches 103 are formed, the redistribution layer 20 on each chip 10 further includes a plurality of exposed outer side surfaces 213, i.e., outer side surfaces of the corresponding dielectric layer 21.
The outer side surface 213 of the redistribution line structure 20 corresponds to the outer side surface 12 of the connected chip 10. In one example, the chip 10 may be in a rectangular parallelepiped shape or a cubic shape. The redistribution line structure 20 provided on the chip 10 is also shaped like a rectangular parallelepiped or a cube. In one example, the outer side 12 of the chip 10 includes four sides. The redistribution line structure 20 provided on the chip 10 has four outer surfaces 213.
After the plurality of first cutting grooves 103 are formed, please refer to fig. 2, 4, and 5. In step S54, the first molding material layer 31 in the molding mold material structure 30 is formed on each wafer 100 and the corresponding redistribution structure 20 and in the corresponding first cutting trench 103, respectively. The first molding material layer 31 covers the outer side surfaces 12 of the chips 10 of the wafer 100, the outer side surfaces 213, the second top surfaces 211 and the electrical connection layers 23 of the redistribution structures 20, and fills the corresponding first cutting trenches 103. In an example, the first molding Compound layer 31 may be an Epoxy molding Compound (Epoxy molding Compound) or the like, but is not limited thereto.
Please refer to fig. 2, 5, 6, and 7, as shown in step S55. The temporary carrier plate a is removed, and processing is performed from the first bottom surface 102 of each wafer 100 to expose the third bottom surface 11 of the chip 10 of each wafer 100 and the first molding material layer 31 formed in the first cutting groove 103 on each wafer 100. A second molding material layer 32 in the molding material structure 30 is formed on the third bottom surface 11 of each of the chips 10 and the exposed first molding material layer 31. The first molding material layer 31 is connected with the second molding material layer 32 to form the molding material structure 30.
In an example, the processing performed on the first bottom surface 102 of the wafer 100 may be a polishing method. By the polishing method, a part of the substrate of the wafer 100 is removed, the chips 10 of each wafer 100 are temporarily formed into a single body, and the surface of the first molding material layer 31 provided in the plurality of first cutting grooves 103 corresponding to the third bottom surfaces 11 of the chips 10 is exposed. Since the plurality of chips 10 are fixed by the corresponding first molding material layer 31 and second molding material layer 32, they are not yet separated from each other.
In an example, the second molding Compound layer 32 of the molding Compound structure 30 may be an Epoxy molding Compound (Epoxy molding Compound), but is not limited thereto.
Please refer to fig. 2, 7, and 8, as shown in step S56. A plurality of second dicing grooves 104 are formed along the first molding material layer 31 and the corresponding second molding material layer 32 formed in the plurality of first dicing grooves 103 in each of the wafers 100 to separate the plurality of chips 10. In one example, the plurality of second cutting grooves 104 may be formed by a laser cutting method, a hub type cutting method, or the like. When the plurality of chips 10 are separated, the first molding material layer 31 and the second molding material layer 32 are also separated. So that each of the chips 10 is provided with a corresponding redistribution circuit structure 20, a corresponding first molding material layer 31, and a corresponding second molding material layer 32. In one example, a width of the second cutting groove 104 is smaller than a width of the first cutting groove 103.
In the above example, the first molding material layer 31 has an exposed fourth top surface 311 and a plurality of exposed outer side surfaces 312. The second molding material layer 32 has an exposed fourth bottom surface 321 and a plurality of exposed outer side surfaces 322.
Referring to fig. 2 and 9, in step S57, an emi shielding structure 40 is formed on the periphery of the first molding material layer 31 and the second molding material layer 32 on each of the chips 10. For simplicity, only one chip 10 is illustrated and described in the figures. Before the emi shielding structure 40 is disposed, the separated chip 10 shown in fig. 8 may be placed on a temporary tape (tape), and removed from the temporary tape after the emi shielding structure 40 is disposed, which is not shown.
The emi shielding structure 40 comprises a first emi shielding layer 41. The first emi shielding layer 41 is disposed on the outer surface 312 of the first molding material layer 31, the fourth bottom 321 of the second molding material layer 32, and the outer surface 322.
Wherein, the emi shielding structure 40 may be a metal material. In one example, the metal material includes, but is not limited to, copper, nickel, gold.
Referring to fig. 1, 2 and 9, after the electromagnetic interference shielding structure 40 is disposed, in step S58, the second top surface 211 and the electrical connection layer 23 of the redistribution structure 20 on each chip 10 are exposed from the first molding material layer 31.
In one example, the first molding material layer 31 and the corresponding portion of the first emi shielding layer 41 on the second top surface 211 of the redistribution structure 20 are removed by a dry etching method (plasma etching), etc. The second top surface 211 of the redistribution structure 20 and a portion of the electrical connection layer 23 are exposed from the first molding material layer 31.
As for the structure of the first embodiment, the redistribution line structure 20 is disposed on the first top surface 101 of the chip 10. The molding material structure 30 is disposed on the outer side surface 12 and the third bottom surface 11 of the chip 10, and is disposed on the outer side surface 213 of the redistribution circuit structure 20. That is, the first molding material layer 31 of the molding die structure 30 is disposed on the outer side surface 213 of the redistribution line structure 20 and on the outer side surface 12 of the chip 10. The second molding material layer 32 of the molding material structure 30 is disposed on the third bottom surface 11 of the chip 10. The first emi shielding layer 41 of the emi shielding structure 40 is disposed on the outer side 312 of the first molding material layer 31, and on the fourth bottom 321 and the outer side 322 of the second molding material layer 32.
Referring to fig. 10, a second embodiment of the package structure is substantially the same as the first embodiment. In the second embodiment, the second molding material layer 32 is removed, and a portion of the first emi shielding layer 41 disposed on the outer side 322 and the fourth bottom 321 of the second molding material layer 32 is removed to expose the third bottom 11 of the wafer 100, the first molding material layer 31 corresponds to the surface of the third bottom 11 of the wafer 100, and the first emi shielding layer 41 corresponds to the surface of the third bottom 11 of the wafer 100. This embodiment provides four-sided protection of the package structure.
Please refer to fig. 11 for a third embodiment of the package structure of the present invention. The third embodiment is substantially the same as the first embodiment described above. In the third embodiment, before the emi shielding structure 40 is disposed, a plurality of grooves 323 are further formed on the fourth bottom 321 of the second molding material layer 32. When the first emi shielding layer 41 of the emi shielding structure 40 is disposed, the first emi shielding layer 41 covers and fills the plurality of grooves 323 to form a plurality of heat dissipation structures. Since the first emi shielding layer 41 passes through the plurality of grooves 323 and is very close to the third bottom surface 11 of the chip 10, the heat energy of the chip 10 can be dissipated outwards through the first emi shielding layer 41.
Referring to fig. 12, a fourth embodiment of the package structure of the present invention is substantially the same as the above embodiments. In the fourth embodiment, before the emi shielding structure 40 is disposed, a plurality of openings 323A penetrating through the second molding material layer 32 are further formed on the fourth bottom surface 321 of the second molding material layer 32. When the first emi shielding layer 41 of the emi shielding structure 40 is disposed, the first emi shielding layer 41 covers and fills the openings 323A. The first emi shielding layer 41 is contacted with the third bottom surface 11 of the chip 10 through the openings 323A to form a plurality of heat dissipation structures. In this example, the first emi shielding layer 41 is not electrically connected to the chip 10. The first emi shielding layer 41 can dissipate heat of the chip 10 to the outside.
Please refer to fig. 13 for a fifth embodiment of the package structure of the present invention. The fifth embodiment is substantially the same as the above embodiments. In the fifth embodiment, in step S58, a portion of the first molding material layer 31 and a corresponding portion of the first emi shielding layer 41 are removed, the remaining portion of the first molding material layer 31 is covered on the second top surface 211 of the redistribution circuit structure 20, and the plurality of electrical connection layers 23 are partially exposed out of the first molding material layer 31. In addition, the first emi shielding layer 41 is flush with the first molding material layer 31 disposed on the second top surface 211 of the redistribution structure 20, so as to effectively provide protection against emi. The chip 10 and the redistribution trace structure 20 are surrounded by the molding compound structure 30 to provide six-sided protection of the structure.
In one example, the thickness of the electrical connection layer 23 exposing the first molding material layer 31 disposed on the second top surface 211 of the redistribution structure 20 is more than half of the height of the electrical connection layer 23. Thereby, both an effective protection and an effective connection can be provided.
Please refer to fig. 14 for a sixth embodiment of the package structure of the present invention. The sixth embodiment is substantially the same as the fifth embodiment. In the sixth embodiment, before the emi shielding structure 40 is disposed, a plurality of grooves 323 may be further formed on the fourth bottom 321 of the second molding material layer 32. When the first emi shielding layer 41 of the emi shielding structure 40 is disposed, the first emi shielding layer 41 covers and fills the plurality of grooves 323 to form a plurality of heat dissipation structures. Since the first emi shielding layer 41 passes through the plurality of grooves 323 and is very close to the third bottom surface 11 of the chip 10, the heat energy of the chip 10 can be dissipated outwards through the first emi shielding layer 41.
Please refer to fig. 15 for a seventh embodiment of the package structure of the present invention. The seventh embodiment is substantially the same as the fifth embodiment. In the seventh embodiment, before the emi shielding structure 40 is disposed, a plurality of openings 323A penetrating through the second molding material layer 32 may be further formed on the fourth bottom surface 321 of the second molding material layer 32. When the first emi shielding layer 41 of the emi shielding structure 40 is disposed, the first emi shielding layer 41 covers and fills the openings 323A. The first emi shielding layer 41 is contacted with the third bottom surface 11 of the chip 10 through the openings 323A to form a plurality of heat dissipation structures. In this example, the first emi shielding layer 41 is not electrically connected to the chip 10. The first emi shielding layer 41 can conduct heat from the chip 10 to the outside for heat dissipation.
Please refer to fig. 16 for an eighth embodiment of the package structure of the present invention. The eighth embodiment is substantially the same as the fifth embodiment. In the eighth embodiment, a second emi shielding layer 42 of the emi shielding structure 40 is further disposed on the first molding material layer 31 on the second top surface 211 of the redistribution structure 20 and the first emi shielding layer 41. The second emi shielding layer 42 is electrically connected to the first emi shielding layer 41. The second emi shielding layer 42 is spaced apart from the exposed electrical connection layers 23, i.e. the two are not electrically connected to avoid signal interference and short circuit. Wherein the second emi shielding layer 42 may be a metal material. In one example, the metal material includes, but is not limited to, copper, nickel, gold. The second emi shielding layer 42 is disposed to provide emi protection of the second top surface 211 of the redistribution circuit structure 20, so as to achieve six-sided emi protection.
Please refer to fig. 17 for a ninth embodiment of the package structure of the present invention. The ninth embodiment is substantially the same as the eighth embodiment. In the eighth embodiment, before the emi shielding structure 40 is disposed, a plurality of grooves 323 may be further formed on the fourth bottom 321 of the second molding material layer 32. When the first emi shielding layer 41 of the emi shielding structure 40 is disposed, the first emi shielding layer 41 covers and fills the plurality of grooves 323 to form a plurality of heat dissipation structures. Since the first emi shielding layer 41 passes through the plurality of grooves 323 and is very close to the third bottom surface 11 of the chip 10, the heat energy of the chip 10 can be dissipated outwards through the first emi shielding layer 41.
Please refer to fig. 18 for a tenth embodiment of the package structure of the present invention. The tenth embodiment is substantially the same as the eighth embodiment. In the tenth embodiment, before the emi shielding structure 40 is disposed, a plurality of openings 323A penetrating through the second molding material layer 32 may be further formed on the fourth bottom surface 321 of the second molding material layer 32. When the first emi shielding layer 41 of the emi shielding structure 40 is disposed, the first emi shielding layer 41 covers and fills the openings 323A. The first emi shielding layer 41 is contacted with the third bottom surface 11 of the chip 10 through the openings 323A to form a plurality of heat dissipation structures. In this example, the first emi shielding layer 41 is not electrically connected to the chip 10. The first emi shielding layer 41 can conduct heat from the chip 10 to the outside for heat dissipation.
According to the above, the production efficiency can be improved by disposing a plurality of wafers 100 on the temporary carrier a and fabricating the redistribution circuit structures 20 for all the wafers 100 at the same time. In addition, the molding material structure 30 provides multi-surface protection and reinforcement for the chip 10 and the redistribution circuit structure 20. And, through setting up in the periphery of the said shaping mould material structure 30 and correspond to the said chip 10 and the electromagnetic interference of the said rewiring circuit structure 20 and shelter from the structure 40, offer the multi-faceted electromagnetic interference protection to the structure. Thereby achieving the purposes of improving the structural strength, using reliability and stability.
In some embodiments, a corresponding heat dissipation structure is formed on the second molding material layer 32, so as to enhance the heat dissipation effect and further enhance the performance.
In some of the above embodiments, the first molding material layer 31 protects the outer side surface 12 of the chip 10, the outer side surface 213 of the redistribution routing structure 20, and the second molding material layer 32 protects the third bottom surface 11 of the chip 10, so as to achieve five-side protection of the structure. Moreover, the first emi shielding layer 41 is disposed on the outer side 312 of the first molding material layer 31, the fourth bottom 321 and the outer side 322 of the second molding material layer 32, so as to achieve five-sided emi protection.
In addition, in some embodiments, the first molding material layer 31 covering the second top surface 211 of the redistribution structure 20 is still remained, so as to provide protection for the redistribution structure 20, thereby improving the reliability of subsequent use in connection with a printed circuit board. For these embodiments, six-sided protection of the structure, i.e. top, bottom and four outer sides, can be achieved.
In addition, in some embodiments, the second emi shielding layer 42 is further disposed on the first molding material layer 31 remaining on the second top surface 211 of the redistribution structure 20, so as to further improve emi protection of the redistribution structure 20 or emi protection when the redistribution structure is connected to a corresponding pcb and operates subsequently. For these embodiments, six sides of protection against electromagnetic interference, namely the top side, the bottom side and the four outer sides, can be achieved.
The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.
Claims (24)
1. A package structure, comprising:
a chip;
a redistribution line structure disposed on the chip and forming an electrical connection;
the molding die material structure is arranged at the periphery of the chip and the redistribution circuit structure;
and the electromagnetic interference shielding structure is arranged at the periphery of the molding material structure.
2. The package structure of claim 1, wherein the molding compound structure comprises:
the first molding material layer is arranged on a plurality of outer side surfaces of the chip and a plurality of outer side surfaces of the redistribution circuit structure;
and the second molding material layer is arranged on the bottom surface of the chip and is connected with the first molding material layer.
3. The package structure of claim 2, wherein the EMI shielding structure comprises a first EMI shielding layer disposed on the outer sides of the first molding material layer, the outer sides of the second molding material layer, and the bottom surface.
4. The package structure according to claim 1, wherein the molding compound structure includes a first molding compound layer disposed on a plurality of outer sides of the chip and a plurality of outer sides of the redistribution routing structure; the electromagnetic interference shielding structure comprises a first electromagnetic interference shielding layer arranged on a plurality of outer side surfaces of the first molding material layer.
5. The package structure according to claim 3, wherein the bottom surface of the second molding material layer is further provided with a plurality of grooves, and the first EMI shielding layer fills the plurality of grooves.
6. The package structure according to claim 3, wherein a plurality of openings are further formed through the second molding material layer, and the first EMI shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.
7. The package structure of claim 1, wherein the molding compound structure comprises:
the first molding material layer is arranged on the plurality of outer side surfaces of the chip and the plurality of outer side surfaces and the top surface of the rewiring circuit structure, and the electric connection layer part arranged on the top surface of the rewiring circuit structure is exposed out of the first molding material layer;
and the second molding material layer is arranged on the bottom surface of the chip and is connected with the first molding material layer.
8. The package structure of claim 7, wherein the EMI shielding structure comprises a first EMI shielding layer disposed on the outer sides of the first molding material layer, the outer sides of the second molding material layer, and the bottom surface.
9. The package structure of claim 8, wherein a plurality of grooves are further formed on the second molding material layer, and the first EMI shielding layer fills the plurality of grooves.
10. The package structure according to claim 8, wherein a plurality of openings are further formed through the second molding material layer, and the first emi shielding layer fills the plurality of openings and is connected to the chip.
11. The package structure of claim 7, wherein the EMI shielding structure comprises:
the first electromagnetic interference shielding layer is arranged on the plurality of outer side surfaces of the first molding material layer, the plurality of outer side surfaces of the second molding material layer and the bottom surface;
and the second electromagnetic interference shielding layer is arranged on the first molding material layer on the top surface of the redistribution circuit structure and is separated from the exposed electric connection layer.
12. The package structure of claim 11, wherein a plurality of grooves are further formed on the second molding material layer, and the first emi shielding layer fills the plurality of grooves.
13. The package structure of claim 11, wherein a plurality of openings are further formed through the second molding material layer, and the first emi shielding layer fills the plurality of openings and is connected to the bottom surface of the chip.
14. A method of manufacturing a package structure, the method comprising:
providing more than one wafer;
forming a redistribution circuit structure on the top surface of the wafer;
forming a plurality of first cutting grooves on the wafer and the corresponding redistribution circuit structure so as to form a plurality of chips provided with the corresponding redistribution circuit structure;
forming a first molding material layer in a molding material structure on the wafer and the corresponding redistribution circuit structure and the corresponding first cutting groove;
processing from the bottom surface of the wafer to expose the bottom surfaces of the chips of the wafer and a first molding material layer formed in a first cutting groove of the wafer, and forming a second molding material layer in the molding material structure on the bottom surfaces of the chips of the wafer and the exposed first molding material layer;
forming a plurality of second cutting grooves along the first molding material layer formed in the plurality of first cutting grooves in the wafer and the corresponding second molding material layer to separate the plurality of chips;
forming an electromagnetic interference shielding structure on the periphery of the first molding material layer and the second molding material layer on the chip;
the redistribution circuit structure on each chip is exposed.
15. The method for manufacturing a package structure according to claim 14, wherein in the step of exposing the redistribution routing structures on the chips, the first molding material layer and a corresponding portion of the emi shielding structure on the top surface of the redistribution routing structures on the chips are removed, the top surface of the redistribution routing structures on the chips are exposed, and the electrical connection layers formed on the redistribution routing structures are exposed.
16. The method of manufacturing a package structure according to claim 15, wherein a plurality of grooves are formed on the second molding material layer before the step of forming the emi shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form the heat dissipation structure.
17. The method of manufacturing a package structure according to claim 15, wherein before the step of forming the emi shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips, a plurality of openings penetrating through the second molding material layer are formed on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected with the bottom surface of the chip.
18. The method for manufacturing the package structure according to claim 14, wherein in the step of exposing the redistribution structure on each of the chips, a portion of the first molding material layer and a corresponding portion of the emi shielding structure are removed, a remaining portion of the first molding material layer is covered on a top surface of the redistribution structure, and a portion of the electrical connection layer formed on the redistribution structure is exposed.
19. The method of manufacturing a package structure according to claim 18, wherein a plurality of grooves are formed on the second molding material layer before the step of providing an electromagnetic interference shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips; when the electromagnetic interference shielding structure is arranged, the electromagnetic interference shielding structure fills the plurality of grooves.
20. The method of manufacturing a package structure according to claim 18, wherein before the step of forming the emi shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips, a plurality of openings penetrating through the second molding material layer are formed on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected with the bottom surface of the chip.
21. The method for manufacturing a package structure according to claim 18, wherein in the step of forming the emi shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips, the first emi shielding layer of the emi shielding structure is formed on a plurality of outer sides of the first molding material layer on each of the chips, and a plurality of outer sides and a bottom of the second molding material layer on each of the chips; and forming a second electromagnetic interference shielding layer of the electromagnetic interference shielding structure on the first molding material layer of the redistribution circuit structure of each chip, wherein the second electromagnetic interference shielding layer is arranged at a distance from the exposed electric connection layer.
22. The method of manufacturing a package structure according to claim 21, wherein a plurality of grooves are formed on the second molding material layer before the step of forming the emi shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of grooves to form the heat dissipation structure.
23. The method of manufacturing a package structure according to claim 21, wherein before the step of forming the emi shielding structure on the first molding material layer and the periphery of the second molding material layer on each of the chips, a plurality of openings penetrating through the second molding material layer are formed on the second molding material layer; when the electromagnetic interference shielding structure is formed, the electromagnetic interference shielding structure fills the plurality of openings and is connected with the bottom surface of the chip.
24. The method for manufacturing a package structure according to claim 14, wherein when the wafer is plural;
arranging the wafer on a temporary bearing plate;
arranging a corresponding redistribution circuit structure on the top surface of the wafer and forming electrical connection;
forming the plurality of first cutting grooves on the wafer and the corresponding redistribution routing structure so as to form a plurality of chips provided with the corresponding redistribution routing structure;
arranging a first molding material layer in the molding material structure on the wafer and the corresponding redistribution circuit structure and in the corresponding first cutting groove;
removing the temporary bearing plate, and processing from the bottom surface of each wafer to expose the bottom surface of the chip of each wafer and the first molding material layer arranged in the first cutting groove of each wafer, and arranging the second molding material layer in the molding material structure on the bottom surface of the chip of each wafer and the exposed first molding material layer;
forming a plurality of second cutting grooves along the first molding material layer arranged in the plurality of first cutting grooves and the corresponding second molding material layer in each wafer so as to separate the plurality of chips;
arranging an electromagnetic interference shielding structure on the peripheries of the first molding material layer and the second molding material layer on each chip;
the redistribution circuit structure on each chip is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011047601.XA CN114334912A (en) | 2020-09-29 | 2020-09-29 | Package structure and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011047601.XA CN114334912A (en) | 2020-09-29 | 2020-09-29 | Package structure and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
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| CN114334912A true CN114334912A (en) | 2022-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011047601.XA Pending CN114334912A (en) | 2020-09-29 | 2020-09-29 | Package structure and method for manufacturing the same |
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| Country | Link |
|---|---|
| CN (1) | CN114334912A (en) |
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2020
- 2020-09-29 CN CN202011047601.XA patent/CN114334912A/en active Pending
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