CN114334904A - Semiconductor device and manufacturing method thereof, chip and electronic equipment - Google Patents

Abstract

The disclosure provides a semiconductor device, a manufacturing method thereof, a chip and an electronic device. The device comprises a semiconductor substrate, stacked metal layers, an air gap and the like. The stacked metal layer is arranged above the semiconductor substrate, and a groove is arranged in the stacked metal layer. The first spacer is disposed in the recess and along the side of the stacked metal layers, and the air gap is disposed in the recess. The chip includes the device of any embodiment of the present disclosure. The electronic device comprises the chip of any embodiment of the disclosure. The manufacturing method comprises the following steps: a stacked metal layer is formed above a semiconductor substrate, a groove is formed in the stacked metal layer, a first spacer and a second spacer are formed on the side wall of the groove, a sacrificial layer is formed between the adjacent second spacers, and the second spacers and the sacrificial layer are sequentially removed to form an air gap in the groove. The present disclosure can manufacture a large-sized air gap on the stacked metal layer, thereby greatly improving the problem of chip performance degradation caused by parasitic resistance and parasitic capacitance.

Description

Semiconductor device and manufacturing method thereof, chip and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor device technology, and more particularly, to a semiconductor device, a method of manufacturing the same, a chip, and an electronic apparatus.

Background

At present, in order to improve the characteristics of the chip, the parasitic resistance and the parasitic capacitance are often required to be reduced. Common technical means for reducing parasitic resistance and parasitic capacitance include: copper is used instead of aluminum as a constituent material of the conductive line to reduce the delay through copper interconnection, or an oxide of a low-k material may be employed as an insulating material or the like. However, the reduction of parasitic resistance and parasitic capacitance is still limited by these measures, and it is difficult to achieve the practical application requirements. Accordingly, it has been proposed to use an Air Gap (Air Gap) as the insulating film. However, due to the limitations of conventional techniques, it is very difficult to fabricate air gaps and semiconductor device structures that meet the design requirements. For example, the sizes of different metal layers are often different, and the spacings between the metal layers in the same layer are also generally different, it is difficult to form air gaps with the same shape in different areas in the conventional technology, and the size of the manufactured air gap is often smaller, so that the insulation performance of the air gap is limited.

Disclosure of Invention

In order to solve the problems that the conventional technology is small in air gap size and difficult to make air gaps with the same shape in different areas, the disclosure innovatively provides a semiconductor device, a manufacturing method thereof, a chip and electronic equipment so as to achieve the purpose of manufacturing the air gaps meeting the requirements.

To achieve the above technical object, the present disclosure provides a semiconductor device. The semiconductor device may include, but is not limited to, a semiconductor substrate, stacked metal layers, an air gap, a first spacer, an upper stop layer, and the like. At least one stacked metal layer is arranged above the semiconductor substrate, and a groove is arranged in the stacked metal layer. The first spacer is disposed in the recess and along a side of the stacked metal layers. The upper stop layer is deposited on the stacked metal layer, and the first spacer, the stacked metal layer and the upper stop layer jointly enclose the air gap.

To achieve the above technical object, the present disclosure also provides a chip including the semiconductor device in any embodiment of the present disclosure.

To achieve the above technical object, the present disclosure provides an electronic device including a chip in any one of the embodiments of the present disclosure. Electronic devices include, but are not limited to, smart phones, computers, tablets, wearable smart devices, artificial smart devices, mobile power sources, and the like.

To achieve the above technical objects, the present disclosure provides a method of manufacturing a semiconductor device, which may include, but is not limited to, the following steps. Forming at least one stacked metal layer above the semiconductor substrate, forming a groove in the stacked metal layer by adopting an etching mode, sequentially forming a first spacer and a second spacer on the side wall of the groove, forming a sacrificial layer between the adjacent second spacers, sequentially removing the second spacers and the sacrificial layer, and depositing an upper stop layer on the stacked metal layer so as to enable the first spacer, the stacked metal layer and the upper stop layer to jointly enclose an air gap.

The beneficial effect of this disclosure does: compared with the prior art, the method can manufacture the large-size air gap on the stacked metal layer to be used as the insulating film with good insulation performance, so that the problem of poor performance of chips such as dynamic random access memories and the like caused by parasitic resistance and parasitic capacitance is greatly improved.

The present disclosure also enables the provision of shaped and sized air gaps for semiconductor devices, i.e., air gaps of the same shape and size can be made in different regions on the same or different layers of stacked metal layers to meet the actual design requirements of the semiconductor device.

The method can manufacture the required air gap structure on the premise of not investing in complex processes, can meet the actual application requirements in various scenes, and has the outstanding advantages of low processing cost of semiconductor devices, short process period, suitability for large-area popularization and application and the like.

Drawings

Fig. 1 shows a schematic longitudinal cross-sectional structure of a semiconductor device after forming a groove in stacked metal layers.

Fig. 2 shows a longitudinal cross-sectional structural view of the semiconductor device after forming the first spacer on the inner sidewall of the groove.

Fig. 3 is a schematic diagram showing a longitudinal cross-sectional structure of the semiconductor device after forming a second spacer on an outer sidewall of the first spacer and a portion of an inner sidewall of the groove.

Fig. 4 shows a longitudinal cross-sectional structural diagram of the semiconductor device after forming a sacrificial layer between adjacent second spacers and etching back.

Fig. 5 shows a schematic diagram of a longitudinal cross-sectional structure of a semiconductor device after a protective layer is deposited and chemical mechanical planarization is performed.

Fig. 6 shows a schematic diagram of a longitudinal cross-sectional structure of the semiconductor device after removing the second spacers.

Fig. 7 shows a longitudinal cross-sectional structural diagram of the semiconductor device after the sacrificial layer is removed.

Fig. 8 shows a schematic longitudinal cross-sectional structure of the semiconductor device after deposition of the upper stop layer.

In the figure, the position of the upper end of the main shaft,

100. a semiconductor substrate.

200. And a lower stop layer.

300. Stacking metal layers; 301. and (4) a groove.

400. A first spacer.

500. A second spacer.

600. A sacrificial layer.

700. And a protective layer.

800. An air gap.

900. And (4) an upper stop layer.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

In order to manufacture an air gap meeting the design requirements of a product, the present disclosure provides a method for manufacturing a semiconductor device, so as to provide an air gap having a large size and meet the requirements of having the same shape of air gaps in different regions, thereby utilizing the air gap as a better-performing insulating film and improving the performance of a chip.

In particular, to solve at least one problem of the prior art, the present disclosure provides a method for manufacturing a semiconductor device that may include, but is not limited to, the following steps.

As shown in fig. 1, a semiconductor substrate 100 is provided. A lower stop layer 200 and a Stack Metal layer (Stack Metal)300 may be sequentially formed over the semiconductor substrate 100, wherein, in some embodiments of the present disclosure, the lower stop layer 200 is disposed on the semiconductor substrate 100, and the Stack Metal layer 300 may be disposed on the lower stop layer 200. More specifically, the present disclosure forms at least one stacked metal layer 300 above the semiconductor substrate 100, and forms a groove 301 on the stacked metal layer 300 by etching; the stack Metal layer 300 includes each stack Metal, and may have Inter-Metal Dielectric (IMD) layers between adjacent stack metals, and each recess 301 may be formed by etching away the IMD layers between the stack metals in the present disclosure; the process of forming the recess on the stack metal layer 300 by etching away the intermetal dielectric layer is a mature process, and is not described in detail in this embodiment. As shown in fig. 1, the bottom wall of the groove 301 is the upper surface of the lower stop layer 200, and the sidewall of the groove 301 is the stacked metal side. In addition, the lower stopper layer 200 serves to prevent metal ions in the stacked metal layer 300 from diffusing into other layers to improve the reliability of the semiconductor device. In this embodiment, the material of the lower stop layer 200 may be silicon nitride. It should be understood that although the stacked metal layer 300 is shown as one layer in the figures, the present disclosure provides a solution that can be applied to a multi-layer stacked metal layer structure with two or more layers.

As shown in fig. 2, first spacers 400 are formed on sidewalls of the recess 301. The first spacers 400 of the present embodiment are formed beside the stacked metal layer 300, and the height of the first spacers 400 is smaller than the height of the stacked metal layer 300. In this embodiment, the first spacer 400 having a certain thickness and shape is formed along the sidewall of the stacked metal layer 300 by a sidewall process, and the specific shape and thickness of the first spacer 400 may be determined according to the shape and thickness of the air gap 800 to be formed; it can be seen that in the case of the shape and size determination of the recess 301, the specific shape and thickness of the first spacer 400 plays a very critical role in determining the shape and size of the air gap, and the present embodiment can adjust the size and shape of each air gap 800 by adjusting the size and shape of the first spacer 400. The process of the sidewall manufacturing process is a mature process, and is not further described in this embodiment. The material of the first spacers 400 in this embodiment may be, for example, silicon nitride.

As shown in fig. 3, a second spacer 500 having a certain thickness and shape is formed on the outer sidewall of the first spacer 400 and the sidewall of the recess 301, and the second spacer 500 is formed by a sidewall process in this embodiment. The second spacers 500 are used to occupy a space to be filled with a part of the air gap, and the second spacers 500 need to be removed in a subsequent process. The second spacers 500 in this embodiment may be made of oxide, such as silicon oxide. The specific process of the sidewall manufacturing process is a mature process, which will not be described in detail in this embodiment. In the present embodiment, the first spacer 400 and the second spacer 500 are sequentially formed on the sidewall of the stacked metal layer 300 by a sidewall spacer process. As shown in fig. 3, the height of the second spacers 500 in some embodiments of the present disclosure is greater than the height of the first spacers 400.

As shown in fig. 4, a sacrificial layer 600 is formed between the adjacent second spacers 500. The sacrificial layer 600 also occupies a portion of the air gap to be filled, and the sacrificial layer 600 is used for being removed in a subsequent process. The sacrificial layer in this embodiment may be, for example, a Spin on hard mask (SOH). More specifically, the process of forming the sacrificial layer 600 between the adjacent second spacers 500 includes: the sacrificial layer 600 is coated, and then the sacrificial layer 600 is etched back, so that the height of the sacrificial layer 600 is less than the height of the second spacers 500 and greater than or equal to the height of the first spacers 400.

As shown in fig. 5, the present embodiment may deposit a protective layer 700. Since the height of the sacrificial layer 600 is less than that of the second spacers 500, the second spacers 500 may be removed in a next process by exposing the second spacers 500 after performing a Chemical-Mechanical Planarization (CMP) process on the protective layer 700. The material of the protection layer 700 in this embodiment may be, for example, silicon nitride.

As shown in fig. 6, the second spacers 500 are removed to form a portion of the air gap. In this embodiment, the second spacers 500 are removed by etching, for example, the second spacers 500 between the first spacers 400 and the sacrificial layer 600 may be removed by wet etching or dry etching.

As shown in fig. 7, the sacrificial layer 600 is removed to form air gaps 800 within the grooves 301. Specifically, the sacrificial layer 600 may be removed by Ashing (Ashing), and etching gas (eachgas) may enter along the space formed after the second spacers 500 are removed, and after the Ashing process is completed, an air gap 800 may be formed between adjacent stacked metals, and the air gap 800 may be composed of the space occupied by the original second spacers 500 and the space occupied by the original sacrificial layer 600, and it is apparent that this embodiment may provide an air gap 800 having a very large size, which may be filled in almost the entire recess 301 except the space occupied by the first spacers 400. Therefore, the present embodiment can form the large-sized air gap 800 with a set shape and thickness, and further can form the semiconductor device structure with the large air gap in some embodiments of the present disclosure, so as to meet the design requirements of the semiconductor device in different application scenarios.

As shown in fig. 8, an upper stop layer 900 is deposited. The present disclosure utilizes the first spacer 400, the stacked metal layer 300, and the upper stop layer 900 to collectively enclose the air gap 800, and the shape of the air gap 800 may vary according to the variation of the shape of the first spacer 400. It can be seen that the air gap 800 manufactured in the present disclosure can be used as an insulating film with better insulating performance, so that the problems of performance degradation of chips such as dynamic random access memory and the like caused by parasitic capacitance and parasitic resistance can be effectively solved, and the problems that the size of the air gap manufactured by the conventional technology is often smaller and the air gap with the same shape is difficult to manufacture in different areas are effectively solved. In addition, the upper stop layer 900 may be used to provide an etch stop for other device layers above, and the upper stop layer 900 may be made of silicon nitride, for example.

As shown in fig. 7 and 8, one or more embodiments of the present disclosure can also provide a semiconductor device based on the same inventive concept as the method of manufacturing the semiconductor device. A corresponding semiconductor device may be processed by one or more embodiments of a method of manufacturing a semiconductor device, which may include, but is not limited to, the semiconductor substrate 100, the lower stop layer 200, the stacked metal layer 300, the first spacer 400, the protection layer 700, the air gap 800, the upper stop layer 900, and so on.

The semiconductor base 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate, so that formation of a plurality of memory cells on the semiconductor base 100 may be realized. A lower stopper layer 200, a stacked metal layer 300, a first spacer 400, a protective layer 700, an air gap 800, and the like are disposed on the semiconductor substrate 100.

The lower stop layer 200 is disposed on the upper surface of the semiconductor substrate 100, the material of the lower stop layer 200 may include, but is not limited to, silicon nitride, silicon oxynitride, and/or silicon carbon nitride (SiCN), and the lower stop layer 200 may be, for example, silicon nitride.

The stacked metal layer 300 is at least one layer and is disposed above the semiconductor substrate 100. The stacked metal layer 300 may be used to form a portion of a conductive line of a semiconductor device such as a dram, and may be made of copper and/or aluminum. As shown in fig. 1, a groove 301 is disposed on the stacked metal layer 300.

The first spacers 400 are disposed in the recess 301 and also along the sides of the stacked metal layers 300. With the recess 301 sized, the larger the size of the first spacer 400, the smaller the size of the air gap 800, and the smaller the size of the first spacer 400, the larger the air gap 800. The thickness and size of the air gap 800 in this embodiment are directly affected by the first spacer 400, which also illustrates that the size and shape of the air gap 800 can be adjusted as desired, and that a large size air gap 800 can be provided. In the case that the spacing (which may be understood as the width of the recess 301) between the stacked metals at different positions is different, one or more embodiments of the present disclosure may still make the air gaps at different positions have almost the same size and shape by adjusting the size of the first spacer 400; for example, making the first spacer 400 larger when the width of the recess 301 is larger and smaller when the width of the recess 301 is smaller, eventually resulting in all air gaps having a uniform shape and size. In addition, the material of the first spacer 400 in this embodiment may be, for example, silicon nitride.

The protection layer 700 is disposed on the air gap 800, and is formed on the stacked metal layer 300, the second spacer 500 and the sacrificial layer 600 by deposition in the process of forming the air gap 800, and the protection layer 700 on the sacrificial layer 600 is remained by etching back. The material of the protection layer 700 may be silicon nitride.

The air gap 800 is disposed in the groove, and more specifically, the air gap 800 in the present embodiment is filled in the groove 301. As shown in fig. 8, the outer side of the first spacer 400 and the exposed side of the stacked metal layer 300 within the recess 301 may be circumferentially surrounded by an air gap 800.

The air gap 800 in this embodiment may be disposed between the adjacent first spacers 400 and the adjacent upper stacked metal, so that the air gap 800 fills all the remaining space in the recess 301. The inside of the air gap 800 in this embodiment may be filled with a gaseous medium, wherein the dielectric constant of the gaseous medium is lower than that of silicon oxide. The dielectric constant of the gaseous medium of some embodiments of the present disclosure may be less than 2.8, for example the dielectric constant of the gaseous medium may be close to 1. The gaseous medium may be, for example, air with a better insulation effect, and of course, the air gap 800 in one or more embodiments of the present disclosure may also contain two or more other media. It can be seen that the present disclosure can dispose a large-sized and shape-selectable air gap 800 beside the stacked metal layer 300 as an insulating film, so as to significantly improve the performance of the semiconductor device and effectively reduce the problems of parasitic capacitance and parasitic resistance of the chips such as the dynamic random access memory.

As shown in fig. 8, an upper stop layer 900 is disposed on the stacked metal layer 300. The upper stop layer 900 of the present embodiment is deposited on the stack metal layer 300. The first spacer 400, the stacked metal layer 300, and the upper stop layer 900 together form an air gap 800. The material of the upper stop layer 900 may include, but is not limited to, silicon nitride, silicon oxynitride and/or silicon carbon nitride (SiCN), and the material of the upper stop layer 900 may be the same as the material of the protection layer 700, such as silicon nitride.

One or more embodiments of the present disclosure may provide a chip having a large-sized air gap, which may include the semiconductor device in any of the embodiments of the present disclosure.

The present disclosure can also provide an electronic device including the chip in any of the embodiments of the present disclosure. The electronic device may include, but is not limited to, a smart phone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:

a semiconductor substrate;

the semiconductor device comprises a semiconductor substrate, at least one stacked metal layer and a plurality of grooves, wherein the stacked metal layer is arranged above the semiconductor substrate;

a first spacer disposed in the recess and along a side of the stacked metal layers;

an upper stop layer deposited on the stacked metal layer; wherein the first spacer, the stacked metal layers, and the upper stop layer collectively enclose the air gap.

2. The semiconductor device according to claim 1,

the air gap is arranged between the adjacent first spacers.

3. The semiconductor device according to claim 2,

the air gap is arranged between the adjacent stacked metals.

4. The semiconductor device according to any one of claims 1 to 3,

the air gap is filled with gaseous medium; wherein the dielectric constant of the gaseous medium is lower than the dielectric constant of silicon oxide.

5. A chip comprising the semiconductor device according to any one of claims 1 to 4.

6. An electronic device comprising the chip of claim 5.

7. The electronic device of claim 6, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

8. A method of manufacturing a semiconductor device, comprising:

forming at least one stacked metal layer above the semiconductor substrate;

forming a groove in the stacked metal layers;

sequentially forming a first spacer and a second spacer on the side wall of the groove;

forming a sacrificial layer between adjacent second spacers;

sequentially removing the second spacers and the sacrificial layer;

and depositing an upper stop layer on the stacked metal layer, so that the first spacer, the stacked metal layer and the upper stop layer jointly enclose the air gap.

9. The method according to claim 8, wherein the step of sequentially removing the second spacer and the sacrificial layer comprises:

depositing a protective layer;

performing chemical mechanical planarization treatment on the protective layer to expose the second spacers;

etching the second spacer, and removing the second spacer by adopting a dry etching or wet etching mode;

and removing the sacrificial layer by adopting an ashing treatment to form an air gap between adjacent stacked metals.

10. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein a height of the second spacer is larger than a height of the first spacer;

the process of forming a sacrificial layer between adjacent second spacers includes:

coating a sacrificial layer;

and carrying out back etching treatment on the sacrificial layer so that the height of the sacrificial layer is smaller than that of the second spacer and is larger than or equal to that of the first spacer.

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