CN114141749A

CN114141749A - Semiconductor device, method of manufacturing the same, memory, and electronic apparatus

Info

Publication number: CN114141749A
Application number: CN202010917314.3A
Authority: CN
Inventors: 裴俊值; 高建峰; 刘卫兵; 李俊杰; 卢一泓
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2020-09-03
Filing date: 2020-09-03
Publication date: 2022-03-04

Abstract

The present disclosure provides a semiconductor device, a method of manufacturing the same, a memory, and an electronic apparatus. The device comprises a stacked metal layer, an air gap, a first spacer and the like, wherein the air gap is arranged along the side surface of the stacked metal layer so as to surround the stacked metal layer; and the first spacer is disposed along a side of the air gap to surround the air gap. The dynamic random access memory includes the semiconductor device of the present disclosure. The electronic device comprises the dynamic random access memory of the present disclosure. The manufacturing method comprises the following steps: forming a groove on the stacked metal layer in an etching mode, and sequentially forming a second spacer and a first spacer on the side wall of the groove, wherein the second spacer is positioned between the stacked metal layer and the first spacer; the second spacers are removed to form an air gap between the stacked metal layers and the first spacers. According to the technical scheme, the air gap can be processed beside the stacked metal layer, so that the problem of poor performance of chips such as a memory and the like caused by parasitic resistance and parasitic capacitance is effectively solved.

Description

Semiconductor device, method of manufacturing the same, memory, and electronic apparatus

Technical Field

The present disclosure relates to the field of semiconductor device technology, and more particularly, to a semiconductor device, a method of manufacturing the same, a memory, and an electronic apparatus.

Background

In order to improve the characteristics of a Dynamic Random Access Memory (DRAM), it is often necessary to reduce parasitic resistance and parasitic capacitance. The technical means adopted at present comprise: copper is used instead of aluminum as a constituent material of the conductive line so as to reduce the delay through copper interconnection, or an oxide of a low-k material may be used as an insulating material, or the like. However, the existing measures still have limited reduction of parasitic resistance and parasitic capacitance, and the practical application requirements are difficult to achieve. Accordingly, it has been proposed to use an Air Gap (Air Gap) as the insulating film. However, due to the limitations of conventional techniques, it is very difficult to fabricate air gaps and semiconductor device structures that meet the design requirements. For example, the sizes of the stacked metal layers at different positions are often different, and it is difficult to make air gaps with the same shape at different positions by the conventional technology.

Disclosure of Invention

In order to solve the problems that an air gap and a semiconductor device structure meeting design requirements are difficult to manufacture and practical application requirements are difficult to achieve in the conventional technology, the disclosure innovatively provides a semiconductor device and a manufacturing method thereof, a memory and electronic equipment.

To achieve the above technical object, the present disclosure provides a semiconductor device. The semiconductor device includes, but is not limited to, a semiconductor substrate, at least one stacked metal layer, an air gap, and a first spacer. The stacked metal layer is disposed above the semiconductor substrate. The air gap is disposed along a side of the stacked metal layers to surround the stacked metal layers. The first spacer is disposed along a side of the air gap to surround the air gap. Wherein an air gap is between the stacked metal layers and the first spacer.

To achieve the above technical object, the present disclosure also provides a dynamic random access memory including the semiconductor device in any one of the embodiments of the present disclosure.

To achieve the above technical object, the present disclosure can also provide an electronic device including the dynamic random access memory in any embodiment of the present disclosure.

To achieve the above technical object, the present disclosure provides a method of manufacturing a semiconductor device. The method includes, but is not limited to, the steps of: sequentially forming an intermetallic dielectric layer and a stacked metal layer above the semiconductor substrate; forming a groove on the stacked metal layer by adopting an etching mode, and exposing the intermetallic dielectric layer; sequentially forming a second spacer and a first spacer on the side wall of the groove, wherein the second spacer is positioned between the stacked metal layer and the first spacer; the second spacers are removed to form an air gap between the stacked metal layers and the first spacers.

The beneficial effect of this disclosure does: compared with the prior art, the technical scheme provided by the disclosure can process the air gap with a certain shape and thickness beside the stacked metal layer, so as to effectively solve the problem of poor performance of chips such as a dynamic random access memory and the like caused by parasitic resistance and parasitic capacitance.

The method can manufacture the required air gap structure on the premise of not investing in complex processes, can meet the actual application requirements in various scenes, and has the outstanding advantages of low processing cost of semiconductor devices, short process period, suitability for large-area popularization and application and the like.

Drawings

Fig. 1 shows a schematic longitudinal cross-sectional structure of a semiconductor device after a groove is etched on a current stacked metal layer.

Fig. 2 is a schematic diagram showing a longitudinal cross-sectional structure of the semiconductor device after forming a second spacer on the inner sidewall of the groove.

Fig. 3 shows a schematic longitudinal cross-sectional structure of the semiconductor device after forming the first spacers on the sidewalls of the second spacers.

Fig. 4 shows a schematic longitudinal cross-sectional structure of the semiconductor device after the intermetallic dielectric layer is deposited again.

Fig. 5 shows a schematic diagram of a longitudinal cross-sectional structure of the semiconductor device after etching the intermetal dielectric layer and removing the second spacers.

Fig. 6 shows a schematic diagram of a longitudinal cross-sectional structure of the semiconductor device after an upper stop layer is deposited over the entire device layer in fig. 5.

In the figure, the position of the upper end of the main shaft,

100. a semiconductor substrate.

200. And stacking the metal layers.

300. An air gap; 301. a second spacer.

400. A first spacer.

500. An inter-metal dielectric layer; 5000. and (4) a groove.

600. A lower barrier layer; 601. and (4) an upper barrier layer.

700. A lower stop layer; 701. and (4) an upper stop layer.

800. And an electrode.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

One or more embodiments of the present disclosure may provide a method for manufacturing a semiconductor device, which can manufacture an air gap structure having a certain shape and thickness and meeting design requirements beside a stacked metal layer, so as to improve chip performance by using the air gap as an insulating film. The method includes, but is not limited to, the following steps.

As shown in fig. 1, a semiconductor substrate 100 is provided. A lower stopper layer 700, an Inter-Metal Dielectric (IMD) 500, an electrode 800, a lower barrier layer 600, a Stack Metal (Stack Metal)200, an upper barrier layer 601, etc., may be sequentially formed on the semiconductor substrate 100, as described in detail below. In some embodiments of the present disclosure, a lower stop layer 700 is first deposited over the semiconductor substrate 100, and an inter-metal dielectric layer 500 is deposited on the lower stop layer 700. An electrode 800 is then formed on the inter-metal dielectric layer 500, and the electrode 800 may pass through the inter-metal dielectric layer 500 and the lower stop layer 700 in a longitudinal direction. Some embodiments of the present disclosure may form the electrode 800 by photolithography or etching, and metal plating or sputtering, and the forming process is a mature process, which is not described in detail in this disclosure. The lower barrier layer 600, the stacked metal layer 200 and the upper barrier layer 601 are sequentially formed, for example, the stacked metal layer 200 may be formed by sputtering, and the stacked metal layer 200 may be electrically connected to the electrode 800 and may be used as a conductive line of a semiconductor device. Both the lower barrier layer 600 and the upper barrier layer 601 serve to prevent diffusion of metal into other device layers (e.g., the inter-metal dielectric layer 500), improving the reliability of the operation of the semiconductor device. The process of forming the stacked metal layer 200 may include a Chemical Mechanical Polishing (CMP) step to make the top surface of the stacked metal layer flush with the top surfaces of other device layers in the same layer. Through the above steps, the present disclosure can achieve the formation of the inter-metal dielectric layer 500 and the stacked metal layer 200 sequentially above the semiconductor substrate 100. Next, a groove 5000 is formed on the stacked metal layer 200 by etching, and the inter-metal dielectric layer 500 below can be exposed. The recess 5000 in the present embodiment may have a certain depth in the inter-metal dielectric layer 500.

As shown in fig. 2, a second spacer 301 can be formed on the inner sidewall of the recess 5000, and the thickness and shape of the second spacer 301 can be set appropriately according to the design requirement of the semiconductor device. Wherein the second spacers 301 are used to occupy the space that the subsequent air gap 300 needs to occupy, the current second spacers 301 play a critical role in determining the shape and thickness of the air gap 300. In some embodiments of the present disclosure, the second spacers 301 may be formed along the sidewalls of the recess 5000 by a sidewall process. Fig. 2 shows a schematic longitudinal cross-section of a semiconductor device, in which the second spacers 301 may form a closed pattern in plan view, but may also be an open pattern. The detailed process of the sidewall process will not be described in detail in this embodiment. The second spacers 301 need to be removed in a subsequent process, and thus, the second spacers 301 in some embodiments of the present disclosure may be, for example, an oxide, such as silicon oxide, or the like.

As shown in fig. 3, the first spacers 400 may be formed after the second spacers 301 are formed. For example, the first spacer 400 may be formed by a sidewall process along the inner sidewall of the second spacer 301, and the specific shape and thickness of the first spacer 400 according to some embodiments of the present disclosure may be set as appropriate according to the actual situation. The present disclosure enables the second spacer 301 and the first spacer 400 to be sequentially formed on the sidewall of the intermetallic recess 5000, and the second spacer 301 is between the stacked metal layer 200 and the first spacer 400. The detailed process of the sidewall process is not repeated in this embodiment.

As shown in fig. 4, an intermetal dielectric layer 500 is again deposited. In some embodiments of the present disclosure, after the second spacers 301 and the first spacers 400 are sequentially formed, the following steps are further included. One or more intermetal dielectric layers 500 are deposited, and then the deposited intermetal dielectric layers 500 are subjected to a chemical mechanical polishing process to make the polished intermetal dielectric layers 500 level with the upper barrier layer 601.

As shown in fig. 5, the re-deposited inter-metal dielectric layer 500 is etched to expose the second spacers 301 to be removed. The second spacers 301 may then be removed by dry etching, wet etching, or the like, so as to form air gaps 300 with a set shape and thickness between the stacked metal layer 200 and the first spacers 400, thereby forming the semiconductor device structure in some embodiments of the present disclosure. The semiconductor device provided by the present disclosure includes: an insulating film formed of an air gap 300 and disposed beside the stacked metal layer 200. Therefore, the technical scheme provided by the present disclosure can conveniently manufacture the air gap 300 with a certain thickness and shape by disposing and removing the second spacer 301, so as to meet the design requirements of the semiconductor device in different application scenarios. The present disclosure can use the processed air gap 300 as an insulating film, so as to effectively improve the problems of the performance degradation of the dram due to the parasitic capacitance and the parasitic resistance. It should be understood that although only one stacked metal layer 200 is shown in the drawings, the disclosed solution can obviously be used on a multi-stacked metal layer 200 structure of two layers and more than two layers.

As shown in fig. 6, after forming the air gap 300 of the present disclosure to facilitate the performance of subsequent semiconductor device processing (e.g., providing etch stop locations for overlying device layers), some embodiments of the present disclosure further include the step of depositing one or more upper stop layers 701 over the inter-metal dielectric layer 500. Specifically including depositing the upper stop layer 701 over the entire device layer in fig. 5, the semiconductor device in other embodiments of the present disclosure may be formed such that the fabrication method provided by the present disclosure may be used as a sub-process of a chip processing flow. The material of the upper stop layer 701 may include, but is not limited to, silicon nitride.

As shown in fig. 5 and 6, one or more embodiments of the present disclosure can also provide a semiconductor device based on the same inventive concept as the method of manufacturing the semiconductor device. A corresponding semiconductor device product may be fabricated by one or more embodiments of the fabrication method. The semiconductor device includes, but is not limited to, a semiconductor substrate 100, stacked metal layers 200, air gaps 300, first spacers 400, inter-metal dielectric layers 500, an upper barrier layer 601, a lower barrier layer 600, an upper stop layer 701, a lower stop layer 700, electrodes 800, and the like.

The semiconductor base 100 is, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate, and it is possible to form a plurality of memory cells on the semiconductor base 100. A lower stopper layer 700, an inter-metal dielectric layer 500, a lower barrier layer 600, a stack metal layer 200, an upper barrier layer 601, and the like are disposed on the semiconductor substrate 100.

The stacked metal layer 200 is at least one layer and can be used to form a portion of a conductive line of a device such as a dynamic random access memory. At least one stacked metal layer 200 of some embodiments of the present disclosure may be disposed over the semiconductor substrate 100. The material of each stacked metal layer 200 may be aluminum and/or copper.

As shown in fig. 5 and 6, the air gap 300 is disposed along the side of the stacked metal layers 200 so that the stacked metal layers 200 may be circumferentially surrounded by the air gap 300. The air gap 300 of some embodiments of the present disclosure can be understood to be a cavity without a solid phase material, the interior of which can contain a gaseous medium. Wherein the dielectric constant of the gaseous medium can be lower than the dielectric constant of silicon oxide. Some embodiments of the present disclosure may have a dielectric constant of less than 2.8 for gaseous media, for example the dielectric constant of gaseous media may be close to 1. The gaseous medium may be, for example, air with a better insulation effect, and of course, the air gap 300 in some embodiments of the present disclosure may also contain two or more gaseous media. The air gap 300 in the embodiment of the present disclosure may be disposed on the side of the stacked metal layer 200, so as to achieve the purpose of disposing an insulating film with a smaller dielectric constant beside the stacked metal layer 200, thereby significantly improving the performance of the semiconductor device and solving the problems of parasitic capacitance and parasitic resistance in the conventional technology.

As shown in fig. 5 and 6, the first spacer 400 is disposed along the side of the air gap 300, and the first spacer 400 circumferentially surrounds the air gap 300. The air gap 300 is between the stacked metal layers 200 and the first spacer 400. The shape and thickness of the first spacer 400 are set according to actual circumstances.

The upper barrier layer 601 is formed on the upper surface of the stack metal layer 200. In the longitudinal cross-sectional direction, the upper barrier layer 601, the lower barrier layer 600 and the surrounding air gap 300 may completely surround the stacked metal layers 200 of each portion. The material of the upper barrier layer 601 may be at least one of titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). The lower barrier layer 600 is formed on the lower surface of the stacked metal layer 200, and the material of the lower barrier layer 600 may be at least one of titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). The lower barrier layer 600 and the upper barrier layer 601 are used to prevent diffusion of metal in the stacked metal layer 200 to other layers, so as to improve the reliability of the operation of the semiconductor device.

The inter-metal dielectric layer 500 is disposed above the semiconductor substrate 100 and distributed below the lower barrier layer 600. In some embodiments of the present disclosure, the intermetal dielectric layer 500 is further filled in the recess 5000 surrounded by the first spacers 400, and thus may be distributed between the lower stop layer 700 and the upper stop layer 701. The first spacers 400 and the air gaps 300 in some embodiments of the present disclosure each extend down into the inter-metal dielectric layer 500.

The lower stop layer 700 is disposed above the semiconductor substrate 100 between the inter-metal dielectric layer 500 and the semiconductor substrate 100. The material of the lower stop layer 700 includes, but is not limited to, silicon nitride, silicon oxynitride, and/or silicon carbon nitride (SiCN). An upper stop layer 701 is deposited on the upper surface of the upper barrier layer 601. The material of the upper stop layer 701 may also include, but is not limited to, silicon nitride, silicon oxynitride, and/or silicon carbon nitride (SiCN).

The electrode 800 penetrates the lower stop layer 700 and the inter-metal dielectric layer 500 in a longitudinal direction, and the electrode 800 is electrically connected to the stacked metal layer 200 (not shown). Both the electrode 800 and the stacked metal layer 200 can be used to form a conductive line, wherein the material of the electrode 800 includes, but is not limited to, metal tungsten.

Still other embodiments of the present disclosure may provide a dynamic random access memory, which may include the semiconductor device of any of the embodiments of the present disclosure.

The present disclosure can also provide an electronic device that may include the dynamic random access memory in any of the embodiments of the present disclosure. The electronic device includes, but is not limited to, a smart phone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source, and the like.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

at least one stacked metal layer disposed above the semiconductor substrate;

an air gap disposed along a side of the stacked metal layers to surround the stacked metal layers;

a first spacer disposed along a side of the air gap to surround the air gap;

wherein the air gap is between the stacked metal layers and the first spacer.

2. The semiconductor device according to claim 1, further comprising:

and the intermetallic dielectric layer is arranged above the semiconductor substrate and is filled in the groove surrounded by the first spacers.

3. The semiconductor device according to claim 2, further comprising:

the lower barrier layer is formed on the lower surface of the stacked metal layer;

and the upper barrier layer is formed on the upper surface of the stacked metal layer.

4. The semiconductor device according to claim 3,

the intermetallic dielectric layer is also distributed below the lower barrier layer; the first spacer and the air gap both extend down into the inter-metal dielectric layer.

5. The semiconductor device according to claim 4, further comprising:

the lower stop layer is arranged above the semiconductor substrate and is positioned between the intermetallic dielectric layer and the semiconductor substrate;

an upper stop layer deposited on an upper surface of the upper barrier layer;

and the electrode penetrates through the lower stop layer and the intermetallic dielectric layer along the longitudinal direction and is electrically connected with the stacked metal layer.

6. A dynamic random access memory comprising the semiconductor device of any one of claims 1 to 5.

7. An electronic device comprising the dynamic random access memory according to claim 6.

8. The electronic device of claim 7, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

9. A method of manufacturing a semiconductor device, comprising:

sequentially forming an intermetallic dielectric layer and a stacked metal layer above the semiconductor substrate;

forming a groove on the stacked metal layer in an etching mode, and exposing the intermetallic dielectric layer;

sequentially forming a second spacer and a first spacer on the side wall of the groove, wherein the second spacer is positioned between the stacked metal layers and the first spacer;

removing the second spacer to form an air gap between the stacked metal layers and the first spacer.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising, after the second spacer and the first spacer are formed in this order:

depositing an intermetallic dielectric layer;

performing chemical mechanical polishing treatment on the deposited intermetallic dielectric layer;

and etching the re-deposited intermetallic dielectric layer to expose the second spacers to be removed.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, further comprising, after forming the air gap:

an upper stop layer is deposited over the inter-metal dielectric layer.

12. The method of manufacturing a semiconductor device according to claim 9, wherein the step of sequentially forming the inter-metal dielectric layer and the stacked metal layer over the semiconductor substrate comprises:

depositing a lower stop layer over the semiconductor substrate;

depositing the intermetal dielectric layer on the lower stop layer;

forming an electrode on the intermetal dielectric layer, the electrode penetrating the intermetal dielectric layer and the lower stop layer in a longitudinal direction;

and sequentially forming a lower barrier layer, a stacked metal layer and an upper barrier layer, wherein the stacked metal layer is electrically connected with the electrode.

13. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the step of forming the second spacer and the first spacer includes:

forming the second spacers along the side walls of the grooves by a side wall manufacturing process;

and forming the first spacer along the inner side wall of the second spacer by a side wall manufacture process.