CN104681497A - Manufacture method of storage device - Google Patents
Manufacture method of storage device Download PDFInfo
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- CN104681497A CN104681497A CN201310642148.0A CN201310642148A CN104681497A CN 104681497 A CN104681497 A CN 104681497A CN 201310642148 A CN201310642148 A CN 201310642148A CN 104681497 A CN104681497 A CN 104681497A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000003860 storage Methods 0.000 title abstract 10
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000003989 dielectric material Substances 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 125
- 230000015654 memory Effects 0.000 claims description 73
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 10
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000000227 grinding Methods 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 238000010276 construction Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
The invention relates to a manufacture method of a storage device. The manufacture method comprises the steps of providing a substrate, wherein the substrate comprises a storage unit area and a peripheral area; forming a plurality of first grid electrodes in the storage unit area and forming at least one second grid electrode in the peripheral area; forming a sacrifice layer on the substrate; forming a first stop layer on the sacrifice layer in the storage unit area; carrying out the etching process by adopting the first stop layer as a mask; sequentially forming a second stop layer on the substrate; depositing a dielectric material on the second stop layer; carrying out the flattening process for the dielectric material by adopting the first stop layer and the second stop layer in the storage unit area as a grinding stop layer; removing the first stop layer and the second stop layer in the storage unit area; removing the sacrifice layer in the storage unit area so as to forming a plurality of first contact openings among the first grid electrodes after the first stop layer and the second stop layer are removed. The stop layers in different thicknesses are formed in the storage unit area and the peripheral area, so that a landing area contacting a plug is not compressed while the size of the storage device is further reduced.
Description
Technical field
The invention relates to a kind of manufacture method of memory.
Background technology
In general, along with the size of memory reduces gradually, in order to overcome more and more little live width and prevent contact plunger generation aligning mistake (misalignment), self-aligning contact plug (self-aligned contact, SAC) technique can be adopted.
In self-aligning contact plug technique, the thickness of gate lateral wall can affect the size of the contact plunger be formed between grid.Memory component comprises memory cell areas and surrounding zone, in general, can form grid in memory cell areas and surrounding zone simultaneously simultaneously.Afterwards, etch process can be carried out to the sidewall of grid, so that the formation of contact plunger subsequently.
But in some memory constructions, surrounding zone can be formed with metal silicide on grid, source electrode and drain region.If carry out etch process to the sidewall of grid, metal silicide will be caused to expose, and then affect the electric characteristics of memory.Therefore, the grid and source/drain regions of surrounding zone are formed in the memory construction of metal silicide, cannot etch the clearance wall of this grid (sidewall), affect the formation of subsequent touch connector.Therefore when reducing the size of memory further, the problem that the touch-down zone (landing area) that can produce contact plunger is compressed.
Therefore, industry needs a kind of manufacture method that can reduce the memory of the size of memory when not exposing metal silicide and do not compress the touch-down zone of contact plunger badly, to overcome the problems referred to above.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of memory, makes, when reducing memory-size further, can not produce the problem that contact plunger touch-down zone is compressed.
The invention provides a kind of manufacture method of memory, comprising: provide substrate, substrate comprises memory cell areas and surrounding zone; In memory cell areas, form multiple first grid and on surrounding zone, form at least one second grid; In substrate, form sacrifice layer, wherein sacrifice layer covers first grid, second grid and insert between first grid; The first stop-layer is formed on the sacrifice layer of memory cell areas; With the first stop-layer for mask (mask) carries out etch process, to remove the sacrifice layer of surrounding zone, and then expose the second grid on surrounding zone; In substrate, form the second stop-layer to compliance, the second stop-layer cover the first stop-layer, sacrifice layer sidewall, with surrounding zone on second grid; Deposition of dielectric materials on the second stop-layer; As polish stop layer, flatening process is carried out to dielectric material using first and second stop-layer in memory cell areas, to form interlayer dielectric layer in surrounding zone; Remove the first stop-layer in memory cell areas and the second stop-layer; And after removing the first stop-layer and the second stop-layer, the sacrifice layer in removal memory cell areas to form multiple first contact openings between first grid.
The present invention by forming thick stop-layer as polish stop layer in memory cell areas, and forms thin stop-layer using as etching stopping layer, to form the stop-layer of different-thickness in memory cell areas and surrounding zone simultaneously on surrounding zone.Thus, when forming interlayer dielectric layer in surrounding zone, thick polish stop layer can protect the sacrifice layer in memory cell areas do not affect by the grinding technics of interlayer dielectric layer and produce the problems such as depression, is conducive to the technique of follow-up formation contact plunger.Further, in the step forming contact openings, thin etching stopping layer then can prevent the top of second grid, clearance wall and source/drain regions to be damaged.Thus, the clearance wall of memory cell areas and surrounding zone all has complete structure, and can form self-aligned contact hole between two adjacent clearance walls, makes memory have good element characteristic.In addition, owing to being formed in the memory construction of metal silicide on the second grid and source/drain regions of surrounding zone, cannot etching the clearance wall of second grid, affect the formation of subsequent touch.Therefore, more contribute to controlling the distance between second grid and contact plunger by forming thinner stop-layer, in order to the formation of subsequent touch connector, therefore when reducing the size of memory further, the problem that the touch-down zone (landing area) that can not produce contact plunger is compressed.
Accompanying drawing explanation
Figure 1A to Fig. 1 O is the technique generalized section of the memory according to the embodiment of the present invention.
Symbol description:
100 ~ memory;
102 ~ substrate;
104 ~ memory cell areas;
106 ~ surrounding zone;
108 ~ first grid;
110 ~ second grid;
108a, 110a ~ clearance wall;
112 ~ sacrifice layer;
114,116 ~ stop-layer;
118 ~ dielectric material;
120 ~ interlayer dielectric layer;
122 ~ opening;
124 ~ dielectric material;
130,132 ~ source/drain regions;
140,142 ~ contact openings;
140a, 142a ~ contact plunger;
210,230,232 ~ metal silicide.
Embodiment
Making and the use of the embodiment of the present invention are below described.The embodiment of the present invention provides many suitable inventive concepts and can be implemented on various specific background widely.The specific embodiment disclosed only for illustration made from ad hoc approach and using the present invention, and is not used to limit to scope of the present invention.
It is to be understood that the disclosure below this specification provides many different embodiments or example, to implement different characteristic of the present invention.And the disclosure below this specification is the particular example describing each component and arrangement mode thereof, in the hope of simplifying the explanation of invention.Certainly, these specific examples and be not used to limit the present invention.Such as, if the disclosure below this specification describes, a fisrt feature is formed at above a second feature, namely represent that it comprises formed above-mentioned fisrt feature with above-mentioned second feature is the embodiment directly contacted, also contain and still additional feature can be formed between above-mentioned fisrt feature and above-mentioned second feature, and make the embodiment that above-mentioned fisrt feature may directly not contact with above-mentioned second feature.In addition, in explanation of the present invention, different example may use the reference symbol of repetition and/or use word.These replicators or be to simplify and object clearly with word, and be not used to limit the relation between each embodiment and/or described surface structure.
In order to reduce the size of memory when not making metal silicide expose, the thickness of the etching stopping layer of the memory cell areas of memory is set to different from the thickness of the etching stopping layer of surrounding zone by the present invention, so further can reduce the size of memory when not making metal silicide expose.
Figure 1A to Fig. 1 O is the technique generalized section of the memory 100 according to the embodiment of the present invention.
Please refer to Figure 1A, first, provide substrate 102, substrate 102 comprises memory cell areas 104 and surrounding zone 106.Substrate 102 can comprise silicon base, SiGe substrate or silicon carbide substrate.In addition, substrate 102 can be silicon-on-insulator (silicon-on insulator, SOI) substrate.Moreover, also can comprise other suitable substrates, such as, multilayer (multi-layered) substrate, gradient (gradient) substrate, blend together orientation (hybrid orientation) substrate etc.
Then, please refer to Figure 1B, memory cell areas 104 with surrounding zone 106 form multiple first grid 108 and a second grid 110 respectively.First grid 108 and second grid 110 can comprise, such as doped polycrystalline silicon (doped polysilicon).In addition, first grid 108 and second grid 110 also can include the first clearance wall 108a and the second clearance wall 110a, are formed at first grid 108 with on the sidewall of second grid 110.First clearance wall 108a and the second clearance wall 110a can comprise one or more dielectric material, such as, and the dielectric materials such as silicon nitride, silica, silicon oxynitride.Substrate 102 also includes the both sides that multiple source/drain pole region 130 and 132 is formed at first grid 108 and second grid 110 respectively.In addition, in certain embodiments, optionally (optionally) metal silicide 210,230 and 232 can be formed respectively, to reduce contact resistance on second grid 110 and source/drain regions 130 and 132.The material of metal silicide 210,230 and 232 can comprise cobalt silicide.
Please refer to Fig. 1 C, then, form sacrifice layer 112 in substrate 102, wherein sacrifice layer 112 covers described first grid 108 and second grid 110 and inserts between described first grid 108.Sacrifice layer 112 can include, but not limited to silicon dioxide, polysilicon or aforesaid combination.The method forming sacrifice layer 112 can comprise, chemical vapour deposition (CVD) (chemical vapor deposition, CVD), rotary coating (spin on coating) or aforesaid combination.In addition, in certain embodiments, flatening process can be carried out to the surface of sacrifice layer 112, such as, chemical mechanical milling tech (chemical mechanical polishing, CMP).
Then, please refer to Fig. 1 D, sacrifice layer 112 is formed stop-layer 114.Stop-layer 114 can be nitrogenous material, such as, and silicon nitride, silicon oxynitride or aforesaid combination.The formation method of stop-layer 114 comprises: chemical vapour deposition (CVD) (chemical vapor deposition, CVD), rotary coating (spin on coating) or aforesaid combination.
Afterwards, a Patternized technique is carried out to stop-layer 114, to remove the stop-layer 114 (as referring to figure 1e) beyond memory cell areas 104.The technique of patterning stop-layer can comprise micro-shadow (lithography) and dry ecthing, such as, and reactive ion etch (reactive ion etching, RIE).
Then, please refer to Fig. 1 F, be used as mask (mask) with stop-layer 114 and carry out an etch process, to remove the sacrifice layer 112 on surrounding zone 106.As shown in fig. 1f, the second grid 110 on surrounding zone 106 is exposed out further.In embodiments of the present invention, stop-layer 114 is about 1:5 ~ 1:10 with the Thickness Ratio of sacrifice layer 112.
After the sacrifice layer 112 removed on surrounding zone 106, then, please refer to Fig. 1 G, above substrate 102, form a stop-layer 116.As shown in Figure 1 G, the second grid 110 on remaining stop-layer 114, the exposed sidewall of sacrifice layer 112 and surrounding zone 106 is covered in stop-layer 116 compliance.Stop-layer 116 can be nitrogenous material, such as, and silicon nitride, silicon oxynitride or aforesaid combination.In one embodiment, stop-layer 114 is different mutually from the material of stop-layer 116, and for example, stop-layer 114 can be silicon nitride, and stop-layer 116 can be silicon oxynitride.The formation method of stop-layer 116 can comprise: chemical vapour deposition (CVD) (chemical vapor deposition, CVD), rotary coating (spin on coating) or aforesaid combination.In embodiments of the present invention, the stop-layer 114 in memory cell areas 104 is 20nm ~ 100nm with the gross thickness of stop-layer 116.In certain embodiments, stop-layer 114 is 3:1 ~ 3:9 with the Thickness Ratio of stop-layer 116.
Then, please refer to Fig. 1 H, in memory cell areas 104 and the deposition of dielectric materials 118 on surrounding zone 106 of substrate 102.Dielectric material 118 can comprise silica, silicon nitride, silicon oxynitride, advanced low-k materials (low-k dielectrics) or other suitable dielectric materials.
Please refer to Fig. 1 I, after formation dielectric material 118, common as polish stop layer using the stop-layer 114 in memory cell areas 104 and stop-layer 116, flatening process is carried out to dielectric material 118, to define the interlayer dielectric layer 120 on surrounding zone 106.
Then, please refer to Fig. 1 J, remove the stop-layer 114 and 116 in memory cell areas 104.The method of removal stop layer 114 and 116 can be etch process.
Please refer to Fig. 1 K, the first grid 108 of memory cell areas 104 forms multiple opening 122, its split shed 122 is formed in the sacrifice layer 112 on first grid 108.The formation method of opening 122 can be dry ecthing, such as reactive ion etch (reactive ion etching, RIE).
Then, please refer to Fig. 1 L, in opening 122, insert dielectric material 124.Dielectric material 124 can comprise boron-phosphorosilicate glass, silica or aforesaid combination.The method forming dielectric material 124 can be, use if the process deposits dielectric material 124 of chemical vapour deposition (CVD) is above substrate 102, remove the dielectric material 124 (techniques such as etch-back (etch back) or CMP such as, can be used) beyond opening 122 again.
Please refer to Fig. 1 M, after formation dielectric material 124, using dielectric material 124 as mask (mask), remove remaining sacrifice layer 112 in memory cell areas 104, to form multiple contact openings 140.Contact openings 140 is formed between every two adjacent first grids 108.The method forming contact openings 140 can comprise dry ecthing, wet etching or aforesaid combination.
Then, with reference to 1N figure, multiple contact openings 142 is formed.The method forming contact openings 142 can be and first forms patterned mask layer (not illustrating) in memory cell areas 104 and surrounding zone 106, to cover the predetermined region formed beyond contact openings 142 in contact openings 140 and interlayer dielectric layer 120, and expose the predetermined region forming contact openings 142 in interlayer dielectric layer 120.This patterned mask layer can be patterning photoresistance or patterned hard mask layer.Then, using the stop-layer 116 on surrounding zone 106 as etching stopping layer, the interlayer dielectric layer 120 on etching surrounding zone 106 is to form multiple contact openings 142.The method forming contact openings 142 can comprise dry ecthing, wet etching or aforesaid combination.After the etch process, method, plasma ashing method or its combination can be divested by wet type and remove any used patterned mask layer (not illustrating).
Then, please refer to Fig. 1 O, remove the stop-layer 116 in contact openings 142, make contact openings 142 expose second grid 110, source/drain regions 132 respectively.In the embodiment having metal silicide, contact openings 142 exposes the metal silicide 210 and 232 on second grid 110, source/drain regions 132.Then, in contact openings 140 and 142, insert electric conducting material, to form contact plunger 140a and 142a respectively, namely complete the making of memory 100.Electric conducting material can include, but not limited to tungsten, copper, aluminium, other suitable metals, aforesaid alloy or aforesaid combination.The method inserting electric conducting material can comprise deposits conductive material above substrate 102 and in contact openings 140 and 142, remove the electric conducting material beyond contact openings 140 and 142 again, etch-back or CMP wherein can be used to remove electric conducting material beyond contact openings 140 and 142.
The present invention is common as polish stop layer by forming stop-layer 114 and 116 in memory cell areas 104, and on surrounding zone 106, be formed with stop-layer 116 using as etching stopping layer, to form the stop-layer of different-thickness in memory cell areas 104 with surrounding zone 106 simultaneously.Thus; when forming interlayer dielectric layer 120 in surrounding zone; thick polish stop layer (stop-layer 114 and 116) can protect the sacrifice layer 112 in memory cell areas 104 do not affect by the grinding technics of interlayer dielectric layer 120 and produce the problems such as depression, is conducive to the technique of follow-up formation contact plunger 140a.Further, in the step forming contact openings 142, thin etching stopping layer (stop-layer 116) then can prevent the top of second grid 110, clearance wall 110a and source/drain regions 132 to be damaged.Thus, the clearance wall of memory cell areas and surrounding zone all has complete structure, and can form self-aligned contact hole between two adjacent clearance walls, makes memory have good element characteristic.In addition, owing to being formed in the memory construction of metal silicide 210,232 on the second grid 110 and source/drain regions 132 of surrounding zone 106, cannot etch the clearance wall of second grid 110 (sidewall) 110a, affect the formation of subsequent touch connector 142a.Therefore, more contribute to controlling the distance between second grid 110 and contact plunger 142a by forming thinner stop-layer 116, in order to the formation of subsequent touch connector 142a, therefore when reducing the size of memory further, the problem that the touch-down zone (landing area) that can not produce contact plunger 142a is compressed.
Although the present invention discloses as above with preferred embodiment, so itself and be not used to limit the present invention, have in any art and usually know the knowledgeable, without departing from the spirit and scope of the present invention, when can change, substitute and retouch.For example, have in any art and usually know that the knowledgeable can understand many features described herein easily, function, Design and material can change within the scope of the invention.Moreover; protection scope of the present invention is not confined to technique in specification in described specific embodiment, machine, manufacture, material composition, device, method and step; have in any art and usually know that the knowledgeable can understand existing or following developed technique, machine, manufacture, material composition, device, method and step from disclosure of the present invention, as long as identical function or obtain identical result substantially and all can be used in the present invention substantially can be implemented herein in described embodiment.Therefore, protection scope of the present invention comprises above-mentioned technique, machine, manufacture, material composition, device, method and step.In addition, each claim forms other embodiment, and protection scope of the present invention also comprises the combination of each claim and embodiment.
Claims (13)
1. a manufacture method for memory, is characterized in that, described method comprises:
There is provided a substrate, this substrate comprises a memory cell areas and a surrounding zone;
In this memory cell areas, form multiple first grid and form at least one second grid on this surrounding zone;
In this substrate, form a sacrifice layer, wherein this sacrifice layer covers described first grid, described second grid and insert between described first grid;
One first stop-layer is formed on this sacrifice layer of memory cell areas;
With this first stop-layer for mask carries out an etch process, to remove this sacrifice layer of surrounding zone, and then expose this second grid on this surrounding zone;
In this substrate, form to compliance one second stop-layer, this second stop-layer cover this first stop-layer, this sacrifice layer sidewall, with this surrounding zone on this second grid;
A dielectric material is deposited on this second stop-layer;
As polish stop layer, one flatening process is carried out to this dielectric material using first and second stop-layer of this in this memory cell areas, to form an interlayer dielectric layer in this surrounding zone;
Remove this first stop-layer in memory cell areas and this second stop-layer; And
After removing this first stop-layer and this second stop-layer, remove this sacrifice layer in this memory cell areas to form multiple first contact openings between described first grid.
2. the manufacture method of memory as claimed in claim 1, it is characterized in that, the Thickness Ratio of this first stop-layer and this sacrifice layer is about 1:5 ~ 1:10.
3. the manufacture method of memory as claimed in claim 2, it is characterized in that, the gross thickness of this first and second stop-layer in this memory cell areas is 20nm ~ 100nm.
4. the manufacture method of memory as claimed in claim 1, it is characterized in that, this sacrifice layer comprises silicon dioxide or polysilicon.
5. the manufacture method of memory as claimed in claim 1, it is characterized in that, the material of this interlayer dielectric layer comprises silica, silicon nitride, silicon oxynitride or advanced low-k materials.
6. the manufacture method of memory as claimed in claim 1, it is characterized in that, the Thickness Ratio of first and second stop-layer is 3:1 ~ 3:9.
7. the manufacture method of memory as claimed in claim 1, is characterized in that, after described first contact openings of formation, also comprises:
Multiple second contact openings is formed in this interlayer dielectric layer.
8. the manufacture method of memory as claimed in claim 7, it is characterized in that, described method also comprises:
Multiple first contact plunger is formed in described first opening; And
Multiple second contact plunger is formed in described second opening.
9. the manufacture method of memory as claimed in claim 1, it is characterized in that, this first stop-layer comprises silicon nitride, silicon oxynitride or aforesaid combination.
10. the manufacture method of memory as claimed in claim 1, it is characterized in that, this second stop-layer comprises silicon nitride, silicon oxynitride or aforesaid combination.
The manufacture method of 11. memories as claimed in claim 8, it is characterized in that, described method also comprises:
Forming one source pole district and a drain region in the surrounding zone of substrate is positioned at this second grid both sides.
The manufacture method of 12. memories as claimed in claim 11, is characterized in that, described second contact plunger be formed at respectively this second grid, this source area, with this drain region on.
The manufacture method of 13. memories as claimed in claim 12, it is characterized in that, this surrounding zone also comprises multiple metal silicide, is formed at this second grid, this source area respectively, with on this drain region, and described second contact plunger is positioned on described metal silicide.
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| CN111834392A (en) * | 2019-04-22 | 2020-10-27 | 华邦电子股份有限公司 | Resistive random access memory structure and manufacturing method thereof |
| CN114122256A (en) * | 2020-09-01 | 2022-03-01 | 华邦电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN104681497B (en) | 2017-05-24 |
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