CN114334859A

CN114334859A - Circuit stacking structure

Info

Publication number: CN114334859A
Application number: CN202111622430.3A
Authority: CN
Inventors: 张志铭
Original assignee: Universal Global Technology Kunshan Co Ltd
Current assignee: Universal Global Technology Kunshan Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-04-12
Also published as: TWI808606B; TW202327412A

Abstract

The invention provides a circuit stacking structure, which comprises a first substrate, a control chip, a heat dissipation element, a passive element, a support plate, a second substrate and an inductance element, wherein the inductance element is arranged in the circuit stacking structure and is connected with the control chip such as a switching power supply control chip, the large-volume inductance element can be arranged in the circuit stacking structure through the support plate, the control chip is arranged on the first substrate to be exposed, the heat dissipation element is arranged on the control chip, and the first substrate and the second substrate are electrically connected through a plurality of conductive elements of the support plate. The invention achieves the modularized design, saves the cost, simplifies the complexity of circuit assembly, can reduce the setting space of the circuit, has high operation efficiency and better heat dissipation, and increases the product competitiveness.

Description

Circuit stacking structure

Technical Field

The present invention relates to an assembly of electronic components, and more particularly, to a circuit stack structure.

Background

The conventional circuit assembly includes a controller chip and corresponding passive components (passive devices), sensors, etc., so that many circuit assemblies are arranged in a planar or double-sided manner, which requires a large layout space of circuit boards in terms of area and has a certain degree of complexity in the process even though the circuit assemblies are arranged in a double-sided manner.

And when the chip has the operational capability in the circuit assembly, the heat dissipation problem of the chip is inevitable.

Disclosure of Invention

In view of the problems of the background art, the present invention provides a circuit stack structure to solve the problems of large layout space, complex process and heat dissipation of the chip in circuit assembly.

According to an embodiment of the present invention, a circuit stack structure is provided, which includes:

a first substrate; the control chip is arranged on the upper surface of the first substrate and is electrically connected with the first substrate; a plurality of passive elements arranged on the upper surface or the lower surface of the first substrate, wherein the passive elements are electrically connected with the first substrate; a second substrate; a supporting plate, which is arranged between the first substrate and the second substrate and is provided with a plurality of conductive elements; and an inductance element arranged in the accommodating space formed by the first substrate, the second substrate and the supporting plate. The first ends of the conductive elements are respectively electrically connected with the first substrate, the second substrate is electrically connected with the second ends of the conductive elements, and the inductance element is electrically connected with the first substrate or the second substrate.

The invention has the possible technical effects of achieving the modularized design, saving the cost, simplifying the complexity of circuit assembly, reducing the setting space of the circuit, having high operation efficiency and better heat dissipation and increasing the product competitiveness.

For a further understanding of the techniques, methods and technical effects of the invention to achieve the stated objectives, it is believed that the objects, features and characteristics of the invention will be more fully understood from the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are included to provide a further understanding of the invention, and are not intended to be limiting.

Drawings

Fig. 1 is an exploded view of a circuit stack according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a combination structure of a circuit stack structure according to an embodiment of the invention.

Fig. 3 is a schematic view of a frame plate and a plurality of conductive elements according to an embodiment of the invention.

Fig. 4 is a schematic diagram illustrating a first inductor and a second inductor connecting a first chip and a second chip in a circuit stack structure according to an embodiment of the invention.

Fig. 5 is a schematic view of a second substrate having a plurality of electrical contacts according to an embodiment of the invention.

Detailed Description

The following is a description of the embodiments of the present disclosure related to "circuit stack structure" by specific embodiments, and those skilled in the art can understand the advantages and effects of the present disclosure from the disclosure of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modification and various other changes, which can be made in various details within the specification and without departing from the spirit and scope of the invention. The drawings of the present invention are for illustrative purposes only and are not intended to be drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art and ordinary skill in the art to obtain other drawings based on these drawings without undue effort.

The invention discloses a circuit stack structure, which can adjust voltage or process (power supply) signals and can be arranged on the power supply side of an electronic product for signal processing, for example, arranged in a signal processing circuit such as alternating current-to-direct current (AC/DC), direct current-to-direct current (DC/DC), direct current-to-alternating current (DC/AC) and the like. The electronic product may be, for example, a consumer electronic product, a server, a processor chip, a controller chip, an electronic product for a fifth generation mobile communication technology (5G: 5th generation) application, or an electronic product for an Artificial Intelligence (AI) application, so as to provide a module application with a large current.

Referring to fig. 1 and 2, fig. 1 is an exploded schematic view of a circuit stack structure according to an embodiment of the invention. Fig. 2 is a schematic diagram of a combination structure of a circuit stack structure according to an embodiment of the invention.

The present invention provides a circuit stack structure 1, which includes but is not limited to: a first substrate 11, a control chip 12, a plurality of passive components 13, a supporting board 14, a second substrate 15 and an inductance component 16. The control chip 12 is disposed on the upper surface 111 of the first substrate 11, the control chip 12 is electrically connected to the first substrate 11, a heat dissipation element 121 is disposed on the control chip 12, the control chip 12 can be a Switching Power Supply (SPS) control chip, and the heat dissipation element 121 can be a heat dissipation copper sheet.

In an embodiment, the heat dissipation element 121 is not limited to be a heat dissipation fin or a heat dissipation paste coating for enhancing heat dissipation, and the invention is not limited thereto.

The plurality of passive elements 13 are disposed on the upper surface 111 or the lower surface 112 of the first substrate 11, the plurality of passive elements 13 are electrically connected to the first substrate 11, and the plurality of passive elements 13 may include a resistor, a capacitor, or an inductor. In the present embodiment, the plurality of passive elements 13 may be only configured as capacitors and are disposed on the upper surface 111 or the lower surface 112 of the first substrate 11, and the invention is not limited thereto.

The supporting plate 14 is disposed between the first substrate 11 and the second substrate 15, and the supporting plate 14 may have a hole or a groove, and the hole or the groove may have any shape, such as a square or a circle. And a plurality of conductive elements 141 are provided on the support plate 14. Therefore, the inductance element 16 is disposed in the accommodating space 200 formed by the first substrate 11, the second substrate 15 and the supporting plate 14.

The first ends 142 of the conductive elements 141 are electrically connected to the first substrate 11, respectively. The second substrate 15 is electrically connected to the second ends 143 of the conductive elements 141, so that the inductive element 16 is accommodated in the circuit stack structure 1, and the inductive element 16 is also electrically connected to the first substrate 11 or the second substrate 15, or the inductive element 16 is electrically connected to both the first substrate 11 and the second substrate 15.

Since the volume of the inductance element 16 is usually larger, when the inductance element 16 is disposed between the first substrate 11, the second substrate 15 and the supporting plate 14, the inductance element 16 is covered by the first substrate 11, the second substrate 15 and the supporting plate 14, and the inductance element 16 is substantially invisible in appearance. Therefore, in the present embodiment, the inductance element 16 with a larger volume can be a power type inductance or a filter type inductance, so the inductance element 16 is covered by the supporting plate 14, and the inductance element 16 can be easily electrically connected to the first substrate 11 and the second substrate 15 when being covered by the supporting plate 14, thereby greatly reducing the space occupied by the components in the circuit design. Also in the case of inductive element 16 in the form of a coil winding, inductive element 16 may be a double winding or more inductive element, and thus the connection point of inductive element 16 may be (one end of) an electrode or a winding coil, and the invention is not limited to the foregoing.

Referring to fig. 3, fig. 3 is a schematic view of a frame plate and a plurality of conductive elements according to an embodiment of the invention. Wherein figure 3 shows a top or bottom view that may represent one perspective of the frame plate.

In one embodiment, the supporting Board 14 is formed by a plurality of Frame plates (Frame boards) 140, the Frame plates 140 are stacked on each other, and each Frame plate 140 has a plurality of conductive elements 141. The plurality of conductive elements 141 of the frame plate 140 are Plated Through Holes (PTHs), the plurality of conductive elements 141 of each frame plate 140 are stacked on each other to be electrically connected to each other, first ends 142 of the plurality of conductive elements 141 stacked on the uppermost frame plate 140 are respectively electrically connected to the first substrate 11, and second ends 143 of the plurality of conductive elements 141 stacked on the lowermost frame plate 140 are respectively electrically connected to the second substrate 15.

In an embodiment, the number of the plurality of frame plates 140 can be stacked according to actual requirements, and the setting height of the whole circuit stacking structure 1 is changed to accommodate the inductive elements 16 with different sizes and forms, so as to achieve a modular design.

In one embodiment, when the inductive element 16 is configured as a Power high-current inductor and the control chip 12 is configured as a Switching Power Supply (SPS) control chip, the inductive element 16 and each passive element 13 are integrated as capacitors inside the circuit stack 1. When the support plate 14 is used and a plurality of frame plates 140 are used to stack and cover the inductance element 16, not only can three-dimensional (3d) circuit stacking assembly of the switching power supply design be realized, compared with the traditional assembly, the space of planar arrangement of a large number of circuits can be reduced, the occupied assembly space is reduced in a stacking assembly mode, and the maximum total load current of the designed support plate 14 or each frame plate 140 can be 144 amperes when the total height is up to 7.8mm, when the heat dissipation element 121 (copper sheet) matched above the circuit stacking structure 1 is used and the inductance element 16 is in a two-inductance arrangement mode of a double-winding inductance, the output current of each phase power supply (signal) adjusting loop can be 40 amperes at most, the maximum current of the whole circuit stacking structure 1 can be 80 amperes, and the whole efficiency can also be improved to 85% due to good heat dissipation.

In an embodiment, when the height of each frame plate 140 and the accommodating space 200 are provided by holes or grooves, the height, the size and the shape of the holes or the grooves can be adjusted, and the height of each frame plate 140 can be different, and each frame plate 140 can be designed to be adjusted between 2.5mm to 10mm after being stacked. The invention can realize modular design, can be easily expanded or reduced, and can reduce the circuit layout space of the substrate to save cost.

In one embodiment, since the control chip 12, the passive elements 13 and the inductance element 16 are disposed on the first substrate 11 and the second substrate 15, the circuit components are vertically disposed, so as to greatly reduce and effectively utilize the circuit layout space of the substrates.

Referring to fig. 4, fig. 4 is a schematic diagram showing a first inductor and a second inductor connecting a first chip and a second chip in a circuit stack structure according to an embodiment of the invention.

The control chip 12 can be configured as a first chip 122 and a second chip 123, and when the inductance element 16 is a dual-winding inductance element, the first end 163 of the first inductance 161 formed by one winding of the dual-winding inductance element is electrically connected to the first chip 122 through the first substrate 11, and the first end 164 of the second inductance 162 formed by the other winding of the dual-winding inductance element is electrically connected to the second chip 123 through the first substrate 11. In addition, the

second ends

165 and 166 of the first inductor 161 and the second inductor 162 respectively formed by the dual windings of the dual winding inductor device are electrically connected to the second substrate 15 respectively to be led to the output node VOUT.

In one embodiment, the second substrate 15 is electrically connected to the control chip 12 (i.e. electrically connected to the first chip 122 and the second chip 123) through the plurality of conductive elements 141 of the plurality of frame plates 140 and the first substrate 11. Therefore, the electrical contact of the second substrate 15 receives a power (signal) VIN and transmits the power (signal) VIN to the first chip 122 and the second chip 123 through the plurality of conductive elements 141 of each frame plate 140 and the first substrate 11, the first chip 122 and the second chip 123 adjust the power (signal) VIN, and the power (signal) VIN is output from the electrical contact of the second substrate 15, that is, the output contact VOUT, after passing through the first inductor 161 and the second inductor 162 of the dual-winding inductor device respectively after the power adjustment.

Referring to fig. 5, fig. 5 is a schematic view illustrating that the second substrate is provided with a plurality of electrical contacts according to an embodiment of the invention.

The lower surface 151 of the second substrate 15 is provided with a plurality of electrical contacts 152, which may be circular electrical contacts or square electrical contacts (PAD), at least one electrical contact 152 of the plurality of electrical contacts 152 is electrically connected to the inductive element 16, and the plurality of electrical contacts 152 is electrically connected to the plurality of conductive elements 141 of the lowermost frame plate 140 of the plurality of frame plates 140 stacked with each other.

In one embodiment, when the inductive element 16 is a dual-winding inductive element, at least two electrode contacts or terminals of the dual-winding inductive element are electrically connected to at least two of the plurality of electrical contacts 152.

In one embodiment, the control chip 12 and the electrical contacts of the passive elements 13 are connected to the second substrate 15 through the circuit layout of the first substrate 11 and the conductive elements 141 of the frame plates 140. And the electrical contacts of the inductance element 16 can be sequentially guided and connected to the second substrate 15 through the first substrate 11 and the plurality of conductive elements 141 of the plurality of frame plates 140. It is also not excluded that the electrical contacts of the inductance element 16 are electrically connected through the second substrate 15, then the plurality of conductive elements 141 of the plurality of frame plates 140 and the first substrate 11 are electrically connected to the control chip 12, and finally the electrical contacts of the components are guided back to the second substrate 15 by the above-mentioned method. Therefore, the electrical contact 152 provided on the second substrate 15 itself can form an electrical contact for signal input and output.

In an embodiment, as shown in fig. 5, a Solder Ball (Solder Ball) or a Solder Bump (Solder Bump) may be further disposed on the plurality of electrical contacts 152 of the second substrate 15, which is not shown in the figure, and can be quickly mounted on another substrate during the SMT process, and the invention is not limited thereto.

In an embodiment, by disposing the plurality of conductive elements 141 of each frame plate 140, and according to the circuit (circuit) layouts of the first substrate 11 and the second substrate 15, and matching with the conductive connection of the plurality of conductive elements 141 of each frame plate 140, the plurality of electrical contacts 152 of the second substrate 15 can be electrically connected to each electrical circuit, and can be easily connected to an external substrate (not shown) through the plurality of electrical contacts 152, so that the circuit stacked structure 1 can operate normally and is convenient to assemble. That is, the circuit stack structure 1 can be assembled on an external substrate (not shown) by an SMT process. The circuit layout of the first substrate 11 and the second substrate 15 is determined by the arrangement form and number of the control chip 12, the passive elements 13, the inductive element 16, and the conductive element 141 of the frame plate 140, and the arrangement number and form of the electrical contacts 152 of the second substrate 15 are determined, and the invention is not limited to the foregoing.

In an embodiment, the first substrate 11 and the second substrate 15 may be multi-layer boards, which can enhance flexibility and modularity of the circuit layout of the substrates, and the invention is not limited thereto.

Referring to fig. 1 and fig. 2, when a plurality of frame plates 140 are stacked on each other, for example, three frame plates 140, in an embodiment, the conductive element 141 of the upper frame plate 140 is electrically connected to the conductive element 141 of the middle frame plate 140 and the conductive element 141 of the lower frame plate 140 in sequence. Wherein each frame plate 140 is disposed with the stacking direction as the longitudinal reference, and the conductive elements 141 connected longitudinally are disposed at one or more positions of the upper, middle and lower frame plates 140, so that the conductive elements 141 of the upper, middle and lower frame plates 140 are electrically connected vertically.

In one embodiment, the conductive element 141 of each frame plate 140 is not disposed in a longitudinal direction. The conductive element 141 may also be a conductive metal platinum disposed on the surface of the frame plate 140 according to design requirements, and the form, shape and disposition direction are not limited. Moreover, when the conductive element 141 of each frame plate 140 is configured as a Plated Through Hole (PTH), the conductive element 141 can be configured to be connected in a multi-stage manner according to the thickness of the frame plate 140 or the number of layers of the frame plate 140, and the invention is not limited thereto.

Therefore, the conductive elements 141 of the upper, middle and lower frames 140 shown in the diagram of fig. 2 are electrically connected in the longitudinal direction to form a plurality of signal or power signal transmission paths (i.e., the signal transmission paths formed by the conductive elements 141 of the upper frame 140, the conductive elements 141 of the middle frame 140 and the conductive elements 141 of the lower frame 140), so that at least one or more signal or power signal can be transmitted between the first substrate 11 and the second substrate 15, and the invention is not limited thereto.

In one embodiment, the first ends 142 of the conductive elements 141 stacked on the uppermost frame plate 140 are electrically connected to a plurality of electrical contacts (not shown) on the lower surface 112 of the first substrate 11, respectively. When the plurality of conductive elements 141 of the frame plate 140 are disposed in a Plated Through Hole (PTH) manner, they are uniformly distributed on the frame plate 140 in a surrounding manner, and the invention is not limited thereto.

In an embodiment, the second substrate 15 is electrically connected to the second ends 143 of the conductive elements 141 of the frame plate 140 stacked at the bottom, that is, the second ends 143 of the conductive elements 141 of the lower frame plate 140 are electrically connected to the electrical contacts (not shown) on the upper surface of the second substrate 15, and the invention is not limited thereto.

Therefore, the present invention can not only dispose the inductance element 16 inside the circuit stack structure 1 to reduce the component disposing area of the circuit. And the heat energy generated when the control chip 12 is a switching power control chip can be also significantly improved by disposing the heat energy at the upper end of the circuit stack structure 1. Since the control chip 12 is disposed above the circuit stack structure 1, the problems of complex chip assembly process and heat dissipation are solved.

In one embodiment, the circuit stack 1 is suitable for Surface Mount Technology (SMT) in order to facilitate stacking and assembling. Therefore, when the circuit stacked structure 1 covers the inductance element 16 as a dual-winding inductance element, the first ends 163 and 164 of the first inductance 161 and the second inductance 162 formed by the dual windings thereof are electrically connected to the first substrate 11 through a substrate plated through hole 113 on the first substrate 11, respectively, and the first inductance 161 and the second inductance 162 of the dual-winding inductance element are electrically connected to the first chip 122 and the second chip 123 through the first substrate 11, respectively, and the invention is not limited to the foregoing.

In an embodiment, after the control chip 12 and the passive components 13 on the first substrate 11 are mounted by a Surface Mount Technology (SMT) in the circuit stacked structure 1, the second substrate 15, the inductive component 16, the plurality of frames 14 and the first substrate 11 are sequentially stacked by the SMT process to complete the circuit stacked structure 1.

[ possible technical effects of the invention ]

The invention has the possible technical effects of achieving modular design, saving cost, simplifying the complexity of circuit assembly and reducing the setting space of the circuit. The invention has high operation efficiency and better heat dissipation, and increases the product competitiveness.

Finally, it should be noted that while in the foregoing specification, the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present inventive concept as defined by the following claims.

Claims

1. A circuit stack, comprising:

a first substrate;

the control chip is arranged on the upper surface of the first substrate and is electrically connected with the first substrate;

a plurality of passive elements arranged on the upper surface or the lower surface of the first substrate, wherein the passive elements are electrically connected with the first substrate;

a second substrate;

a supporting plate, which is arranged between the first substrate and the second substrate and is provided with a plurality of conductive elements; and

the inductance element is arranged in the accommodating space formed by the first substrate, the second substrate and the supporting plate;

the first ends of the conductive elements are respectively electrically connected with the first substrate, the second substrate is electrically connected with the second ends of the conductive elements, and the inductance element is electrically connected with the first substrate or the second substrate.

2. The circuit stack structure of claim 1, wherein the supporting plate is formed by a plurality of frames, the plurality of frames are stacked on each other, each of the frames has the plurality of conductive elements, the plurality of conductive elements of the frames are plated through holes, the plurality of conductive elements of each of the frames are electrically connected to each other by stacking each of the frames on each other, first ends of the plurality of conductive elements of the uppermost frame are electrically connected to the first substrate, respectively, and second ends of the plurality of conductive elements of the lowermost frame are electrically connected to the second substrate, respectively.

3. The circuit stack structure of claim 2, wherein the control chip comprises a first chip and a second chip, and the inductance element is a dual-winding inductance element, a first end of a first inductance formed by one winding of the dual-winding inductance element is electrically connected to the first chip through the first substrate, a first end of a second inductance formed by the other winding of the dual-winding inductance element is electrically connected to the second chip through the first substrate, and each of a first end and a second end of the second inductance formed by the dual-winding of the dual-winding inductance element is electrically connected to the second substrate.

4. The circuit stack structure of claim 3, wherein the control chip is a switching power control chip, the second substrate is electrically connected to the control chip through the conductive elements of the frame plates and the first substrate, the second substrate receives a power source and transmits the power source to the first chip and the second chip through the conductive elements of the frame plates and the first substrate, the first chip and the second chip are power-adjusted, and the power source is output from the second substrate after passing through the first inductor and the second inductor of the dual-winding inductive element respectively after being power-adjusted.

5. The circuit stack structure of claim 3, wherein the first ends of the first inductor and the second inductor formed by the dual windings of the dual winding inductor element are electrically connected to the first substrate through a substrate plated through hole on the first substrate, respectively, such that the first inductor and the second inductor of the dual winding inductor element are electrically connected to the first chip and the second chip through the first substrate, respectively.

6. The circuit stack structure of claim 2, wherein the plurality of frame plates are stacked on each other to a height of 2.5mm to 10 mm.

7. The circuit stack structure of claim 2, wherein the plurality of frame plates are stacked in three.

8. The circuit stack of claim 2, wherein the second substrate is provided with a plurality of electrical contacts, at least one of the electrical contacts is electrically connected to the inductive element, and the electrical contacts are electrically connected to the conductive elements of the lowermost frame plate of the stacked frame plates.

9. The circuit stack structure of claim 1, wherein the control chip has a heat dissipation element disposed thereon, and the heat dissipation element is a copper heat dissipation sheet.

10. The circuit stack structure of claim 1, wherein the plurality of passive components are capacitors.