CN114334810A - Preparation method of three-dimensional packaging structure and three-dimensional packaging structure - Google Patents
Preparation method of three-dimensional packaging structure and three-dimensional packaging structure Download PDFInfo
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- CN114334810A CN114334810A CN202210234833.9A CN202210234833A CN114334810A CN 114334810 A CN114334810 A CN 114334810A CN 202210234833 A CN202210234833 A CN 202210234833A CN 114334810 A CN114334810 A CN 114334810A
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Abstract
The embodiment of the invention provides a preparation method of a three-dimensional packaging structure and the three-dimensional packaging structure, and relates to the technical field of semiconductor packaging. Compared with the prior art, the forming groove is formed on the die pressing switching layer after the carrier plate is stripped, and the traditional slotting/punching technology is avoided, so that the increase of warping or the cracking phenomenon is avoided, and the reliability of the die pressing switching layer is greatly improved. Meanwhile, the stripping difficulty is relatively low, and the carrier plate is used as a mold, so that the high-cost technologies such as etching grooving, laser grooving and the like are avoided, and the preparation cost and the process difficulty are greatly reduced. The structure and the method provided by the invention have the advantages of simple process, low cost and the like, and are more suitable for future multi-chip integrated packaging modes and structures.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a preparation method of a three-dimensional packaging structure and the three-dimensional packaging structure.
Background
With the rapid development of the semiconductor industry, past bump packages and wafer level packages cannot meet the development requirements of future products, and along with the physical limit of the moore's law of wafer manufacturing, the breakthrough in performance is expected to be made, and the breakthrough in packaging is an important checkpoint of future chips.
To solve the problem of insufficient wiring density of organic substrates, Silicon substrates with tsv (through Silicon via) vertical interconnect vias and high density metal wiring have been developed. The silicon wafer is electrically interconnected with the silicon substrate and other through holes in an insulated manner, and TSV integration is adopted, so that the integration density of a system can be improved, and the system-level heterogeneous integration is conveniently realized. A silicon-based passive platform with TSVs is called a TSV Interposer (Interposer). In a 2.5D Interposer package, a plurality of chips are arranged side by side on the Interposer, and higher-density interconnection between the chips and a package substrate is realized through a TSV structure, a Redistribution Layer (RDL), a micro Bump (Bump) and the like on the Interposer.
The TSV technology is the most common technology in the industry at present, and is also the most mature technology at present, but the cost is high, so that each large package factory can look far away; in addition to the TSV technology, there is tgv (through Glass via) technology, but the same TSV technology has the problems of high cost and difficult preparation, so it cannot be used in large scale in the industry at present. In addition, the TSV or TGV technology requires a punching operation on the wafer or the substrate, which is likely to increase warpage and even cause cracks, resulting in poor reliability.
Disclosure of Invention
The object of the present invention includes, for example, providing a method for manufacturing a three-dimensional package structure and a three-dimensional package structure, which can provide a new through hole scheme, have excellent process processability, avoid the existing hole forming technology, have better reliability, and reduce cost.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a method for manufacturing a three-dimensional package structure, including:
providing a carrier plate with a forming convex column;
carrying out mould pressing on the carrier plate to form a mould pressing transfer layer;
stripping the carrier plate to form a forming groove corresponding to the forming convex column on one side surface of the mould pressing transfer layer;
electroplating in the forming groove to form a conductive column;
forming a wiring combination layer on one side surface of the mould pressing switching layer;
a chip is pasted on the surface of the other side of the mould pressing switching layer;
the wiring combination layer is electrically connected with the conductive column, and the conductive column is electrically connected with the chip.
In an alternative embodiment, before the step of molding the die on the other side of the interposer, the method further comprises:
and thinning the molding adapter layer on the other side surface of the molding adapter layer to expose the conductive posts.
In an alternative embodiment, the step of forming a wiring combination layer on one side surface of the mold switching layer includes:
forming a wiring conductive layer in electrical contact with the conductive column on the other side surface of the mold pressing transfer layer;
covering a dielectric layer on the wiring conductive layer;
and forming a pad electrically connected with the wiring conductive layer on the dielectric layer.
In an alternative embodiment, after the step of forming a wiring combination layer on one side surface of the mold interposer, the method further includes:
and carrying out ball planting on the wiring combination layer to form a solder ball.
In an alternative embodiment, the step of attaching a chip to the other side surface of the mold adapter layer comprises:
attaching a plurality of chips with conductive bumps on the other side surface of the die pressing switching layer in a hot pressing fusion mode;
the conductive bump is correspondingly connected with the conductive column.
In an alternative embodiment, the step of providing a carrier plate with a molding protrusion comprises:
providing a metal carrier plate;
and slotting at intervals on the metal carrier plate to form a plurality of forming convex columns.
In an alternative embodiment, after the step of die-attaching a chip to the other side surface of the die-attach interposer, the method further comprises:
mounting the wiring combination layer on a substrate;
wherein the substrate is electrically connected to the wiring combination layer.
In an alternative embodiment, after the step of mounting the wiring combination layer on a substrate, the method further comprises:
and filling a protective material between the molding transfer layer and the chip to form a protective layer.
In a second aspect, the present invention provides a three-dimensional package structure formed by the method for manufacturing a three-dimensional package structure according to any one of the preceding embodiments, the three-dimensional package structure comprising:
the die pressing switching layer is internally provided with a conductive column which penetrates through the die pressing switching layer;
the wiring combination layer is arranged on one side surface of the mould pressing switching layer;
the chip is arranged on the other side surface of the mould pressing switching layer;
the wiring combination layer is electrically connected with the conductive column, and the conductive column is electrically connected with the chip.
In an optional embodiment, the three-dimensional package structure further includes a substrate, the wiring combination layer is attached to the substrate, and the substrate is electrically connected to the wiring combination layer.
The beneficial effects of the embodiment of the invention include, for example:
according to the preparation method of the three-dimensional packaging structure and the three-dimensional packaging structure provided by the embodiment of the invention, firstly, the carrier plate with the forming convex columns is subjected to mould pressing to form the mould pressing transfer layer, then, the carrier plate is peeled off, so that the forming grooves are formed on the mould pressing transfer layer, then, the forming grooves are electroplated to form the conductive columns, and finally, wiring and chip mounting are completed. Compared with the prior art, the forming groove is formed on the die pressing switching layer after the carrier plate is stripped, and the traditional slotting/punching technology is avoided, so that the increase of warping or the cracking phenomenon is avoided, and the reliability of the die pressing switching layer is greatly improved. Meanwhile, the stripping difficulty is relatively low, and the carrier plate is used as a mold, so that the high-cost technologies such as etching grooving, laser grooving and the like are avoided, and the preparation cost and the process difficulty are greatly reduced. The structure and the method provided by the invention have the advantages of simple process, low cost and the like, and are more suitable for future multi-chip integrated packaging modes and structures.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a block diagram illustrating a method for manufacturing a three-dimensional package structure according to a first embodiment of the present invention;
fig. 2 to 9 are process flow diagrams of a method for manufacturing a three-dimensional package structure according to a first embodiment of the invention;
fig. 10 is a schematic view of a three-dimensional package structure according to a second embodiment of the invention.
Icon: 100-a three-dimensional package structure; 110-mold pressing of the transfer layer; 111-forming a groove; 113-a conductive post; 130-wiring combination layer; 131-wiring conductive layer; 133-a dielectric layer; 135-solder balls; 150-chip; 151-protective layer; 170-a substrate; 200-a carrier plate; 210-forming the convex column.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background, the via technology used in the prior art is costly and less reliable. Specifically, the standard 2.5D packaging process flow is as follows: coating, exposing and developing a blank silicon wafer, reserving a through hole area, then etching by a dry method, wherein gases and equipment used in the process are very high and are also the reason for keeping the cost high, then electroplating blind holes to enable electroplating columns to fill the holes, then packaging the front side of the silicon wafer at a wafer level, grinding the back side of the silicon wafer in a grinding mode to enable the electroplating columns to leak out, then attaching chips with different functions to the back side of the silicon wafer, and finally slicing to complete packaging and attaching to a substrate.
Meanwhile, in the prior art, the silicon through hole technology is used for bearing the adapter plate, but the silicon wafer is a single crystal, and the excessive through holes can cause the damage of the crystal, thereby causing the increase of warpage and the serious even breakage of the silicon, and avoiding the defect caused by the concentration of stress by injecting outside.
In order to solve the above problems, the present invention provides a novel three-dimensional package structure and a method for manufacturing the same, which can greatly reduce the cost and improve the stability. It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1, the embodiment provides a method for manufacturing a three-dimensional package structure, which is used for manufacturing a three-dimensional package structure 100, and the method adopts a novel process, avoids the traditional punching processes such as TSV or TGV, and the like, effectively reduces the process difficulty and cost, has higher reliability, and has better performance of the device after mounting.
The preparation method of the three-dimensional packaging structure provided by the embodiment comprises the following steps:
s1: a carrier 200 having a molding protrusion 210 is provided.
Specifically, referring to fig. 2, the carrier 200 may be prepared in advance, for example, a metal carrier 200 is provided first, and then a plurality of forming pillars 210 are formed by forming grooves at intervals on the metal carrier 200. When the slot is spaced, the redundant part needs to be removed to form the spacing part of two adjacent units. It should be noted that, the forming convex column 210 and the metal carrier 200 are an integral structure, and may be grooved at intervals by using a laser grooving process or an etching process, and the forming convex column 210 is formed at a non-grooved portion. Since the carrier 200 can be reused, it can be prepared before packaging, and will not cause excessive cost.
S2: the molding is performed on the carrier 200 to form the mold-transferred layer 110.
Specifically, referring to fig. 3, a molding compound is used to mold the carrier 200, which may be performed by a molding machine, and the molding compound fills gaps between the plurality of molding pillars 210, and the molding compound is cured to form the molding transition layer 110, wherein the plurality of molding pillars 210 are embedded into the molding transition layer 110.
S3: the carrier 200 is peeled off to form a molding groove 111 corresponding to the molding protrusion 210 on one side surface of the mold-pressing transition layer 110.
Specifically, referring to fig. 4 in combination, the carrier board 200 may be peeled off by using a laser lift-off technique, and due to the presence of the molding pillars 210, a plurality of molding grooves 111 are formed on the surface of the mold-pressing transition layer 110 after the peeling. It should be noted that, the carrier 200 may function like a mold, wherein step S3 is a demolding step, and for convenience of stripping, the forming pillar 210 may be designed to be a trapezoid structure or a frustum structure, i.e., the cross-sectional area of the free end of the forming pillar 210 is smaller, so as to be conveniently stripped from the mold-pressing adapting layer 110.
It should be noted that, the molding compound is used for molding, the mold pressing adapting layer 110 with the molding groove 111 is formed, the mold pressing adapting layer can be used as an adapting plate for subsequent signals of the chip 150, advantages of easy plasticity and low cost of the molding compound are fully utilized, fine wiring is manufactured in subsequent processing, and the structure such as the molding groove 111 can be accurately molded by using a mature process of molding by plastic molding, so that the preparation of the subsequent process is facilitated, the cost is greatly reduced, and the reliability is improved.
Of course, here, for convenience of peeling, a UV glue layer may be coated on the carrier 200 before molding, and the peeling operation may be completed by means of ultraviolet irradiation.
S4: conductive posts 113 are formed in the molding grooves 111 by electroplating.
Specifically, referring to fig. 5 in combination, after the peeling is completed, the mold relay layer 110 is turned over, and a metal layer is electroplated on one side surface of the mold relay layer 110, wherein the metal layer is filled in the molding groove 111, and the conductive pillar 113 is formed. Preferably, the conductive pillar 113 may be a copper pillar, which has good conductive performance.
S5: a wiring combination layer 130 is formed on one side surface of the mold interposer 110.
Specifically, see fig. 6 in combination, where the wiring combination layer 130 is electrically connected with the conductive pillar 113. Firstly, a wiring conductive layer 131 electrically contacting with the conductive post 113 is formed on the other side surface of the molding transit layer 110, then a dielectric layer 133 is covered on the wiring conductive layer 131, finally, a groove is formed on the dielectric, and after the metal layer is exposed, metal is deposited in the groove, so that a pad electrically connected with the wiring conductive layer 131 is formed on the dielectric layer 133. The wiring conductive layer 131 is a metal layer, preferably a copper layer, and after the metal layer is formed, the wiring may be patterned and then covered with the dielectric layer 133.
It should be noted that, by means of the front rewiring, each signal contact is led out to be matched with the solder joint of the substrate 170, so that the loss of the signal transmission element can be greatly reduced, and the performance can be improved.
S6: the ball is mounted on the wiring combination layer 130 to form a solder ball 135.
Specifically, with continued reference to fig. 6, after the wiring combination layer 130 is completed, ball mounting may be completed on the bonding pad to form a solder ball 135, and the solder ball 135 is electrically connected to the wiring combination layer 130.
S7: the thinning process is performed on the molding transition layer 110 on the other side surface of the molding transition layer 110 to expose the conductive pillars 113.
Specifically, referring to fig. 7 in combination, the embossed via layer 110 may be thinned by a grinding process, and the thinning may be determined as required, at least the end portions of the conductive pillars 113 need to be exposed.
S8: and a chip 150 is surface-mounted on the other side of the molding adapter layer 110.
Specifically, referring to fig. 8, after the grinding is completed, a plurality of chips 150 are mounted on the grinding side of the die pressing adapter layer 110, each chip 150 has a tiny bump, and the plurality of chips 150 with conductive bumps are mounted on the other side surface of the adapter layer by hot pressing and fusion, wherein the conductive bumps on the plurality of chips 150 are correspondingly connected with the conductive pillars 113, so as to achieve electrical connection between the chips 150 and the conductive pillars 113.
It should be noted that, by thermocompression bonding the front surfaces of the chips 150 with different functions and the conductive pillars 113 on the back surface of the molding adapter layer 110, the package reliability can be improved, and the loss between signal transmissions can be greatly reduced, thereby improving the performance.
S9: the wiring assembly layer 130 is mounted on a substrate 170.
Specifically, referring to fig. 9, the substrate 170 is provided with a corresponding pad structure, the integrated package structure is attached to the substrate 170 in a thermal compression manner, and the solder balls 135 are correspondingly pressed to the pad structure on the substrate 170, so that the substrate 170 and the wiring combination layer 130 are electrically connected.
S10: a protective material is filled between the mold relay layer 110 and the chip 150 to form a protective layer 151.
Specifically, referring to fig. 10 in combination, after the upper board is completed, a protective material, such as resin, is filled on the molding transition layer 110 to form a protective layer 151 covering the plurality of chips 150, so as to protect the chips 150.
After the chip 150 is mounted or the protective layer 151 is prepared, a cutting process is performed to cut along the mold adapter layer 110 to form a single package structure, so as to complete the integration of the chip 150.
In summary, the present embodiment provides a method for manufacturing a three-dimensional package structure, which includes molding a carrier 200 having molding pillars 210 to form a molding transition layer 110, peeling off the carrier 200 to form molding grooves 111 on the molding transition layer 110, electroplating conductive pillars 113 in the molding grooves 111, and finally completing the wiring and chip mounting 150. Compared with the prior art, the forming groove 111 is formed on the mold pressing adapting layer 110 after the carrier plate 200 is peeled off, and the traditional slotting/punching technology is avoided, so that the increase of warpage or the cracking phenomenon is avoided, and the reliability of the carrier plate is greatly improved. Meanwhile, the stripping difficulty is relatively low, and the carrier plate 200 is used as a mold, so that the high-cost technologies such as etching grooving, laser grooving and the like are avoided, and the preparation cost and the process difficulty are greatly reduced. The structure and the method provided by the invention have the advantages of simple process, low cost and the like, and are more suitable for the future packaging mode and structure of multi-chip 150 integration.
Second embodiment
With continued reference to fig. 10, the present embodiment provides a three-dimensional package structure 100, which is prepared by the method for preparing a three-dimensional package structure according to the first embodiment.
The three-dimensional package structure 100 provided in this embodiment includes a molding adapter layer 110, a wiring combination layer 130 and a chip 150, wherein the molding adapter layer 110 is provided with a conductive pillar 113, the conductive pillar 113 penetrates through the molding adapter layer 110 and extends to two side surfaces of the molding adapter layer 110, the wiring combination layer 130 is disposed on one side surface of the molding adapter layer 110 and is electrically connected to the conductive pillar 113, the chip 150 is disposed on the other side surface of the molding adapter layer 110 and is electrically connected to the conductive pillar 113, and the chip 150 is electrically connected to the wiring combination layer 130 through the conductive pillar 113.
In this embodiment, a plurality of conductive pillars 113 are formed in the molding adapter layer 110 by electroplating, and a plurality of chips 150 are simultaneously formed, and a plurality of chips 150 with conductive bumps are attached to the surface of the molding adapter layer 110, so that the chips 150 and the conductive pillars 113 can be correspondingly connected. The molding transition layer 110 may be molded by using the carrier plate 200 with the molding protrusion 210 as a mold, so as to directly form the molding groove 111 on the molding transition layer 110, and then form the conductive pillar 113 in the molding groove 111 by electroplating, thereby simplifying the process and reducing the cost.
It should be noted that in the present embodiment, the conductive pillars 113 are metal pillars and are formed by an electroplating process, and two ends of each conductive pillar 113 respectively penetrate through the surface of the molding adapter layer 110, so as to facilitate electrical connection.
In the present embodiment, the wiring combination layer 130 includes a wiring conductive layer 131 and a dielectric layer 133, wherein the wiring conductive layer 131 contacts the conductive pillar 113, the dielectric layer 133 covers the wiring conductive layer 131, an opening is formed in the dielectric layer 133 by a slot, a pad is formed in the opening, and a solder ball 135 is formed by ball-planting on the pad.
Further, the three-dimensional package structure 100 further includes a substrate 170, where the substrate 170 is provided with solder joints, and the wiring combination layer 130 is attached to the substrate 170, so that the solder balls 135 are soldered to the solder joints correspondingly, thereby achieving electrical connection between the wiring combination layer 130 and the substrate 170.
In the three-dimensional package structure 100 provided by this embodiment, the molding adapter layer 110 is formed by molding the carrier 200 with the molding pillars 210, and then the carrier 200 is peeled off, so as to form the molding grooves 111 on the molding adapter layer 110, and then the conductive posts 113 are formed in the molding grooves 111 by electroplating, thereby completing the wiring and mounting of the chip 150. By stripping the carrier 200, the molding groove 111 is formed on the mold-pressing transition layer 110, and the conventional grooving/punching technology is avoided, so that the increase of warpage or the cracking phenomenon is avoided, and the reliability is greatly improved. Meanwhile, the stripping difficulty is relatively low, and the carrier plate 200 is used as a mold, so that the high-cost technologies such as etching grooving, laser grooving and the like are avoided, and the preparation cost and the process difficulty are greatly reduced.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A preparation method of a three-dimensional packaging structure is characterized by comprising the following steps:
providing a carrier plate with a forming convex column;
carrying out mould pressing on the carrier plate to form a mould pressing transfer layer;
stripping the carrier plate to form a forming groove corresponding to the forming convex column on one side surface of the mould pressing transfer layer;
electroplating in the forming groove to form a conductive column;
forming a wiring combination layer on one side surface of the mould pressing switching layer;
a chip is pasted on the surface of the other side of the mould pressing switching layer;
the wiring combination layer is electrically connected with the conductive column, and the conductive column is electrically connected with the chip.
2. The method for preparing a three-dimensional package structure according to claim 1, wherein before the step of surface mounting a chip on the other side of the mold adapter layer, the method further comprises:
and thinning the molding adapter layer on the other side surface of the molding adapter layer to expose the conductive posts.
3. The method for manufacturing a three-dimensional package structure according to claim 2, wherein the step of forming a wiring combination layer on one side surface of the mold-pressing via layer comprises:
forming a wiring conductive layer in electrical contact with the conductive column on the other side surface of the mold pressing transfer layer;
covering a dielectric layer on the wiring conductive layer;
and forming a pad electrically connected with the wiring conductive layer on the dielectric layer.
4. The method for manufacturing a three-dimensional package structure according to claim 1, wherein after the step of forming a wiring combination layer on one side surface of the mold via layer, the method further comprises:
and carrying out ball planting on the wiring combination layer to form a solder ball.
5. The method for preparing the three-dimensional packaging structure according to claim 1, wherein the step of attaching a chip to the other side surface of the mold adapter layer comprises:
attaching a plurality of chips with conductive bumps on the other side surface of the die pressing switching layer in a hot pressing fusion mode;
the conductive bump is correspondingly connected with the conductive column.
6. The method of claim 1, wherein the step of providing a carrier with a molding post comprises:
providing a metal carrier plate;
and slotting at intervals on the metal carrier plate to form a plurality of forming convex columns.
7. The method for preparing the three-dimensional packaging structure according to claim 1, wherein after the step of attaching a chip to the other side surface of the mold adapter layer, the method further comprises:
mounting the wiring combination layer on a substrate;
wherein the substrate is electrically connected to the wiring combination layer.
8. The method for manufacturing a three-dimensional package structure according to claim 7, wherein after the step of mounting the wiring combination layer on a substrate, the method further comprises:
and filling a protective material between the molding transfer layer and the chip to form a protective layer.
9. A three-dimensional encapsulation structure formed by the method for manufacturing a three-dimensional encapsulation structure according to any one of claims 1 to 8, comprising:
the die pressing switching layer is internally provided with a conductive column which penetrates through the die pressing switching layer;
the wiring combination layer is arranged on one side surface of the mould pressing switching layer;
the chip is arranged on the other side surface of the mould pressing switching layer;
the wiring combination layer is electrically connected with the conductive column, and the conductive column is electrically connected with the chip.
10. The three-dimensional package structure of claim 9, further comprising a substrate, wherein the wiring assembly is attached to the substrate, and wherein the substrate is electrically connected to the wiring assembly.
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| CN202210234833.9A CN114334810A (en) | 2022-03-11 | 2022-03-11 | Preparation method of three-dimensional packaging structure and three-dimensional packaging structure |
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| CN202210234833.9A CN114334810A (en) | 2022-03-11 | 2022-03-11 | Preparation method of three-dimensional packaging structure and three-dimensional packaging structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150137384A1 (en) * | 2013-11-19 | 2015-05-21 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
| CN108174615A (en) * | 2015-09-29 | 2018-06-15 | 大日本印刷株式会社 | Wiring structure body and its manufacturing method, semiconductor device, multi-layer circuit structure body and its manufacturing method, substrate for carrying semiconductor components, the forming method of pattern structure, the manufacturing method of the mold of coining and its manufacturing method, imprint mold group and multi-layer wire substrate |
| CN109308951A (en) * | 2017-07-28 | 2019-02-05 | Tdk株式会社 | Conductive board, electronic device and display device |
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- 2022-03-11 CN CN202210234833.9A patent/CN114334810A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150137384A1 (en) * | 2013-11-19 | 2015-05-21 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
| CN108174615A (en) * | 2015-09-29 | 2018-06-15 | 大日本印刷株式会社 | Wiring structure body and its manufacturing method, semiconductor device, multi-layer circuit structure body and its manufacturing method, substrate for carrying semiconductor components, the forming method of pattern structure, the manufacturing method of the mold of coining and its manufacturing method, imprint mold group and multi-layer wire substrate |
| CN109308951A (en) * | 2017-07-28 | 2019-02-05 | Tdk株式会社 | Conductive board, electronic device and display device |
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