CN114334676B - Packaging method of power chip and corresponding packaging structure - Google Patents
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Abstract
The application provides a packaging method and a corresponding packaging structure of a power chip, wherein the packaging method comprises the following steps: providing a buried substrate, wherein at least a power chip is buried in the buried substrate, and the power chip is electrically connected to the buried substrate; the top of the embedded substrate is provided with a plurality of first pins; providing at least one coil; placing the at least one coil on top of the buried substrate and soldering both ends of each coil to corresponding first pins, one end of each coil being electrically connected to the power supply in/chip through the corresponding first pins; and forming a magnetic package body above the embedded substrate, wherein the magnetic package body covers the top of the embedded substrate, and the magnetic package body covers the coil and the first pins.
Description
Technical Field
The present application relates to the field of semiconductor packaging technology, and in particular, to a method for packaging a power chip and a corresponding packaging structure.
Background
The power chip belongs to one kind of power management chip, and is widely applied to electronic equipment and systems in various industries such as communication, industry, medical treatment, electric power, rail transit and the like, and plays an important role in providing electric energy for the electronic system and realizing voltage conversion.
With the development of society and the progress of technology, related technologies such as smart cities, smart factories, smart grids, automatic driving, artificial intelligence and the like are emerging, corresponding electronic system functions become more and more complex, system power is improved, but system volume gradually tends to be miniaturized and intelligent, and the power density of a power management chip for supplying power to the electronic system is also required to be improved continuously.
The power chip in the prior art is limited by a packaging structure, the internal space of the chip is difficult to maximally and effectively utilize, particularly, the space utilization rate of internal magnetic conduction type materials is low, the power density is difficult to improve, and the heat radiation performance of the system is reduced and the efficiency is also reduced due to the volume limitation caused by miniaturization along with the miniaturization trend of chip design.
Therefore, how to increase the power density of the power chip in a limited space has become a technical problem to be solved in the industry.
Disclosure of Invention
The application provides a packaging method and a packaging structure of a power chip, which are used for improving the power density of the power chip and solving the problem of low efficiency of the power chip.
According to a first aspect of the present application, there is provided a packaging method of a power chip, the method comprising the steps of:
providing a buried substrate, wherein at least a power chip is buried in the buried substrate, and the power chip is electrically connected to the buried substrate; the top of the embedded substrate is provided with a plurality of first pins;
providing at least one coil;
placing the at least one coil on the top of the embedded substrate, and welding two ends of each coil to corresponding first pins, wherein one end of each coil is electrically connected with the power chip through the corresponding first pins; and forming a magnetic package body above the embedded substrate, wherein the magnetic package body covers the top of the embedded substrate, and the magnetic package body covers the coil and the first pins.
Optionally, the forming the magnetic package above the buried substrate specifically includes:
placing the embedded substrate welded with the coil in a concave cavity mold, forming a specific space between the upper side of the embedded substrate and the concave cavity mold, injecting a liquid magnetic conduction material into the specific space, and then solidifying to form a magnetic package;
and taking out the concave cavity die.
Optionally, after the cavity mold is taken out, the method further comprises:
the embedded substrate after the formation of the magnetic package is heated and then cooled and solidified for the second time.
Optionally, the method further comprises cutting the embedded substrate according to a preset size to form a single finished product.
According to a second aspect of the present application, there is provided a power chip package structure, prepared by the above power chip package method, the power chip package structure comprising:
a buried chip structure and a magnetic component disposed over the buried chip structure; wherein:
the embedded chip structure comprises: a buried substrate, and a power chip disposed in the buried substrate; the power chip is electrically connected to the embedded substrate;
the magnetic assembly includes: a magnetic package and at least one coil; the top of the embedded substrate is provided with a plurality of first pins, and two ends of each coil are respectively and electrically connected to the corresponding first pins; the coils and the first pins are all coated in the magnetic package body, and one end of each coil is electrically connected with the power chip through the corresponding first pin.
Optionally, the magnetic package is formed by injecting a liquid magnetic conductive material into a specific space above the embedded substrate and then solidifying the liquid magnetic conductive material.
Optionally, the embedded chip structure further includes an electronic component, where the electronic component is disposed in the embedded substrate and is electrically connected to the embedded substrate.
Optionally, a plurality of second pins are disposed at the bottom of the embedded substrate, and the power chip is electrically connected with the embedded substrate through the corresponding second pins.
Optionally, the electronic component includes a component pin, and the component pin is electrically connected to a corresponding second pin.
Optionally, the electronic component is a resistor or a capacitor.
Optionally, the number of the power supply chips is at least one, and each power supply chip corresponds to one coil.
According to the packaging method of the power supply chip, the traditional discrete inductance device is changed into the traditional discrete inductance device, the coil is directly prepared at the top of the embedded substrate, the magnetic packaging body is formed above the embedded substrate, and covers the coil and the first pin which is arranged at the top of the embedded substrate and is used for connecting the coil, so that the on-chip inductance is formed; therefore, the effective utilization space inside the power chip is greatly improved, the power density, the system efficiency and the heat dissipation performance of the power chip are comprehensively improved, and the whole power system works more stably and reliably.
In the alternative scheme of the application, the coil is directly packaged by the magnetic packaging body, and the magnetic packaging body directly covers the embedded substrate, so that the partial thermal resistance from the coil shell to the plastic packaging shell in the plastic packaging body of the traditional discrete inductor is eliminated, the heat dissipation thermal resistance of the magnetic device is reduced, the surface area of the coil for directly dissipating heat is increased, and the overall heat dissipation effect is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art structure;
FIG. 2 is a flow chart of a power chip packaging method of the present application;
FIG. 3 is a flow chart of forming a magnetic package according to an embodiment of the application;
FIG. 4 is a top view of a single coil structure in an embodiment of the application;
FIG. 5 is a schematic cross-sectional view taken along line A-A of FIG. 4;
FIG. 6 is a bottom view of the monocoil structure of FIG. 4;
FIG. 7 is a schematic diagram of a dual coil structure in an embodiment of the application;
FIG. 8 is a schematic cross-sectional view taken along B-B of FIG. 7;
reference numerals illustrate:
110-plastic package;
111-inductance;
112-pins;
1-embedded chip structure;
11-a buried substrate;
12-a power chip;
13-a second pin;
131-power chip pins;
132—electronic component pins;
14-electronic components;
2-magnetic assembly;
21-coil;
22-magnetic package;
23-a first pin;
A-A: cutting;
B-B: and (5) cutting.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical scheme of the application is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Referring to fig. 1, fig. 1 is a package structure of a conventional power chip, as shown in fig. 1, the package structure of the conventional power chip includes:
a substrate, wherein a power supply chip is arranged in the substrate;
the inductor 111 is an independently packaged device, and specifically comprises an inductor winding, a magnetic material for wrapping the inductor winding and a packaging shell, wherein the inductor winding and the magnetic material are packaged in the packaging shell; pins 112 of the inductor are led out from two ends of the packaging shell; the pins 112 of the inductor are used for being electrically connected with the substrate;
a plastic package 110 for packaging the inductor 111 onto the substrate.
The applicant discovers that the periphery of an inductance winding of the existing packaging structure of the power chip needs to be coated with magnetic materials through analysis and research on the existing packaging structure of the power chip, the packaging shell is used as a primary element for packaging, and the inductor needs to be packaged secondarily by adopting a packaging body after being electrically connected to a substrate, so that the inductor and the substrate form a whole. This results in a significant space waste due to the large proportion of space occupied by the inductor in the overall structure. Therefore, how to save the space occupied by the inductor is important to improve the space utilization rate of the packaging structure of the whole power chip.
The power chip referred to in the present application is also called a power die (die).
The applicant has carried out a series of designs about how to reduce the occupation space of the inductor, and has obtained the technical solution of the present application.
Referring to fig. 2, and referring to fig. 4 to 8, an embodiment of the application provides a method for packaging a power chip, which includes the following steps:
s11: a buried substrate 11 is provided.
As shown in fig. 4 to 6, a plurality of first pins 23 are disposed on top of the buried substrate 11; and at least the power chip 12 is embedded in the embedded substrate 11, and the power chip 12 is electrically connected to the embedded substrate 11.
In addition, as a specific embodiment, a plurality of second pins 13 are disposed at the bottom of the buried substrate 11, and the power chip 12 is electrically connected to the corresponding second pins 13. In practice, the power chip 12 has a power chip pin 132, and the power chip 12 is electrically connected to the buried substrate 11 by electrically connecting the power chip pin 132 to the corresponding second pin 13.
As a further preferred embodiment, the second pins 13 may be copper pins, for example, and the power chip pins 132 may be first electroplated with copper and then combined with the copper pins to make electrical connection. It should be understood, of course, that the application is not limited thereto and that other forms of electrical connection are within the scope of the application without departing from the spirit of the application.
In addition to the embedded power chip 12, other electronic components 14 may be optionally embedded in the embedded substrate 11, and in a specific embodiment, the electronic components 14 may be resistors or capacitors, for example. Wherein the electronic component 14 is also electrically connected to the buried substrate 11, for example, the electronic component 14 has an electronic component pin 132, and the electronic component 14 is electrically connected to the buried substrate 11 by connecting the electronic component pin 132 to the corresponding second pin 13.
Wherein the number of electronic components 14 may be one or other values.
The pins provided on the bottom of the embedded substrate 11 for connection to the power chip 12 and the electronic component 14 are collectively referred to as first pins 13. The power chip 12 and the electronic component 14 are electrically connected through the corresponding second pins 13, for example, one pin of the electronic component 14 is connected to one second pin 13, and the second 23 pin is simultaneously connected with one pin of the power chip 12, so as to realize electrical connection.
S12: at least one coil 21 is provided.
The coil 21 may be a cylindrical wire-wound coil, a planar wire-wound coil, or a coil made by winding or processing. It should be understood, of course, that the application is not limited thereto and that any form of coil is within the scope of the application without departing from the spirit of the application.
S13: the coils 21 are placed on top of the buried substrate 11, and both ends of each coil 21 are soldered to and electrically connected with the corresponding first pins 23, and one end of each coil 21 is electrically connected with the corresponding power chip 12 through the corresponding first pin 23, respectively.
Wherein the number of power chips 12 may be, for example, one or two or other numbers. The number of coils 13 may likewise be one or two or another number.
In one embodiment, the number of power chips 12 is one, and the number of coils 21 is one, as shown in fig. 4 and 5. The two ends of the coil 21 are electrically connected to corresponding first pins 23, and the two first pins 23 are electrically connected to corresponding second pins 13 at the bottom of the embedded substrate. One of the two second pins 13 (the pin on the left side of fig. 5) is electrically connected to the power chip 12, and the other pin (the pin on the right side of fig. 5) is used for connection with other elements or as an output. In actual operation, the following manner may be specifically adopted to connect the two ends of the coil 21 to the corresponding first pins 23: referring to fig. 5, firstly, solder paste is printed on the corresponding first pins 23, the coils 21 are placed on the corresponding first pins 23 printed with the solder paste in rows by a chip mounter, then the first pins 23 placed with the solder paste and the corresponding coils 21 are placed in a reflow soldering furnace, the solder paste on the first pins 23 is melted and cooled under the action of the reflow soldering furnace, and finally, the coils 21 are firmly connected with the embedded substrate 11 through the corresponding first pins 23 by soldering tin, and electric conduction is realized.
Of course, the specific welding manner between the two ends of the coil 21 and the first pin is not limited thereto, and other manners of electrically connecting the coil to the first pin are all within the scope of the present application.
In another embodiment, the number of the power chips 12 is two, and the number of the coils 21 is two, as shown in fig. 7 and 8. In fig. 7 and 8, each power chip 12 corresponds to one coil 21, specifically, one end of the coil 21 is connected to a corresponding second pin through a corresponding first pin 23, and is electrically connected to the corresponding power chip 12; the other end of the coil 21 is connected to a corresponding second pin through a corresponding first pin 23, which is used for connection with other elements or as an output.
The specific welding manner between the two ends of the coil 21 and the first pin 23 is the same as the foregoing manner, and will not be described herein.
Of course, it should be appreciated that the above two embodiments of the correspondence between the power chips and the coils are merely examples of the present application, and the present application is not limited thereto, and specifically, the number of the power chips and the coils in the present application may also be other values, and the correspondence may also be other correspondence, for example, the number of the power chips may be 3 or other values, and the number of the coils may be 3 or other values. And the corresponding relation between the power chip and the coils can be that one power chip corresponds to two or more coils.
S14: a magnetic package 22 is formed over the buried substrate, the magnetic package 22 covers the top of the buried substrate 11, and the magnetic package 22 encapsulates the coil 21 and the first leads 23.
It can be seen that, compared with the prior art shown in fig. 1, the packaging method of the power supply chip provided by the application is characterized in that the traditional discrete inductor device is changed into a coil directly prepared on the top of the embedded substrate 11, a magnetic packaging body 22 is formed above the embedded substrate 11, and the magnetic packaging body 22 covers the coil 21 and a first pin 23 arranged on the top of the embedded substrate and used for connecting the coil, so that an on-chip inductor is formed; compared with the prior art, firstly, the package housing of the discrete inductance element is omitted, and secondly, the package housing of the whole power chip is directly made of magnetic materials, so that the plastic package body 110 in the prior art is omitted. Therefore, the effective utilization space inside the power chip is greatly improved, the power density, the system efficiency and the heat dissipation performance of the power chip are comprehensively improved, and the whole power system works more stably and reliably.
As a preferred embodiment, referring to fig. 3, the forming a magnetic package above a buried substrate in step S14 specifically includes:
s141: placing the embedded substrate 11 welded with the coil 21 in a cavity mold, so that a specific space is formed between the upper side of the embedded substrate 11 and the cavity mold, and injecting a liquid magnetic conductive material into the specific space for curing to form a magnetic package 22;
s142: and taking out the concave cavity die.
S143: the buried substrate 11 after the formation of the magnetic package 22 is heated and then cooled and solidified for the second time.
In one example, the buried substrate 11 after the formation of the magnetic package 22 is heated by an oven and then cooled and solidified, and the buried substrate 11 after the formation of the magnetic package 22 is heated by an oven and then cooled and solidified.
It should be appreciated, of course, that the heating by the oven is merely an example of the present application, and the heating method of the present application is not limited thereto, and other heating modes are within the scope of the present application as long as they do not depart from the spirit of the present application.
And, as an alternative, the step S143 may be followed by the steps of:
s144: cutting the embedded substrate according to a preset size to form a single finished product.
The application also provides a packaging structure of the power chip, which is prepared by the packaging method of the power chip, and the structure is shown in figures 4 to 8; wherein fig. 4 to 6 show a structure including a power chip and a coil; fig. 7 to 8 show a structure including two power chips and two coils.
As shown in fig. 4 to 6, the package structure of the power chip includes:
a buried chip structure 1 and a magnetic component 2 arranged above the buried chip structure; wherein:
the embedded chip structure 1 includes: a buried substrate 11, and a power chip 12 provided in the buried substrate 11; the power chip 12 is electrically connected to the buried substrate 11.
The magnetic assembly 2 comprises: a magnetic package 22 and a coil 21; two first pins 23 are arranged on the top of the embedded substrate, and two ends of the coil 21 are respectively and electrically connected to the corresponding first pins 23; the coils 21 and the first pins 23 are all wrapped in the magnetic package 22, and one end of each coil 21 is electrically connected with the power chip 12 through the corresponding first pin 23.
Specifically, a plurality of second pins 13 are disposed at the bottom of the embedded substrate 11, and the power chip 12 is electrically connected to the embedded substrate 11 through the corresponding second pins 13. And the second pins 13 are electrically connected to the corresponding first pins 23, for example, through holes penetrating the bottom and the top of the embedded substrate 11 are formed in the embedded substrate, the through holes connect the second pins to the corresponding first pins, and conductive materials are filled in the through holes to electrically connect the second pins to the corresponding first pins.
As an alternative embodiment, other electronic components 14 are embedded in the embedded substrate 11, and as a specific embodiment, the electronic components 14 may be, for example, resistors or capacitors. Wherein the electronic component 14 is also electrically connected to the buried substrate 11, for example, the electronic component 14 has an electronic component pin 132, and the electronic component 14 is electrically connected to the buried substrate 11 by connecting the electronic component pin 132 to the corresponding first pin 13.
Wherein the number of electronic components 14 may be one or other values.
The pins provided on the bottom of the embedded substrate 11 for connection to the power chip 12 and the electronic component 14 are collectively referred to as second pins 13. The power chip 12 and the electronic component 14 are electrically connected through the corresponding second pins 13, for example, one pin of the electronic component 14 is connected to one second pin 13, and the first pin is simultaneously connected with one pin of the power chip 12, so that the electrical connection is realized.
The structure including two power chips and two coils shown in fig. 7 to 8, in which each coil 21 corresponds to one power chip 12, is similar to the structure including one power chip and one coil described above, and will not be described again.
The embedded substrate 11 can shorten the line length of the components, improve the electrical characteristics, increase the effective packaging area of the printed circuit board, reduce a large number of soldering points on the surface of the printed circuit board, and improve the packaging reliability.
In the present application, the material of the magnetic package 22 is a magnetically permeable material, and the magnetic package is formed by injecting a liquid magnetically permeable material into a specific space above the embedded substrate and then curing.
In a specific embodiment, for example: the Buck system-level power chip based on the Buck circuit structure with the packaging size of 2.5mm multiplied by 1.2mm can be selected from optimal magnetic elements in the market at present, and the coil size in the power chip with the packaging size is 2.0mm multiplied by 1.6mm multiplied by 0.8mm, and the inductance value is 0.47 mu H, the saturated current is 4.5A, and the DCR (internal resistance of a coil device) is 28mΩ.
In the packaging structure, the coil is directly packaged by the magnetic packaging body, so that the overall optimization of the coil parameters can be realized according to the simulation result. Namely, in a Buck-type system-in-chip based on a Buck circuit structure having a package size of 2.5mm×2.5mm×1.2mm, the size of the coil can be increased to 2.5mm×2.5mm×1mm, and accordingly, the inductance value thereof is 0.56 μH, the saturation current is 6A, and the DCR (internal resistance of the coil former) is 20mΩ.
Under the same conditions of current, voltage and the like, the internal resistance of the coil is reduced from original 28mΩ to 20mΩ according to the formulaIt can be obtained that the lost power of the power supply is +.>And the efficiency of the power system chip is improved by reducing the power system chip.
The saturation current of the coil is increased from 4.5A to 6A, and the power density of the power supply system chip is also increased by 25% under the same condition.
In addition, the inductance value of the coil can be increased from 0.47 mu H to 0.56 mu H, according to the formula:
the electric wave ripple output by the power supply system is inversely proportional to the inductance value of the coil, namely, along with the increase of the inductance value of the coil, the voltage ripple output by the power supply system is reduced, so that the power supply system works more stably and reliably.
Referring to fig. 1, the top of the conventional power chip further includes a plastic package 110, and the heat conduction effect of the magnetically conductive material is far greater than that of the conventional plastic package 110, in the present application, since the coil is directly encapsulated by the magnetically conductive material and the magnetically conductive material is directly covered over the embedded substrate, the thermal resistance from the coil housing to the plastic package housing in the conventional plastic package 110 is directly eliminated, the heat dissipation thermal resistance of the magnetic device is reduced, the surface area of the coil for direct heat dissipation is increased, and the overall heat dissipation effect is effectively improved.
The electrical connection method according to the present application is not limited to this, and other electrical connection methods are within the scope of the present application as long as they do not depart from the spirit of the present application.
The application provides a packaging structure of a power chip and a packaging method thereof, wherein a coil is placed at the top of a buried substrate, a magnetic packaging body is formed above the buried substrate, and the magnetic packaging body covers the top of the buried substrate, so that the effective utilization space inside the power chip is greatly improved, the power density, the system efficiency and the heat dissipation performance of the power chip are comprehensively improved, and the whole power system works more stably and reliably.
In the alternative scheme of the application, the coil is directly packaged by the magnetic packaging body, and the magnetic packaging body directly covers the embedded substrate, so that the partial thermal resistance from the coil shell to the plastic packaging shell in the traditional plastic packaging body is eliminated, the heat dissipation thermal resistance of the magnetic device is reduced, the surface area of the coil for direct heat dissipation is increased, and the whole heat dissipation effect is effectively improved.
In the description of the present specification, reference to the description of the terms "one embodiment," "one embodiment," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solution of the present application, and not limiting thereof; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (11)
1. A method of packaging a power chip, the method comprising the steps of:
providing a buried substrate, wherein at least a power chip is buried in the buried substrate, and the power chip is electrically connected to the buried substrate; the top of the embedded substrate is provided with a plurality of first pins;
providing at least one coil, wherein the coil comprises a coil made of planar wire-wound type;
placing the at least one coil on the top of the embedded substrate, and welding two ends of each coil to corresponding first pins, wherein one end of each coil is electrically connected with the power chip through the corresponding first pins; and a magnetic package body is directly formed above the embedded substrate, the magnetic package body covers the whole top of the embedded substrate, and the magnetic package body covers the coil and the first pins.
2. The method of packaging a power chip according to claim 1, wherein forming a magnetic package over the buried substrate specifically comprises:
placing the embedded substrate welded with the coil in a concave cavity mold, forming a specific space between the upper side of the embedded substrate and the concave cavity mold, injecting a liquid magnetic conduction material into the specific space, and then solidifying to form a magnetic package;
and taking out the concave cavity die.
3. The method of packaging a power chip of claim 2, further comprising, after removing the cavity mold:
the embedded substrate after the formation of the magnetic package is heated and then cooled and solidified for the second time.
4. A method for packaging a power chip according to claim 2 or 3,
and cutting the embedded substrate according to a preset size to form a single finished product.
5. A power chip package structure prepared by the power chip package method according to any one of claims 1 to 4, wherein the power chip package structure comprises:
a buried chip structure and a magnetic component disposed over the buried chip structure; wherein:
the embedded chip structure comprises: a buried substrate, and a power chip disposed in the buried substrate; the power chip is electrically connected to the embedded substrate;
the magnetic assembly includes: the magnetic packaging body and at least one coil, wherein the coil comprises a coil made of planar wire winding; the top of the embedded substrate is provided with a plurality of first pins, and two ends of each coil are respectively and electrically connected to the corresponding first pins; the coils and the first pins are all coated in the magnetic package body, and one end of each coil is electrically connected with the power chip through the corresponding first pin.
6. The package structure of claim 5, wherein the magnetic package is formed by injecting a liquid magnetically permeable material into a specific space above the embedded substrate and then curing.
7. The package structure of a power chip as claimed in claim 5, wherein,
the embedded chip structure further comprises an electronic component, wherein the electronic component is arranged in the embedded substrate and is electrically connected with the embedded substrate.
8. The package structure of the power chip according to claim 7, wherein a plurality of second pins are disposed at a bottom of the embedded substrate, and the power chip is electrically connected to the embedded substrate through the corresponding second pins.
9. The package structure of a power chip as claimed in claim 8, wherein,
the electronic component includes component pins electrically connected to corresponding second pins.
10. The package structure of a power chip according to claim 8, wherein the electronic component is a resistor or a capacitor.
11. The package structure of power chips as defined in claim 5, wherein said number of power chips is at least one, each of said power chips corresponding to at least one coil.
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| CN202111584935.5A CN114334676B (en) | 2021-12-22 | 2021-12-22 | Packaging method of power chip and corresponding packaging structure |
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| CN114334676B true CN114334676B (en) | 2023-11-21 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103383891A (en) * | 2012-05-04 | 2013-11-06 | 陈建兴 | Inductor manufacturing method and inductor |
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| TWI376774B (en) * | 2007-06-08 | 2012-11-11 | Cyntec Co Ltd | Three dimensional package structure |
| US7868431B2 (en) * | 2007-11-23 | 2011-01-11 | Alpha And Omega Semiconductor Incorporated | Compact power semiconductor package and method with stacked inductor and integrated circuit die |
| CN110010509B (en) * | 2018-01-05 | 2023-10-20 | 光宝新加坡有限公司 | Double-lead-frame magnetic coupling packaging structure and manufacturing method thereof |
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| CN103383891A (en) * | 2012-05-04 | 2013-11-06 | 陈建兴 | Inductor manufacturing method and inductor |
| CN104135139A (en) * | 2013-05-03 | 2014-11-05 | 胜美达电机（香港）有限公司 | Power supply module |
| CN109585149A (en) * | 2017-09-26 | 2019-04-05 | 绿点高新科技股份有限公司 | The preparation method and its product of inductor |
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