CN111477551A - Integrally formed electronic device and manufacturing method thereof - Google Patents

Integrally formed electronic device and manufacturing method thereof Download PDF

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Publication number
CN111477551A
CN111477551A CN202010237941.2A CN202010237941A CN111477551A CN 111477551 A CN111477551 A CN 111477551A CN 202010237941 A CN202010237941 A CN 202010237941A CN 111477551 A CN111477551 A CN 111477551A
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China
Prior art keywords
integrated circuit
circuit
frame
electronic device
integrally formed
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Withdrawn
Application number
CN202010237941.2A
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Chinese (zh)
Inventor
张程龙
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Huayuan Zhixin Semiconductor Shenzhen Co ltd
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Huayuan Zhixin Semiconductor Shenzhen Co ltd
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Priority to CN202010237941.2A priority Critical patent/CN111477551A/en
Publication of CN111477551A publication Critical patent/CN111477551A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses an integrally formed electronic device and a manufacturing method thereof. The method comprises the following steps: connecting a first integrated circuit to a circuit frame having a first element; connecting a second element to the first element over the first integrated circuit to form an inductor coil around the first integrated circuit; the inductor coil is encapsulated with the first integrated circuit using a magnetic material. The device comprises a circuit frame, a first integrated circuit and a second element; the circuit frame is provided with a first element; the first integrated circuit is located above the first element; the second element is connected with the first element to form an inductance coil surrounding the first integrated circuit; further comprising a magnetic material encapsulating the inductor coil with the first integrated circuit. The application not only can further reduce the product size after the encapsulation, but also can increase the inductance of the inductor and improve the heat dissipation effect.

Description

Integrally formed electronic device and manufacturing method thereof
Technical Field
The present disclosure relates to circuit packaging technologies, and particularly to an integrally formed electronic device and a method for manufacturing the same.
Background
With the development of electronic technology, people have increasingly high requirements on high power density of circuits. In the context of a high power density DC/DC converter, an integrated device of the inductor and the control chip is used.
Inductance and control chip's integrated into one piece generally adopts the chip setting to realize outside the inductance in the existing market: the inductor stack is pre-formed on the control chip or mounted in parallel on the substrate, and finally EPOXY resin is molded to cast the inductor and the control chip together to form an integrated device. The integrated device obtained in this way not only has small inductance but also has large volume.
The above background disclosure is only for the purpose of assisting in understanding the inventive concepts and technical solutions of the present application and does not necessarily pertain to the prior art of the present application, and should not be used to assess the novelty and inventive step of the present application in the absence of explicit evidence to suggest that such matter has been disclosed at the filing date of the present application.
Disclosure of Invention
The application provides an integrated electronic device and a manufacturing method thereof, which can further improve power density, increase efficiency and reduce the size of a packaged product, so that the product is small in size, and the inductance of an inductor can be increased and the heat dissipation effect can be improved.
In a first aspect, the present application provides a method for manufacturing an integrally formed electronic device, including:
a1, connecting a first integrated circuit with a circuit frame having a first element such that the first integrated circuit is located above the first element;
a2, connecting a second element with the first element above the first integrated circuit to form an inductance coil surrounding the first integrated circuit;
a3, encapsulating the inductance coil with the first integrated circuit by using a magnetic material.
In some preferred embodiments, said a1 specifically comprises: fixedly connecting the first integrated circuit with a circuit frame having a first element with a non-conductive bonding material and connecting electrodes of the first integrated circuit with electrodes of the circuit frame with metal wires such that the first integrated circuit is located above the first element.
In some preferred embodiments, the first integrated circuit is a flip-chip integrated circuit; a solder ball is arranged above the copper column of the flip integrated circuit;
the A1 specifically comprises: connecting the solder balls of the flip-chip integrated circuit with electrodes of a circuit frame having a first element such that the flip-chip integrated circuit is located above the first element.
In some preferred embodiments, the circuit frame is a lead frame with only a front side half-etched; the first element is a conductive lead;
and the method also comprises A4, and performing back half etching on the lead frame after the package is finished so as to form a complete circuit.
In some preferred embodiments, the second element comprises in particular form a connecting bridge wire and a bridge conductor.
In a second aspect, the present application provides an integrally molded electronic device including a circuit frame, a first integrated circuit, and a second element;
the circuit frame is provided with a first element;
the first integrated circuit is connected with the circuit frame and is positioned above the first element;
the second element is located above the first integrated circuit;
the second element is connected with the first element to form an inductance coil surrounding the first integrated circuit;
further comprising a magnetic material encapsulating the inductor coil with the first integrated circuit.
In some preferred embodiments, the specific form of the circuit frame includes a lead frame and a printed circuit board.
In some preferred embodiments, the second element comprises in particular form a connecting bridge wire and a bridge conductor.
In some preferred embodiments, the bridge conductor is a copper bridge.
In some preferred embodiments, the first element is a conductive lead.
In some preferred embodiments, the first integrated circuit is a control integrated circuit.
In a third aspect, the present application provides an article comprising the above-described integrally molded electronic device.
Compared with the prior art, the beneficial effects of the embodiment of the application are as follows:
the circuit frame and the second element are combined to form a coil to realize the inductance function, so that the first integrated circuit is arranged in the inductance coil. The inductor coil and the first integrated circuit are encapsulated together by using a magnetic material and are directly molded, namely, a prefabricated inductor is not arranged; the inductor core is outside and the first integrated circuit and the inductor coil are inside. The power density can be further improved, the efficiency is increased, the size of the packaged product is reduced, the size of the product is small, the inductance of the inductor can be increased, and the heat dissipation effect is improved.
Drawings
Fig. 1 is a schematic structural diagram of a circuit frame according to a first embodiment of the present application;
FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 illustrates the process of step A1 of the method of fabrication of the first embodiment of the present application;
FIG. 4 is a cross-sectional view taken along line B-B of FIG. 3;
FIG. 5 shows the processes of step A1 and step A2 of the method of making the first embodiment of the present application;
FIG. 6 is a cross-sectional view taken along line C-C of FIG. 5;
FIG. 7 illustrates the process of step A3 of the method of fabrication of the first embodiment of the present application;
FIG. 8 is a cross-sectional view taken along line D-D of FIG. 7;
FIG. 9 is a cross-sectional view taken in the direction E-E of FIG. 7;
FIG. 10 illustrates the process of step A4 of the method of fabrication of the first embodiment of the present application;
FIG. 11 is a cross-sectional view taken in the direction F-F of FIG. 10;
FIG. 12 is a sectional view taken in the direction G-G of FIG. 10;
FIG. 13 illustrates the process of step A5 of the method of fabrication of the first embodiment of the present application;
FIG. 14 is a sectional view taken in the direction H-H in FIG. 13;
FIG. 15 is a cross-sectional view taken along line K-K of FIG. 13;
fig. 16 shows a front side of an integrally formed electronic device of the first embodiment of the present application;
fig. 17 shows the back side of the integrally molded electronic device of the first embodiment of the present application;
fig. 18 is a schematic structural diagram of a circuit frame according to a second embodiment of the present application;
FIG. 19 is a sectional view taken along the line A-A in FIG. 18;
fig. 20 shows a process of printing solder paste of a manufacturing method of a second embodiment of the present application;
FIG. 21 is a bottom view of FIG. 20;
FIG. 22 illustrates the process of step A1 of the method of making a second embodiment of the present application;
FIG. 23 is a sectional view taken in the direction B-B in FIG. 22;
FIG. 24 is a bottom view of FIG. 22;
FIG. 25 illustrates the process of step A2 of the method of making a second embodiment of the present application;
FIG. 26 is a bottom view of FIG. 25;
fig. 27 shows the process of step a3 of the method of making the second embodiment of the present application;
FIG. 28 is a cross-sectional view taken in the direction of C-C in FIG. 27;
FIG. 29 is a cross-sectional view taken in the direction D-D of FIG. 27;
FIG. 30 illustrates the process of step A4 of the method of making the second embodiment of the present application;
FIG. 31 is a cross-sectional view taken in the direction E-E of FIG. 30;
FIG. 32 is a sectional view taken in the direction F-F in FIG. 30;
FIG. 33 illustrates the process of step A5 of the method of making a second embodiment of the present application;
FIG. 34 is a sectional view taken in the direction G-G of FIG. 33;
FIG. 35 is a sectional view taken in the direction H-H in FIG. 33;
fig. 36 shows a front side of an integrally formed electronic device of a second embodiment of the present application;
fig. 37 shows the back surface of an integrally molded electronic device of the second embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the embodiments of the present application more clearly apparent, the present application is further described in detail below with reference to fig. 1 to 37 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or be indirectly connected to the other element. The connection may be for fixation or for circuit connection.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description of the embodiments and simplifying the description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless specifically defined otherwise.
First embodiment
The embodiment provides an integrally formed electronic device and a manufacturing method thereof. Referring to fig. 15, the integrally molded electronic device of the present embodiment includes a first integrated circuit 1, a circuit frame 2, and a second member 3.
The circuit frame 2 is provided with a first element 21.
The first integrated circuit 1 is connected to the circuit frame 2, and the first integrated circuit 1 is located above the first element 21.
The second element 3 is located above the first integrated circuit 1.
The second element 3 is connected to the first element to form an inductor coil 4 (which may also be referred to as an inductor winding) that surrounds the first integrated circuit 1.
The integrated electronic device of the present embodiment further includes a magnetic material 5 encapsulating the inductor coil 4 and the first integrated circuit 1 together.
The present embodiment will be described with reference to a method of manufacturing an integrally formed electronic device according to the present embodiment.
The method for manufacturing an integrally formed electronic device of the present embodiment includes steps a1 to a 5.
Step a1, the first integrated circuit 1 is connected with the circuit frame 2 having the first component 21 such that the first integrated circuit 1 is located above the first component 21.
The first integrated circuit 1 may be various forms of integrated circuits such as a control integrated circuit (which may also be referred to as a control chip), a communication integrated circuit, and a memory integrated circuit.
The first integrated circuit 1 is covered with a metal layer as a shielding layer.
Referring to fig. 1 and 2, the circuit frame 2 may be specifically a lead frame 2A or a Printed Circuit Board (PCB). Wherein, the lead frame 2A is a lead frame with only half-etched front surface; the back surface of the lead frame 2A is not etched. The printed circuit board may be a printed circuit board having two or more layers. The lead frame 2A with only the front surface half-etched will be described as an example.
The first element 21 of the lead frame 2A is a conductive lead 21A, such as a conductive lead formed by etching. The first element 21 is located on the front surface of the lead frame 2A.
Referring to fig. 3 and 4, the first integrated circuit 1 is fixedly connected to the lead frame 2A by a non-conductive bonding material, and specifically, the first integrated circuit 1 is soldered to the lead frame 2A. Wherein the non-conductive bonding material is an insulating welding material; an exemplary non-conductive bonding material is a Film adhesive (DAF) Die Attach Film. Then, referring to fig. 5 and 6, the electrodes of the first integrated circuit 1 are connected with the electrodes of the lead frame 2A with the metal wires 10; illustratively, the metal wire 10 is a fine gold wire, such as a 1mil (thousandths of an inch) gold wire. Thus, the first integrated circuit 1 is located above, specifically directly above, the first element 21, i.e. the conductive lead 21A.
Step a2 is to connect the second element 3 to the first element 21 above the first integrated circuit 1 to form the inductor coil 4 surrounding the first integrated circuit 1.
Referring to fig. 5 and 6, the second member 3 is a connecting bridge wire 3A. The connecting bridge wire 3A is a metal wire, specifically a 2mil copper wire. The second element 3 is connected to the first element 21, i.e. the conductive lead 21A, directly above the first integrated circuit 1 to form the inductor coil 4. Illustratively, the number of the conductive leads 21A and the connecting bridge line 3A is plural; the first connecting bridge wire connects the tail of the first conductive lead wire with the head of the second conductive lead wire, the second connecting bridge wire connects the tail of the second conductive lead wire with the head of the third conductive lead wire, and so on until the inductance coil 4 with two connecting ends is formed. The conductive lead 21A is the lower portion of the inductor 4, and the connecting bridge wire 3A is the upper portion of the inductor 4.
The inductor winding 4 surrounds the first integrated circuit 1. Alternatively, the first integrated circuit 1 is located inside the inductor winding 4.
Step a3, the inductor winding 4 is encapsulated with the first integrated circuit 1 using the magnetic material 5.
Illustratively, the magnetic material 5 is a magnetic powder. A first semi-finished device is obtained through step a1 and step a 2. Referring to fig. 7 to 9, the first semi-finished device is placed in a mold, and then a magnetic powder is added into the mold, so that the magnetic powder encapsulates the inductor coil 4 and the first integrated circuit 1, specifically, the conductive leads 21A, the connecting bridge 3A and the first integrated circuit 1, on the lead frame 2A, and then slowly heated and gradually sintered to form a whole. In this way, a second semi-finished device can be obtained. The encapsulated magnetic material 5 serves as a core of the inductor, and the inductor coil 4 is also encapsulated in the magnetic material.
Step a4, after the package is completed, the lead frame 2A is subjected to back half etching to form a complete circuit.
Since the lead frame 2A is only half-etched on the front side, after the second half-finished device is obtained by magnetic powder encapsulation, referring to fig. 10 to 12, the lead frame 2A is also half-etched on the back side in order to be disconnected to form a complete circuit, thereby obtaining a third half-finished device.
It should be noted that step a4 is optional, and step a4 is not required, for example, if a printed circuit board is used as the circuit frame 2 to fabricate an integrally formed electronic device.
Step A5, sealing and curing.
After the third semi-finished device is obtained through step a4, referring to fig. 13 to 15, the third semi-finished device is sealed, for example, by using a green paint commonly used in the PCB industry, and cured. Thus, referring to fig. 16 and 17, a complete product, that is, the integrally molded electronic device of the present embodiment can be obtained.
As can be seen from the above, in the present embodiment, the lead frame 2A and the connecting bridge wire 3A are combined to form a coil to realize the inductance function, and the first integrated circuit 1 is disposed inside the inductance coil 4. The inductor coil 4 is encapsulated with the first integrated circuit 1 using the magnetic material 5, directly molded, i.e. without a prefabricated inductor; the inductor core of the inductor is on the outside and the first integrated circuit 1 and the inductor winding 4 are on the inside. The power density can be further improved, the efficiency is increased, the size of the packaged product is reduced, the size of the product is small, the inductance of the inductor can be increased, and the heat dissipation effect is improved.
The integrated electronic device may also comprise other components, such as capacitors arranged on the circuit frame 2.
Second embodiment
The present embodiment differs from the first embodiment in that: the first integrated circuit 1 is a flip-chip integrated circuit 1B; solder balls (Solder Ball) are arranged above the copper columns of the flip-chip integrated circuit 1B; the second element 3 is a bridge conductor 3B.
Referring to fig. 22 to 24, step a1 specifically includes: the solder balls of the flip-chip integrated circuit 1B are connected to the electrodes of the circuit frame 2 having the first element 21 so that the flip-chip integrated circuit 1B is located above the first element 21.
Referring to fig. 18 and 19, the circuit frame 2 is embodied as a lead frame 2A.
Referring to fig. 22 to 24, since the first integrated circuit 1 is the flip-chip integrated circuit 1B, the solder balls 101 of the flip-chip integrated circuit 1B are dipped in flux (flux) and then placed on the corresponding positions on the electrodes of the lead frame 2A, so as to fix the flip-chip integrated circuit 1B and connect the flip-chip integrated circuit 1B and the lead frame 2A.
Referring to fig. 25 and 26, step a2 specifically includes: the bridge conductor 3B is connected to the first element 21 above the first integrated circuit 1 to form the inductor coil 4 surrounding the first integrated circuit 1.
Illustratively, the bridge conductor 3B is a copper bridge.
Before step a2 is performed, referring to fig. 20 and 21, solder paste 22 needs to be printed at corresponding locations on the first element 21, i.e., the conductive leads 21A of the lead frame 2A, to connect the bridge conductors 3B in step a 2. In this way, the bridge conductor 3B is placed at a corresponding position on the conductive lead 21A, and then reflow (reflow) is performed to connect the bridge conductor 3B with the conductive lead 21A.
Referring to fig. 27 to 29, in step a3, the conductive leads 21A, the bridge conductor 3B and the first integrated circuit 1 are encapsulated.
Referring to fig. 30 to 37, step a4 and step a5 are the same as those of the first embodiment.
Third embodiment
The present embodiments provide a product; the product comprises the integrated electronic device. Illustratively, the product is a converter, in particular a high power density DC-DC converter; alternatively, the product is a power source.
The embodiment of the application can simplify the manufacturing process and facilitate the manufacturing of products, thereby reducing the cost.
Those skilled in the art will appreciate that all or part of the processes of the embodiments methods may be performed by a computer program, which may be stored in a computer-readable storage medium and executed to perform the processes of the embodiments methods. And the aforementioned storage medium includes: various media capable of storing program codes, such as ROM or RAM, magnetic or optical disks, etc.
The foregoing is a further detailed description of the present application in connection with specific/preferred embodiments and is not intended to limit the present application to that particular description. For a person skilled in the art to which the present application pertains, several alternatives or modifications to the described embodiments may be made without departing from the concept of the present application, and these alternatives or modifications should be considered as falling within the scope of the present application.

Claims (10)

1. A method for manufacturing an integrally formed electronic device, comprising:
a1, connecting a first integrated circuit with a circuit frame having a first element such that the first integrated circuit is located above the first element;
a2, connecting a second element with the first element above the first integrated circuit to form an inductance coil surrounding the first integrated circuit;
a3, encapsulating the inductance coil with the first integrated circuit by using a magnetic material.
2. The method according to claim 1, wherein the a1 specifically comprises: fixedly connecting the first integrated circuit with a circuit frame having a first element with a non-conductive bonding material and connecting electrodes of the first integrated circuit with electrodes of the circuit frame with metal wires such that the first integrated circuit is located above the first element.
3. The method of manufacturing according to claim 1, wherein:
the first integrated circuit is a flip-chip integrated circuit; a solder ball is arranged above the copper column of the flip integrated circuit;
the A1 specifically comprises: connecting the solder balls of the flip-chip integrated circuit with electrodes of a circuit frame having a first element such that the flip-chip integrated circuit is located above the first element.
4. The method of manufacturing according to claim 1, wherein:
the circuit frame is a lead frame only with half-etched front surface; the first element is a conductive lead;
and the method also comprises A4, and performing back half etching on the lead frame after the package is finished so as to form a complete circuit.
5. The method of manufacturing according to claim 1, wherein: the second element comprises a connecting bridge wire and a bridge conductor in a specific form.
6. An integrally formed electronic device, comprising: comprises a circuit frame, a first integrated circuit and a second element;
the circuit frame is provided with a first element;
the first integrated circuit is connected with the circuit frame and is positioned above the first element;
the second element is located above the first integrated circuit;
the second element is connected with the first element to form an inductance coil surrounding the first integrated circuit;
further comprising a magnetic material encapsulating the inductor coil with the first integrated circuit.
7. The integrally formed electronic device of claim 6, wherein: the specific form of the circuit frame comprises a lead frame and a printed circuit board.
8. The integrally formed electronic device of claim 6, wherein: the second element comprises a connecting bridge wire and a bridge-shaped conductor in a specific form; the bridge-shaped conductor is a copper bridge.
9. The integrally formed electronic device of claim 6, wherein: the first element is a conductive lead; the first integrated circuit is a control integrated circuit.
10. A product characterized by: comprising an integrally formed electronic device according to any of claims 6 to 9.
CN202010237941.2A 2020-03-30 2020-03-30 Integrally formed electronic device and manufacturing method thereof Withdrawn CN111477551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010237941.2A CN111477551A (en) 2020-03-30 2020-03-30 Integrally formed electronic device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010237941.2A CN111477551A (en) 2020-03-30 2020-03-30 Integrally formed electronic device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN111477551A true CN111477551A (en) 2020-07-31

Family

ID=71749281

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010237941.2A Withdrawn CN111477551A (en) 2020-03-30 2020-03-30 Integrally formed electronic device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111477551A (en)

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