CN114334662B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN114334662B CN114334662B CN202210227839.3A CN202210227839A CN114334662B CN 114334662 B CN114334662 B CN 114334662B CN 202210227839 A CN202210227839 A CN 202210227839A CN 114334662 B CN114334662 B CN 114334662B
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Abstract
The application discloses a forming method of a semiconductor device and the semiconductor device, wherein the forming method comprises the following steps: manufacturing a grid structure on a semiconductor substrate; forming a side wall on the surface of the side wall of the grid structure, wherein the thickness of the side wall is equal to the sum of a design target value and a preset thickening value; and taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate at two sides of the grid structure to form a source region and a drain region. According to the method, the side wall of the gate structure is thickened, so that the distance between the source and the drain of the semiconductor device is increased, the electric field peak value in the channel can be reduced, the HCI effect is improved, the method is simple to operate, and the cost is not increased basically.
Description
Technical Field
The present disclosure relates to the field of semiconductor devices, and more particularly, to a method for forming a semiconductor device and a semiconductor device.
Background
As the size of semiconductor devices (such as MOSFETs) is continuously reduced, the sizes of the semiconductor devices, such as channel length, polysilicon gate thickness and junction depth, are also reduced in an equal ratio, but the power supply voltage is not reduced in an equal ratio, so that the electric field strength of the channel region is significantly increased, and the Hot Carrier Injection (HCI) effect reduces the lifetime of the semiconductor devices.
In the related art, the HCI can be improved by adding a Lightly Doped Drain (LDD) region, but this method requires a new mask; or, a new mask is not added, but a mask of other steps is shared, and the LDD region is manufactured by controlling the concentration, angle, area of the implanted region, and the like of the ion implantation of the LDD region.
The increase of the mask or the decrease of the yield increases the manufacturing cost of the semiconductor device.
Disclosure of Invention
The application provides a method for forming a semiconductor device and the semiconductor device, which can improve HCI effect with low cost scheme.
In a first aspect, an embodiment of the present application provides a method for forming a semiconductor device, including:
manufacturing a grid structure on a semiconductor substrate;
forming a side wall on the surface of the side wall of the grid structure, wherein the thickness of the side wall is equal to the sum of the design target value and a preset thickening value;
and taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate at two sides of the grid structure to form a source region and a drain region.
Optionally, the side walls include a first sub-side wall covering the surface of the side wall of the gate structure and a second sub-side wall covering the surface of the first sub-side wall.
Optionally, the thickness of the first sub-sidewall is equal to the sum of the design target value of the first sub-sidewall and the preset thickening value.
Optionally, the method for forming a sidewall on the sidewall surface of the gate structure further includes:
manufacturing a first insulating layer, wherein the first insulating layer covers the side face and the top face of the grid structure and the top face of the semiconductor substrate outside the grid structure, and the thickness of the first insulating layer is equal to the sum of the design target value of the first sub-side wall to be formed and the preset thickening value;
manufacturing a second insulating layer on the first insulating layer;
etching the second insulating layer, and reserving the second insulating layer on the side surface of the gate structure to form the second sub-side wall;
and etching the first insulating layer, and reserving the first insulating layer covered by the etched second insulating layer to form the first sub-side wall.
Optionally, the first insulating layer is an oxide layer, or the first insulating layer is formed by alternately stacking oxide layers and nitride layers, and one side of the first insulating layer close to the sidewall surface of the gate structure is an oxide layer.
Optionally, the second insulating layer is a nitride layer, or the second insulating layer is formed by alternately stacking nitride layers and oxide layers.
Optionally, the oxide is silica or alumina.
Optionally, the ratio of the preset thickening value to the design target value of the first sub-sidewall is 0.4-2.
Optionally, before forming the side wall, the method further includes:
and performing light doping ion implantation on the semiconductor substrate by taking the grid structure as a mask, and forming light doping regions in the semiconductor substrate at two sides of the grid structure.
In a second aspect, an embodiment of the present application further provides a semiconductor device, including a semiconductor substrate, the semiconductor substrate is provided with a gate structure and a source region and a drain region located in the semiconductor substrate on both sides of the gate structure, a side face of the gate structure is provided with a side wall, and a thickness of the side wall is equal to a sum of a design target value and a preset thickening value.
Optionally, the side walls include a first sub-side wall covering the surface of the side wall of the gate structure and a second sub-side wall covering the surface of the first sub-side wall.
Optionally, the thickness of the first sub-sidewall is equal to the sum of the design target value of the first sub-sidewall and the preset thickening value.
Optionally, the ratio of the preset thickening value to the design target value of the first sub-sidewall is 0.4-2.
Optionally, the first sub-sidewall is an oxide layer, or the first sub-sidewall is formed by alternately stacking oxide layers and nitride layers, and one side of the first sub-sidewall, which is close to the sidewall surface of the gate structure, is an oxide layer.
Optionally, the second sub-side wall is a nitride layer, or the second sub-side wall is formed by alternately stacking nitride layers and oxide layers.
Optionally, the semiconductor device further includes two lightly doped ion implantation regions, the two lightly doped ion implantation regions are respectively located at two sides of the gate structure, one lightly doped ion implantation region separates the gate structure from the source region, and the other lightly doped ion implantation region separates the gate structure from the drain region.
The forming method of the semiconductor device comprises the steps of firstly, manufacturing a grid structure on a semiconductor substrate; then forming a side wall on the surface of the side wall of the grid structure, wherein the thickness of the side wall is equal to the sum of the design target value and the preset thickening value; and finally, taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate on two sides of the grid structure to form a source region and a drain region. The side wall of the grid structure is thickened, and particularly the thickness of the side wall is equal to the sum of a design target value and a preset thickening value. After the side wall of the grid structure is thickened, the distance between the source and the drain of the semiconductor device is lengthened, the electric field peak value in the channel can be reduced, and the aim of improving the HCI effect is fulfilled. The method is simple to operate, and the cost is not increased basically.
Drawings
The technical solutions and advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure;
FIGS. 2a-2g are schematic cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present disclosure;
fig. 3 is a schematic flow chart illustrating a method for forming a sidewall of a gate structure according to an embodiment of the present disclosure.
Detailed Description
Refer to the drawings wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.
With the continuous reduction of the size of a semiconductor device, the sizes of the channel length, the polysilicon gate thickness, the junction depth and the like of the semiconductor device are also reduced in an equal ratio, but the power supply voltage is not reduced in an equal ratio, so that the electric field intensity of a channel region is obviously increased, and the problem of parameter change of the semiconductor device due to the hot carrier injection effect is more prominent. In the related art, the HCI effect can be improved by adding LDD regions, but this method requires adding a new mask; or the new photomask is not added, but the photomask of other steps is shared, and the LDD region is manufactured by controlling the ion implantation concentration, angle, area of the implantation region and the like of the LDD region, but the control difficulty is high, the yield is reduced, and the manufacturing cost of the semiconductor device is higher. Based on the method, the forming method of the semiconductor device is provided, and manufacturing cost of the semiconductor device can be reduced.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for forming a semiconductor device according to an embodiment of the present disclosure, the method including:
101. and manufacturing a gate structure on the semiconductor substrate.
For example, the semiconductor substrate may be made of a material such as single crystal silicon, silicon carbide, gallium arsenide, indium phosphide, or silicon germanium, and for example, P atoms may be implanted into single crystal silicon to form a semiconductor substrate having N-type conductivity, or B atoms may be implanted into single crystal silicon to form a semiconductor substrate having P-type conductivity. Well regions may also be fabricated on the semiconductor substrate. The gate structure may include a gate dielectric layer and a polysilicon gate or a metal gate. The material of the gate dielectric layer may be an oxide, such as silicon dioxide, and the material of the gate dielectric layer is preferably a low dielectric constant material, such as benzocyclobutene resin (BCB).
The gate structure may be directly fabricated on the semiconductor substrate, or fabricated on a well region of the semiconductor substrate, and may be specifically selected according to the type and structure of the semiconductor device.
Referring to fig. 2a, for example, in the case of an N-type semiconductor substrate 100, the semiconductor substrate 100 may be cleaned, for example, by using a chemical reagent 1 (NH molar ratio) 3 ·H 2 O : H 2 O 2 : H 2 O =1:2: 50) and chemical reagent 2 (molar ratio HCL: H) 2 O 2 : H 2 O =1:1: 50) sequentially cleaning the N-type semiconductor substrate 100 to remove organic/inorganic impurity particles on the surface of the semiconductor substrate 100, then making a P-type well region on the semiconductor substrate 100, and then making a gate structure 10 in the P-type well region of the semiconductor substrate 100, specifically, making a gate oxide 11 first, and then making a polysilicon gate 12 on the gate oxide 11.
It should be noted that the forming method of the P-well region, the gate oxide layer 11 and the polysilicon gate 12 is a conventional method in the art, and the description of this embodiment is omitted.
102. And forming a side wall on the surface of the side wall of the grid structure, wherein the thickness of the side wall is equal to the sum of the design target value and the preset thickening value.
The side walls of the gate structure 10 mainly prevent the gate from being shorted with the source and drain formed later. In this embodiment, the thickness of the side wall is equal to the sum of the design target value and the preset thickening value, that is, when the side wall of the gate structure 10 is manufactured, the thickness of the side wall is thickened, the thickened side wall is of the preset thickening value, and the side wall may be of a single-layer structure or a double-layer or multi-layer structure.
In an embodiment, referring to fig. 2g, the sidewalls of the gate structure 10 may include a first sub-sidewall 20 and a second sub-sidewall 30, and the first sub-sidewall 20 preferably has a better bonding force with the sidewall surface of the gate structure 10. For example, the first sub-sidewall 20 may be an oxide layer (O), or the first sub-sidewall 20 is formed by alternately stacking an oxide layer (O) and a nitride layer (N), and one side of the first sub-sidewall, which is close to the sidewall surface of the gate structure 10, is an oxide layer. The second sub-side walls 30 mainly protect the first sub-side walls 20, and strength or reliability of the side walls is improved. The second sub-spacers 30 may be nitride layers (N), or the second sub-spacers 30 are formed by alternately stacking nitride layers (N) and oxide layers (O). As an example, the material of the oxide layer may be silicon dioxide, aluminum oxide, or the like, and the material of the nitride layer may be silicon nitride, silicon oxynitride, or the like, so that, in general, the sidewall spacer may be an O structure, or an ON stack structure, an ONO stack structure, an ONON stack structure, or the like.
It should be noted that, the thickness of the side wall is thickened, the first sub-side wall 20 may be thickened, the second sub-side wall 30 may be thickened, and the first sub-side wall 20 and the second sub-side wall 30 may be thickened at the same time, which is not particularly limited in this application.
For example, when only the first sub-side wall 20 is thickened, the thickness of the first sub-side wall 20 is equal to the sum of the design target value and the preset thickened value of the first sub-side wall. For example, according to the structure design of the semiconductor device, if the design target value of the first sub-sidewall 20 is T1, in order to improve the HCI effect, when the semiconductor device is fabricated by using the method of this embodiment, the thickness of the first sub-sidewall 20 is increased based on T1, and the preset increase value T2 may be determined according to the requirement of the voltage endurance performance of the semiconductor device. Preferably, the ratio of the preset thickening value T2 to the design target value T1 of the first sub-sidewall 20 is 0.4-2, which can improve the HCI effect without significantly affecting the performance of the semiconductor device. For example, T1 may be equal to 100 a, T2 may be equal to 40 a, 50 a, 60 a, 80 a, 100 a, 120 a, 140 a, 170 a, 200 a, etc., the final thickness of the first side wall 20 fabricated accordingly is T1+ T2. In this embodiment, the material of the first sub-sidewall 20 is preferably an oxide layer, and the oxide layer and the gate structure 10 have a strong bonding force and a small material stress, so that a thick first sub-sidewall 20 can be formed by deposition, and the shape can be kept intact while the requirement of thickness thickening is met, and an excessive stress is not generated on the internal microstructure of the semiconductor device. In addition, when the first sub-sidewall 20 is an oxide layer, the deposition thickness is easier to control, and the required thickness can be accurately controlled.
As an example, the first sub-spacers 20 are silicon dioxide (O), the second sub-spacers 30 are silicon nitride (N), the spacers are of an ON structure, the inner first sub-spacers 20 provide good bonding force with the semiconductor substrate 100, and the outer second sub-spacers 30 may serve as a protective layer for the first sub-spacers 20.
As another example, the first sub-sidewall 20 is a silicon dioxide layer (O), the second sub-sidewall 30 is a double-layer structure of a silicon nitride layer (N) and a silicon dioxide layer (O), and the entire sidewall is an ONO structure. The silicon nitride is hard, the internal stress is large, and the silicon nitride cannot be made too thick, so that the thickness of the side wall can be increased by manufacturing a layer of silicon dioxide on the surface of the silicon nitride.
Referring to fig. 2b-2f and fig. 3, the method for forming a sidewall on the sidewall surface of the gate structure in step 102 may include the following steps 1021-:
1021. and manufacturing a first insulating layer, wherein the first insulating layer covers the side surface and the top surface of the grid structure and the top surface of the semiconductor substrate outside the grid structure, and the thickness of the first insulating layer is equal to the sum of the design target value and the preset thickening value of the first sub-side wall to be formed.
For example, referring to fig. 2b, a first insulating layer 20A is formed on the top surface of the semiconductor substrate 100 and the side surfaces and the top surface of the gate structure 10. It is understood that the first insulating layer 20A covers the side and top surfaces of the gate structure 10 and the top surface of the semiconductor substrate 100 except for the gate structure 10. The first insulating layer 20A may be an oxide, for example, the first insulating layer 20A may be silicon dioxide, aluminum oxide, or the like, and the first insulating layer 20A serves as a pad having a better bonding force with the semiconductor substrate 100. The first insulating layer 20A may be formed using a deposition process such as CVD (chemical vapor deposition) \ ALD (atomic layer deposition).
For example, the semiconductor substrate 100 may be placed in a high temperature quartz tube furnace, and the first insulating layer 20A may be grown on the upper surface of the semiconductor substrate 100 at 650-. The thickness of the first insulating layer 20A is equal to the sum of the design target value and the preset thickening value.
1022. And manufacturing a second insulating layer on the first insulating layer.
Referring to fig. 2c, after the first insulating layer 20A is formed, a second insulating layer 30A is formed on the first insulating layer 20A. It is understood that the second insulating layer 30A covers the first insulating layer 20A. The second insulating layer 30A may be silicon nitride, or may be an insulating layer in which silicon nitride and silicon dioxide are alternately stacked.
As an example, the first insulating layer 20A is first silicon oxide (O), the second insulating layer 30A is silicon nitride (N), the entire insulating layer is an ON structure, the inner first silicon oxide provides a good bonding force with the semiconductor substrate 100, and the outer silicon nitride can serve as a protective layer of the first insulating layer 20A to prevent the first silicon oxide from being etched away during wet etching (see the subsequent etching step). The semiconductor substrate 100 may be placed in a high temperature quartz tube furnace and the second insulating layer 30A may be grown on the upper surface of the first insulating layer 20A at 620-680 c.
As another example, referring to fig. 2d, the first insulating layer 20A is a first silicon dioxide layer (O), the second insulating layer 30A is a double-layer insulating layer of a silicon nitride layer (N) 31 and a second silicon dioxide layer 32 (O), and the entire insulating layer is an ONO structure. Since the silicon nitride layer 31 is hard and has a large internal stress, it cannot be made too thick, and thus the thickness of the entire insulating layer can be increased by forming a layer of silicon dioxide on the surface of the silicon nitride. In the manufacturing process, the inner insulating layer silicon nitride layer 31 may be first manufactured, and then the outer insulating layer second silicon dioxide layer 32 may be manufactured. For example, the second silicon dioxide layer 32 may be grown on the surface of the silicon nitride layer 31 at 650-720 ℃. Preferably, the thickness of the second silicon dioxide layer 32 is greater than that of the first silicon dioxide layer, so as to ensure that the second silicon dioxide layer 32 remains on the sidewall after the wet etching of the first silicon dioxide layer (see the subsequent etching step for the first insulating layer 20A and fig. 2 f).
1023. And etching the second insulating layer, and reserving the second insulating layer on the side surface of the gate structure to form the second sub-side wall.
In this step, the sidewall of the gate structure 10 is mainly formed, and therefore, the second insulating layer 30A outside the sidewall of the gate structure 10 needs to be etched. It can be understood that the etching of the second insulating layer 30A is preferably an anisotropic etching, that is, the etching speeds in different directions are different, so that the second insulating layer 30A in the target etching region of the second insulating layer 30A (including the top surface of the gate structure and the top surface of the semiconductor substrate 100 outside the gate structure 10) is removed, and only the second insulating layer 30A on the side surface of the gate structure is remained, that is, the second sub-sidewall 30 is formed, and the schematic diagram of the etching effect is shown in fig. 2 e. It should be noted that the second sub-sidewall 30 is a remaining portion of the second insulating layer 30A after etching, and different reference numerals are used to distinguish two features. For example, the second insulating layer 30A may be etched using a maskless dry etching process. Note that the etching rate of the dry etching in the vertical direction shown in the figure is much higher than that in the horizontal direction.
In order to completely etch the second insulating layer 30A in the target etching region, when the second insulating layer 30A is completely etched, a portion of the first insulating layer 20A may be continuously etched, for example, the first insulating layer 20A is etched 20-60A, that is, the target etching region is over-etched, which ensures that the second insulating layer 30A in the target etching region is completely removed, and the first insulating layer 20A in the target etching region is exposed.
1024. And etching the first insulating layer, and reserving the first insulating layer covered by the etched second insulating layer to form the first sub-side wall.
After the second insulating layer 30A in the target etching region is etched, the first insulating layer 20A in the target etching region is etched, and only the first insulating layer 20A covered by the etched second insulating layer 30A is remained, i.e., the first sub-sidewall 20 is formed, so as to finally form the sidewall of the gate structure 10, and a schematic diagram of an etching effect refers to fig. 2 f. Note that the first sub-sidewall 20 is a remaining portion of the first insulating layer 20A after etching, and different reference numerals are used to distinguish two features. The first insulating layer 20A may be etched by a wet method or a dry method, for example, the first insulating layer 20A may be etched by a hydrofluoric acid solution.
103. And taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate at two sides of the grid structure to form a source region and a drain region.
For example, referring to fig. 2g, after the gate structure 10 and the sidewall thereof are formed, the source region 41 and the drain region 42 may be fabricated by ion implantation using the gate structure 10 and the sidewall as masks. For example, phosphorus atoms may be implanted into the P-type conductive well regions on both sides of the gate structure 10 to form two N + doped regions corresponding to the source region 41 and the drain region 42, respectively. It should be noted that, the improvement of the present embodiment lies in: the sidewall of the gate structure 10 is thickened, and the source region 41 and the drain region 42 can be manufactured by a conventional method, which is not described in detail in this embodiment.
In one embodiment, referring to fig. 2g, before forming the gate structure 10, Shallow Trench Isolation (STI) regions 60 may be formed on both sides of the top surface of the semiconductor substrate 100, respectively, for isolating adjacent other semiconductor devices. For example, trenches may be etched in both sides of the top surface of the semiconductor substrate 100, and then the trenches may be filled with a deposited oxide.
It can be understood that, in the method for forming the semiconductor device of the present embodiment, the gate structure is first fabricated on the semiconductor substrate; then forming a side wall on the surface of the side wall of the grid structure, wherein the thickness of the side wall is equal to the sum of the design target value and the preset thickening value; and finally, taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate on two sides of the grid structure to form a source region and a drain region. In this embodiment, the sidewall of the gate structure is thickened, specifically, the thickness of the sidewall is equal to the sum of the design target value and the preset thickened value. After the side wall of the grid structure is thickened, the distance between the source and the drain of the semiconductor device is lengthened, the electric field peak value in the channel can be reduced, and the aim of improving the HCI effect is fulfilled. The method is simple to operate, and the cost is not increased basically.
It is emphasized that, in the fabrication of semiconductor devices, platforms for different processes have fixed process parameters, such as: in the logic product of 180um (gate width) process, when the sidewall is an ONO structure, the thickness of each corresponding layer is 150/300/1000 (unit: a, the same below). When the sidewall of the high-voltage product of 160um process is an ONO structure, the thickness of each corresponding layer is 150/300/1000. In the image sensor product manufactured by the 153um process, when the sidewall is of the ONO structure, the thickness of each corresponding layer is 150/300/800. In the front-illuminated image sensor product with the 90nm technology, when the side wall is of an ON structure, the thickness of each corresponding layer is 100/700. When the sidewall of the 55nm back-illuminated image sensor product is of an ON structure, the thickness of each corresponding layer is 100/550. For a particular platform, the skilled person would not have to make the modification of the sidewall thickness, which is an inertial thinking in the art.
Also, it is also common practice in the art to improve the HCI effect by adding LDD regions. The disadvantages of this method are: (1) a new photomask is required to be added, so that the cost is increased; (2) different photomasks are required to be added for different devices, and the method has poor universality and is not flexible enough; (3) when the LDD region is manufactured, parameters such as concentration, angle and area of the ion implantation of the LDD region need to be adjusted, the control difficulty is high, and the yield is reduced, so that the manufacturing cost of the semiconductor device is further increased. The embodiment breaks through the inertia thinking and abandons the conventional method for improving the HCI in the field, the aim of improving the HCI effect can be achieved by thickening the side wall of the gate structure 10, LDD injection and photomask addition are not needed, the cost is basically unchanged, and the method is suitable for various types of devices, the process is mature, and the operation is simple. The data show that the lifetime of the device can be further improved by 39.4% better with this method than with the conventional method of increasing the LDD region.
In an embodiment, referring to fig. 2g, before forming the sidewall of the gate structure 10 on the semiconductor substrate 100, i.e., before the step corresponding to fig. 2b, a lightly doped ion (N-) implantation may be performed on the semiconductor substrate 100 by using the gate structure as a mask, so as to form a lightly doped region (LDD region) 50 in the semiconductor substrate 100 at two sides of the gate structure 10, and then, a step of forming the sidewall of the gate structure 10 is performed. The LDD regions 50 may withstand a portion of the voltage in the channel to further improve HCI effects. The ion implantation of the LDD region 50 may be performed by a tilt ion implantation process or a vertical ion implantation process. The vertical implantation enables the impurity of the LDD region 50 to diffuse laterally at the time of annealing more slowly than the inclined implantation, and improves the HCI effect while improving the short channel effect. The type of ions implanted into the LDD regions 50 may be determined by the electrical characteristics of the semiconductor device being formed. For example, when the device being formed is a PMOS, the implanted impurity ions may be boron or indium; when the device is formed as an NMOS, the implanted impurity ions may be one or a combination of phosphorus, arsenic, antimony, and bismuth.
With reference to fig. 2g, the present embodiment further provides a semiconductor device, which includes a semiconductor substrate 100, wherein the semiconductor substrate 100 is provided with a gate structure 10, a source region 41 and a drain region 42, and the source region 41 and the drain region 42 are located at two sides of the gate structure 10. The side face of the grid structure 10 is provided with a side wall, and the thickness of the side wall is equal to the sum of the design target value and the preset thickening value.
In the semiconductor device of the embodiment, the thickness of the side wall of the gate structure 10 is equal to the design target value and the preset thickening value, and the side wall of the gate structure 10 is thicker than that of the conventional semiconductor device, so that the distance L between the source and the drain of the semiconductor device is longer, the electric field peak value in the channel can be reduced, and the aim of improving the HCI effect is fulfilled.
In one embodiment, the sidewalls of the gate structure 10 include a first sub-sidewall 20 and a second sub-sidewall 30. The first sub-sidewall 20 is disposed on a side surface of the gate structure 10, and a thickness of the first sub-sidewall 20 is equal to a sum of a design target value and a preset thickening value; the second sub-sidewall 30 is stacked on the surface of the first sub-sidewall 20.
Taking an N-type semiconductor substrate 100 as an example, a P-type well region may be disposed on the semiconductor substrate 100, the gate structure 10, the source region 41, and the drain region 42 are located in the P-type well region, and the source region 41 and the drain region 42 are located at two sides of the gate structure 10, the gate structure 10 includes a gate oxide layer 11 and a polysilicon gate 12, the first sub-sidewall 20 is disposed at a side of the gate structure 10, and the thickness of the first sub-sidewall 20 is equal to the sum of a design target value and a preset thickening value, and the second sub-sidewall 30 is stacked on the surface of the first sub-sidewall 20.
In one embodiment, the first sub-sidewall 20 is a first silicon dioxide layer, the second sub-sidewall 30 is a silicon nitride layer, the sidewall of the gate structure 10 is an ON structure, and the silicon nitride layer ON the outer side has a protective effect ON the first silicon dioxide layer thickened ON the inner side.
In one embodiment, the first sub-sidewall spacers 20 are first silicon dioxide layers, and the second sub-sidewall spacers 30 include a silicon nitride layer 31 and a second silicon dioxide layer 32 sequentially stacked on the surfaces of the first sub-sidewall spacers 20.
In one embodiment, the thickness of the first sub-sidewall 20 is equal to the sum of the design target value and the preset thickening value of the first sub-sidewall 20.
In one embodiment, the ratio of the preset thickening value to the design target value of the first sub-sidewall 20 is 0.4-2.
In one embodiment, the first sub-sidewall spacers 20 are oxide layers, or the first sub-sidewall spacers 20 are formed by alternately stacking oxide layers and nitride layers, and one side of the first sub-sidewall spacers close to the sidewall surface of the gate structure 10 is an oxide layer.
In one embodiment, the second sub-sidewall spacers 30 are nitride layers, or the second sub-sidewall spacers 30 are formed by alternately stacking nitride layers and oxide layers.
In one embodiment, the semiconductor device may further include two LDD regions 50, the two LDD regions 50 being located on either side of the gate structure 10, and one LDD region 50 separating the gate structure 10 from the source region 41 and the other LDD region 50 separating the gate structure 10 from the drain region 42.
In one embodiment, the semiconductor device may further include two Shallow Trench Isolation (STI) regions 60 respectively located on two sides of the top surface of the semiconductor device for isolating other adjacent semiconductor devices.
For the operation principle of the semiconductor device of this embodiment, refer to the foregoing description of the method for forming the semiconductor device of this application, and no further description is given here.
It will be appreciated that embodiments of the present application will work with the conductivity type of the regions of the semiconductor substrate of fig. 2g being reversed.
The present application is further illustrated by the following specific examples.
Example 1
The method comprises the following steps:
201. and cleaning the semiconductor substrate, and manufacturing a gate structure on the semiconductor substrate.
202. A first silicon dioxide is grown at 680 ℃ using a furnace tube atomic deposition process, the first silicon dioxide covering side and top surfaces of the gate structure and a top surface of the semiconductor substrate outside the gate structure, and a thickness of the first silicon dioxide is equal to a sum of a design target value of 150 a and a predetermined thickness value of 150 a, i.e., 300 a.
203. And growing silicon nitride on the surface of the first silicon dioxide at 650 ℃ by adopting a furnace tube atomic deposition process, wherein the growth thickness is 300A.
204. And growing a second silicon dioxide on the surface of the silicon nitride at 680 ℃ by adopting a furnace tube atomic deposition process, wherein the growth thickness is 1000A.
205. And etching the second silicon dioxide and the silicon nitride in the target etching area and the first silicon dioxide with the thickness of 50A by adopting dry etching to form a second sub-side wall, wherein the second sub-side wall is of a laminated structure of the second silicon dioxide and the silicon nitride. The target etching area comprises a top surface of the gate structure and a top surface of the semiconductor substrate outside the gate structure.
206. And continuously etching the first silicon dioxide in the target etching area by adopting wet etching to form a first sub-side wall, wherein the first sub-side wall is made of the first silicon dioxide. It should be noted that, in order to facilitate subsequent manufacturing steps, the first silicon dioxide with a thickness of 50 a may be kept as a mask protection layer, and the first silicon dioxide is completely etched away after the manufacturing of the source region and the drain region is completed.
207. And taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate at two sides of the grid structure to form a source region and a drain region.
Example 2
The method comprises the following steps:
301. and cleaning the semiconductor substrate, and manufacturing a gate structure on the semiconductor substrate.
302. A first silicon dioxide is grown using a chemical vapor deposition process, the first silicon dioxide covering the side and top surfaces of the gate structure and the top surface of the semiconductor substrate outside the gate structure, and having a thickness equal to the sum of a design target value 100 a and a predetermined thickening value 100 a, i.e., 200 a.
303. And growing silicon nitride on the surface of the first silicon dioxide by adopting a low-pressure chemical vapor deposition process, wherein the growth thickness is 500A.
304. And etching the silicon nitride in the target etching area and the first silicon dioxide in the 40A by adopting a dry etching method to form a second sub-side wall, wherein the second sub-side wall is made of silicon nitride. The target etching area comprises a top surface of the gate structure and a top surface of the semiconductor substrate outside the gate structure.
305. And continuously etching the first silicon dioxide in the target etching area by adopting wet etching to form a first sub-side wall, wherein the first sub-side wall is made of the first silicon dioxide. It should be noted that, in order to facilitate subsequent manufacturing steps, the first silicon dioxide with the thickness of 30a may be kept as a mask protection layer, and the first silicon dioxide is completely etched away after the manufacturing of the source region and the drain region is completed.
306. And taking the grid structure and the side walls as masks, and performing ion implantation in the semiconductor substrate at two sides of the grid structure to form a source region and a drain region.
Comparative example 1
Comparative example 1 differs from example 1 only in that the first silica has a thickness of 150 a.
Comparative example 2
Comparative example 2 differs from example 2 only in that the first silica has a thickness of 100 a.
Comparative example 3
Comparative example 3 on the basis of comparative example 1, an LDD structure is added, i.e. comparative example 3 differs from example 1 in that the first silicon dioxide has a thickness of conventional thickness 150 a, but the LDD region is increased. Wherein, the LDD region is implanted with P element, when the energy is 70keV, the dose is 1.7E13, the title angle (the included angle between the incident direction and the normal) is 30 degrees, the twist angle (the included angle between the projection of the incident direction on the wafer and the wafer normal direction) is 315 degrees, the service life of the device is 4.33E-03 years, and the service lives of the devices corresponding to the following improved processes all take the service life value as a comparison reference; the energy is adjusted to 85keV, and the service life of the device is prolonged to 7.45E-02 years. Increasing the energy to 85keV while increasing the dose to 2E13, increasing the device lifetime to 3.17E-02 years, increasing the energy to 85keV while adjusting the title angle to 45, improving the device lifetime to 1.94E-03 years; the energy is adjusted to 85keV, the dose is adjusted to 2E13, the title angle is adjusted to 45 degrees, and the device lifetime is improved to 2.03E-01 years.
Comparing example 1 with comparative example 1, the lifetime of the semiconductor device was tested according to standards established by JEDEC (solid state technology association), and the results show that by increasing the thickness of the first sub-sidewall from 150 a to 300 a, the lifetime of the 5V NMOS device was increased from 2.15E-03 years to 2.83E-01 years; the life of the 5V PMOS device is increased from 2.92E-02 years to 3.72E +00 years;
comparing example 2 with comparative example 2, the results show that by increasing the thickness of the first sub-sidewall from 100 a to 200 a, the lifetime of the 2.8V NMOS device is increased from 2.12E-03 years to 1.62E +00 years; the lifetime of 2.8V PMOS devices increased from 8.66E-02 years to 4.2E +02 years.
Comparing example 1 with comparative example 3, the results show that example 1 can achieve a lifetime of a 5V NMOS device of 2.83E-01 years by increasing the thickness of the first sub-sidewall from 150 a to 300 a, that the first sub-sidewall of comparative example 3 has a thickness of a conventional thickness of 150 a, but with an increased LDD region, that the lifetime of the device is at most 2.03E-01 years in experiments with multiple LDD implantation parameters, and that device lifetime fluctuations are large with process differences, making product consistency control difficult. Compared with the comparative example 3, the service life of the device can be further improved by 39.4% in the embodiment 1 of the application, and the control process of the thickness of the side wall is more mature.
It should be noted that, in the above embodiments, the preset thickening value is equal to the design target value, but for those skilled in the art, the effect of reducing the channel electric field peak value is better when the thickening value is larger than the design target value, without considering the influence on other performances of the semiconductor device, and the technical effect is predictable, therefore, the preset thickening value may also be larger than or smaller than the design target value, and may be selected according to the performances of the device.
In summary, the method for forming the semiconductor device according to the embodiment of the present application can significantly improve the HCI effect and prolong the lifetime of the semiconductor device, and is simple to operate, substantially free from increasing the cost, and suitable for different types of semiconductor devices.
The above detailed description is provided for a method for forming a semiconductor device and the semiconductor device provided in the embodiments of the present application, and the principles and embodiments of the present application are explained in detail herein by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
In addition, in the description of the present application, it is to be understood that the terms "top surface", "side surface", "vertical", "horizontal", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. In addition, the same or different reference numerals may be used to identify structures having the same or similar characteristics. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features.
Claims (2)
1. A method of forming a semiconductor device, comprising:
manufacturing a grid structure on a semiconductor substrate;
the side wall is formed on the surface of the side wall of the grid structure and comprises a first sub-side wall covering the surface of the side wall of the grid structure and a second sub-side wall covering the surface of the first sub-side wall, the thickness of the first sub-side wall is equal to the sum of the design target value of the first sub-side wall and a preset thickening value, and the ratio of the preset thickening value to the design target value of the first sub-side wall is 1: 1;
performing ion implantation in the semiconductor substrate on two sides of the gate structure by taking the gate structure and the side walls as masks to form a source region and a drain region;
the method for forming the side wall on the surface of the side wall of the gate structure further comprises the following steps:
manufacturing a first insulating layer, wherein the first insulating layer covers the side face and the top face of the grid structure and the top face of the semiconductor substrate outside the grid structure, and the thickness of the first insulating layer is equal to the sum of the design target value of the first sub-side wall to be formed and the preset thickening value;
manufacturing a second insulating layer on the first insulating layer;
etching the second insulating layer, and reserving the second insulating layer on the side surface of the gate structure to form the second sub-side wall;
etching the first insulating layer, and reserving the first insulating layer covered by the etched second insulating layer to form the first sub-side wall;
the first insulating layer is an oxide layer, and the oxide layer is a silicon dioxide layer;
the second insulating layer is a nitride layer, or the second insulating layer is formed by alternately laminating a nitride layer and an oxide layer;
and lightly doped regions are not manufactured in the semiconductor substrate at two sides of the grid structure.
2. The utility model provides a semiconductor device, includes the semiconductor substrate, be provided with the grid structure on the semiconductor substrate and be located source region and drain region in the semiconductor substrate of grid structure both sides, the side of grid structure is provided with the side wall, a serial communication port, the side wall is including covering the first sub-side wall on grid structure side wall surface and covering the second sub-side wall on first sub-side wall surface, the thickness of first sub-side wall equals the design target value of first sub-side wall and predetermines the thickening value sum, predetermine the thickening value with the ratio of the design target value of first sub-side wall is 1: 1;
the first sub-side wall is an oxide layer, the second sub-side wall is a nitride layer, or the second sub-side wall is formed by alternately laminating nitride layers and oxide layers; the forming method of the side wall comprises the following steps:
manufacturing a first insulating layer, wherein the first insulating layer covers the side face and the top face of the grid structure and the top face of the semiconductor substrate outside the grid structure, and the thickness of the first insulating layer is equal to the sum of the design target value of the first sub-side wall to be formed and the preset thickening value;
manufacturing a second insulating layer on the first insulating layer;
etching the second insulating layer, and reserving the second insulating layer on the side surface of the gate structure to form the second sub-side wall;
etching the first insulating layer, and reserving the first insulating layer covered by the etched second insulating layer to form the first sub-side wall;
and light doped ion implantation regions are not arranged on two sides of the grid structure.
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