CN114333701A - Grid driving circuit and method - Google Patents
Grid driving circuit and method Download PDFInfo
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- CN114333701A CN114333701A CN202210024524.9A CN202210024524A CN114333701A CN 114333701 A CN114333701 A CN 114333701A CN 202210024524 A CN202210024524 A CN 202210024524A CN 114333701 A CN114333701 A CN 114333701A
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Abstract
The invention discloses a grid drive circuit, which is used for outputting a drive signal to a panel electrode and comprises a drive module and a level signal holding module, wherein the drive module is used for driving a grid electrode to be driven; the driving module is electrically connected with the level signal holding module; the driving module is used for turning on a switch of the grid driving circuit through a high-level input signal; the level signal holding module is used for: and keeping the gate driving circuit to output a high-level signal and keep the high-level signal not pulled down in the first time sequence stage, and keeping the gate driving circuit to output a low-level signal and keep the low-level signal not lifted in the second time sequence stage. A gate driving method is also disclosed. By implementing the invention, the voltage of the grid driving signal is ensured not to be raised after the grid driving signal is started through the dual low-level signal guarantee, the influence of the subsequent time sequence level signal on the output is avoided, and the reliability of the driving circuit is improved.
Description
Technical Field
The present invention relates to the field of signal transmission technologies, and in particular, to a gate driving circuit and a method thereof.
Background
At present, the driving of the horizontal scanning lines of an Active-matrix organic light-emitting diode (AMOLED) display panel is implemented by an external integrated circuit, which can control the gradual charging and discharging of each level of scanning lines, and a Gate drive on Array (GOA) technology is adopted, which is to fabricate a Gate scan driving circuit on a TFT Array substrate by using a TFT Array process to implement a line-by-line scanning driving method. Therefore, the GOA technology can integrate the line scan driving circuit on the array substrate of the display panel, significantly reducing the usage of the external IC, thereby reducing the production cost and power consumption of the display panel, and realizing the narrow frame of the display device.
With the vigorous development of the photoelectric display industry, the goa (gate on array) circuit has been widely used in many fields such as hand-carried and industrial control. A GOA driver circuit (GOA circuit), typically comprises a plurality of driver cells in cascade. Since the GOA circuit is based on the shift function, i.e. the gate in a certain middle row is abnormally driven, the gate in the next row will have problems.
Research personnel find that the signal output to the panel grid in the Gate drive panel circuit often has a lifting phenomenon, namely the Gate drive Gate signal keeps a low level signal after being started, but the Gate output signal is gradually lifted in the time of keeping one frame later, so that the electric leakage of a TFT transistor is increased, the holding capacity of a pixel capacitor is reduced, and the abnormal display of the panel is caused.
Disclosure of Invention
In the prior art, a signal output to a panel Gate in a Gate driving panel circuit often has a lifting phenomenon, which causes an increase in TFT transistor leakage, a decrease in pixel capacitance holding capacity, and a panel display abnormality.
In order to solve the problems, a level signal holding module is arranged in the grid driving circuit, a second output switch is closed, the driving circuit outputs and holds a high level signal in a first time sequence high level signal stage, and voltage on a grid scanning line is ensured not to be raised through dual low level signal guarantee in a second time sequence high level signal stage, so that the influence of subsequent time sequence level signals on output is avoided, and the reliability of the driving circuit is improved.
In a first aspect, a gate driving circuit for outputting a driving signal to a panel electrode includes:
a drive module;
a level signal holding module;
the driving module is electrically connected with the level signal holding module;
the driving module is used for turning on a switch of the gate driving circuit through a high-level input signal;
the level signal holding module is used for:
keeping the grid drive circuit outputting a high level signal in the first time sequence stage, keeping the high level signal not pulled low,
and keeping the gate driving circuit to output a low-level signal in the second timing stage, and keeping the low-level signal not to be raised.
The first driving switch, the second driving switch, the third driving switch, the fourth driving switch, the fifth driving switch, the first output switch and the filtering unit;
the first driving switch or the second driving switch is used for starting and outputting a high level signal to the third driving switch and the fourth driving switch under the action of a high level signal and an initial signal so as to drive the third driving switch and the fourth driving switch to be started;
the third driving switch is used for outputting a high-level signal to the first output switch so as to drive the first output switch to be switched on;
the filtering unit is used for filtering clutter interference on the input low-level signal;
the first output switch is used for outputting a driving level signal to the panel grid.
With reference to the first possible implementation manner of the present invention, in a second possible implementation manner, the level signal holding module includes:
a seventh drive switch, an eighth drive switch, a ninth drive switch, and a second output switch;
the seventh driving switch is used for outputting a high-level signal to the ninth driving switch and the second output switch in a second time sequence stage so as to start the ninth driving switch and the second output switch;
the ninth driving switch is used for outputting a low level signal to the first output switch in a second time sequence stage so as to switch off the first output switch;
the eighth driving switch is used for outputting a low level signal to the first output switch in a second time sequence stage so as to switch off the first output switch;
the second output switch is used for outputting a low level signal to the output end of the driving circuit in a second time sequence stage so as to pull down the output level signal.
With reference to the second possible implementation manner of the present invention, in a third possible implementation manner, the first driving switch, the second driving switch, the third driving switch, the fourth driving switch, the fifth driving switch, the first output switch, and the filtering unit are respectively a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a first capacitor;
the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are respectively used for inputting a driving level signal;
the source electrode of the first MOS tube and the drain electrode of the second MOS tube are respectively used for inputting starting level signals of the first MOS tube and the second MOS tube;
the drain electrode of the first MOS tube, the source electrode of the second MOS tube, the source electrode of the third MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube are connected in common to form a first common connection point;
the drain electrode of the third MOS tube, the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube and the first end of the first capacitor are connected in common to form a second common connection point;
the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube and the input end of the first capacitor are connected in common;
the second end of the first capacitor is used for inputting a low-level signal;
the drain electrode of the sixth MOS tube is used for inputting the level signal of the first time sequence;
the source electrode of the sixth MOS tube is used for outputting a driving level signal;
with reference to the third possible implementation manner of the present invention, in a fourth possible implementation manner, the seventh driving switch, the eighth driving switch, the ninth driving switch, and the second output switch are respectively a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor;
the grid electrode of the seventh MOS tube is used for inputting a second time sequence level signal, the drain electrode of the seventh MOS tube is used for a high level signal, and the source electrode of the seventh MOS tube is connected with the grid electrode of the eighth MOS tube;
the source electrode of the eighth MOS tube and the drain electrode of the ninth MOS tube are connected with the second common contact point;
the drain electrode of the eighth MOS tube, the source electrode of the ninth MOS tube, the source electrode of the fourth MOS tube, the drain electrode of the fifth MOS tube and the input end of the first capacitor are connected in common;
the grid electrode of the ninth MOS tube and the grid electrode of the tenth MOS tube are connected in common to form a third common connection point;
the source electrode of the tenth MOS tube is connected with the input end of the first capacitor;
and the drain electrode of the tenth MOS tube and the source electrode of the sixth MOS tube are connected with the output end of the driving circuit in a common mode.
In a second aspect, a gate driving method using the driving circuit of the first aspect includes:
In a first possible implementation manner of the gate driving method according to the second aspect of the present invention, the step 100 includes:
With reference to the first possible implementation manner of the second aspect of the present invention, in a second possible implementation manner, the step 200 includes:
in step 220, the gate driving circuit outputs and maintains a low level signal at the second timing high level signal stage.
With reference to the second possible implementation manner of the second aspect of the present invention, in a third possible implementation manner, the step 210 includes:
and step 212, turning off the second output switch when the high-level signal is output in the first sequence high-level signal stage, so as to keep the high-level signal from being pulled down.
With reference to the third possible implementation manner of the second aspect of the present invention, in a fourth possible implementation manner, the step 220 includes:
According to the gate driving circuit and the method, the level signal holding module is arranged in the gate driving circuit, the second output switch is closed, the driving circuit outputs and holds a high level signal in the first time sequence high level signal stage, and the voltage on a gate scanning line is ensured not to be raised through dual low level signal guarantee in the second time sequence high level signal stage, so that the influence of subsequent time sequence level signals on the output is avoided, and the reliability of the driving circuit is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of the gate driver circuit logic connection of the present invention;
FIG. 2 is a schematic diagram of a gate driving circuit according to the present invention;
FIG. 3 is a schematic diagram of a first embodiment of a gate driving method according to the present invention;
FIG. 4 is a schematic diagram of a second embodiment of a gate driving method according to the present invention;
FIG. 5 is a schematic diagram of a third embodiment of a gate driving method according to the present invention;
FIG. 6 is a schematic diagram of a fourth embodiment of a gate driving method according to the present invention;
FIG. 7 is a diagram illustrating a fifth embodiment of a gate driving method according to the present invention;
FIG. 8 is a timing diagram of gate driving according to the present invention;
FIG. 9 is a schematic diagram of a gate driver circuit cascade in accordance with the present invention;
the part names indicated by the numbers in the drawings are as follows: 10-driving module, 20-level signal holding module.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Other embodiments, which can be derived by one of ordinary skill in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the prior art, a signal output to a panel Gate in a Gate driving panel circuit often has a lifting phenomenon, which causes an increase in TFT transistor leakage, a decrease in pixel capacitance holding capacity, and a panel display abnormality.
In order to solve the above problems, a gate driving circuit and a method thereof are provided.
In a first aspect, as shown in fig. 1, fig. 1 is a schematic diagram of a logic connection of a gate driving circuit in the present invention, a gate driving circuit for outputting a driving signal to a panel electrode, comprising: a driving module 10, a level signal holding module 20; the driving module 10 is electrically connected with the level signal holding module 20; the driving module 10 is used for turning on a switch of the gate driving circuit through a high-level input signal; the level signal holding module 20 is configured to: and keeping the gate driving circuit to output a high-level signal and keep the high-level signal not pulled down in the first time sequence stage, and keeping the gate driving circuit to output a low-level signal and keep the low-level signal not lifted in the second time sequence stage.
Further, the driving module 10 includes: the first driving switch, the second driving switch, the third driving switch, the fourth driving switch, the fifth driving switch, the first output switch and the filtering unit; the first driving switch and the second driving switch are respectively used for outputting high level signals to the third driving switch and the fourth driving switch under the action of the first high level signal, the second high level signal and the corresponding first initial signal and second initial signal; the first driving switch or the second driving switch is used for outputting a high-level signal to the third driving switch and the fourth driving switch so as to drive the third driving switch and the fourth driving switch to be switched on; the third driving switch is used for outputting a high level signal to the first output switch and is started by the first output switch; the filtering unit is used for filtering clutter interference on the input low-level signal; the first output switch is used for outputting a driving level signal to the panel grid.
Further, the level signal holding module 20 includes a seventh driving switch, an eighth driving switch, a ninth driving switch, and a second output switch; the seventh driving switch is used for outputting a high-level signal to the ninth driving switch and the second output switch in the second time sequence stage so as to start the ninth driving switch and the second output switch; the ninth driving switch is used for outputting a low level signal to the first output switch in the second time sequence stage so as to switch off the first output switch; the eighth driving switch is used for outputting a low level signal to the first output switch in the second time sequence stage so as to switch off the first output switch; the second output switch is used for outputting a low level signal to the output end of the driving circuit in the second time sequence stage so as to pull down the output level signal.
Through setting up level signal holding module 20 in gate drive circuit, at the high level signal stage of first preface, close second output switch, drive circuit output and keep high level signal, at the high level signal stage of second preface, through dual low level signal guarantee, guarantee that the voltage on the grid scanning line can not lift, avoided follow-up preface level signal to the influence of output, improved drive circuit's reliability.
Preferably, as shown in fig. 2, fig. 2 is a schematic diagram of a gate driving circuit connection according to the present invention, and the first driving switch, the second driving switch, the third driving switch, the fourth driving switch, the fifth driving switch, the first output switch, and the filtering unit are respectively a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a first capacitor C1.
The grid electrode of the first MOS transistor M1 and the grid electrode of the second MOS transistor M2 are respectively used for inputting driving level signals; the source electrode of the first MOS transistor M1 and the drain electrode of the second MOS transistor M2 are respectively used for inputting start level signals of the first MOS transistor M1 and the second MOS transistor M2; the drain electrode of the first MOS transistor M1, the source electrode of the second MOS transistor M2, the source electrode of the third MOS transistor M3, the gate electrode of the third MOS transistor M3 and the gate electrode of the fourth MOS transistor M4 are connected in common to form a first common junction P1; the drain electrode of the third MOS transistor M3, the gate electrode of the sixth MOS transistor M6, the gate electrode of the fifth MOS transistor M5 and the first end of the first capacitor C1 are connected in common to form a second common connection point P2; the source electrode of the fifth MOS transistor M5, the drain electrode of the fourth MOS transistor M4 and the input end of the first capacitor C1 are connected in common; the second end of the first capacitor C1 is used for inputting a low-level signal; the drain of the sixth MOS transistor M6 is used for inputting a level signal of the first timing; the source of the sixth MOS transistor M6 is used for outputting a driving level signal.
In the embodiment of the forward scan phase, as shown in fig. 9, fig. 9 is a schematic diagram of the cascade of gate driving circuits in the present invention; the U2D is a normal high level signal (in the normal scan phase, U2D is normal high, D2U is normal low, and the reverse scan phase is opposite), and enters the driving module 10, and the driving module 10 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a first capacitor C1. The U2D normal high level signal turns on the first MOS transistor M1, STVU reaches the position of the first common junction P1 as the starting signal, the high level signal at the position of the first common junction P1 turns on the third MOS transistor M3 and the fourth MOS transistor M4, and the high level signal reaches the position of the second common junction P2 after the third MOS transistor M3 is turned on so that the first output switch M6 is turned on. When the first timing stage CK1 is a high level signal, the driving circuit output SN outputs a high level signal, which means that the gate signal output state of the scan line is completed.
Preferably, the seventh driving switch, the eighth driving switch, the ninth driving switch, and the second output switch are respectively a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10; the gate of the seventh MOS transistor M7 is used for inputting the second timing level signal, the drain is used for the high level signal, and the source is connected to the gate of the eighth MOS transistor M8; the source electrode of the eighth MOS transistor M8 and the drain electrode of the ninth MOS transistor M9 are connected with the second common junction; the drain electrode of the eighth MOS transistor M8, the source electrode of the ninth MOS transistor M9, the source electrode of the fourth MOS transistor M4, the drain electrode of the fifth MOS transistor M5 and the input end of the first capacitor C1 are connected in common; the grid electrode of the ninth MOS transistor M9 and the grid electrode of the tenth MOS transistor M10 are connected in common to form a third common connection point; the source of the tenth MOS transistor M10 is connected to the input terminal of the first capacitor C1; the drain of the tenth MOS transistor M10 and the source of the sixth MOS transistor M6 are commonly connected to the output terminal of the driving circuit.
Referring to fig. 8 and fig. 8, when the gate driving timing diagram of the present invention is at the high level signal stage of the first timing CLK1, the first common node P1 turns on the M4 by the high level signal, and the VGL low level signal makes the potential at the point a also be the VGL low level signal through the M4, so as to ensure that the second output switch M10 is in the off state, so as to prevent the output signal level signal SN at the output terminal of the driving circuit from being pulled down.
When the second common node P2 high level signal turns on M5, the VGL low level signal can also be enabled to reach point a through M5, so as to ensure that the second output switch M10 is in a closed state, so as to prevent the output signal level signal SN at the output terminal of the driving circuit from being pulled low.
When the high-level signal phase of the second timing CLK3 is entered into the level signal keeping module 20, the level signal keeping module 20 includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a tenth MOS transistor M10.
The CLK3 turns on the M8, and the VGL low level signal passes through the M8 to make the second common node P2 a low level signal;
the CLK3 enables the M7 to be turned on, the VGH high level signal enables the point A to be in a high level signal state through the M7, the A high level signal enables the M9 to be turned on, and the VGL low level signal enables the point P2 to be in a low level signal through the M6; the P2 low signal can ensure that M6 is completely in the off state, and avoid the influence of the high signal of the subsequent first timing CLK1 on the level signal SN output by the driving circuit.
Similarly, when the point a is a high level signal, M10 is turned on, and the VGL low level signal pulls down the output end of the driving circuit through M10 to output a signal level signal SN, thereby ensuring that the voltage on the gate scan line does not rise.
The dual guarantee of turning on the second output switch M10 and turning off the first output switch keeps the output signal level signal SN at the output terminal of the driving circuit from rising during one cycle of the current CLK3 signal.
When entering the cycle of the next timing sequence CLK signal, the point a of the high level signal of the second timing sequence CLK3 may be a high level signal again, so that M7, M8, M9, and M10 are turned on again, that is, the output signal level signal SN of the output terminal of the driving circuit is pulled to the VGL low level signal again, so that the output signal level signal SN of the output terminal of the driving circuit keeps the low level signal from being raised in the non-on stage, and the calculation is performed in one frame time, as long as the level signal of the second timing sequence CLK3 is a high level signal, the output signal level signal SN of the output terminal of the driving circuit may keep the low level signal, and the reliability of the gate driving circuit is greatly improved.
In a second aspect, as shown in fig. 3, fig. 3 is a schematic diagram of a first embodiment of a gate driving method in the present invention, and a gate driving method using the driving circuit of the first aspect includes: step 100, turning on a first output switch of a gate driving circuit through a high-level input signal; step 200, a level signal holding module 20 is arranged in the gate driving circuit, so that the gate driving circuit holds a low level signal in the second timing high level signal stage.
Preferably, as shown in fig. 4, fig. 4 is a schematic view of a gate driving method according to a second embodiment of the present invention, and step 100 includes: step 110, inputting a normal high level signal and a starting level signal to a starting switch in a normal scanning stage; step 120, outputting a high level signal to the first output switch to start the first output switch.
Preferably, as shown in fig. 5, fig. 5 is a schematic view of a third embodiment of the gate driving method in the present invention, and the step 200 includes: step 210, the gate driving circuit outputs and maintains a high level signal at a first sequence high level signal stage; in step 220, the gate driving circuit outputs and maintains the low level signal at the second timing high level signal stage.
When the high-level signal phase of the first timing CLK1 is asserted, the second output switch M10 is kept in the off state to prevent the output signal level signal SN at the output terminal of the driving circuit from being pulled low.
When the high-level signal stage of the second timing sequence CLK3 is reached, the level signal holding module 20 is entered to ensure that the first output switch M6 is completely turned off, so as to avoid the influence of the high-level signal of the subsequent first timing sequence CLK1 on the level signal SN output by the driving circuit, and to pull down the output signal level signal SN of the driving circuit through the second output switch M10, thereby ensuring that the voltage on the gate scan line is not raised.
The dual guarantee of turning on the second output switch M10 and turning off the first output switch keeps the output signal level signal SN at the output terminal of the driving circuit from rising during one cycle of the current CLK3 signal. Calculated by one frame time, as long as the level signal of the second timing sequence CLK3 is a high level signal, the output signal level signal SN of the output end of the driving circuit can keep a low level signal, and the reliability of the gate driving circuit is greatly improved.
Preferably, as shown in fig. 6, fig. 6 is a schematic diagram of a fourth embodiment of the gate driving method in the present invention, and step 210 includes: step 211, setting the second output switch in the level signal holding module 20 between the first output switch and the low level signal input end; step 212, turning off the second output switch when the first timing high level signal stage outputs the high level signal, so as to keep the high level signal from being pulled down.
Preferably, as shown in fig. 7, fig. 7 is a schematic diagram of a fifth embodiment of the gate driving method in the present invention, and step 220 includes: step 221, outputting a high level signal to a second output switch, and starting the second output switch; step 222, the second output switch outputs a low level signal to the output end of the driving circuit to pull the low level signal; step 223, outputting a low level signal to the first output switch to turn off the first output switch.
According to the gate driving circuit and the method, the level signal holding module 20 is arranged in the gate driving circuit, the second output switch is closed, the driving circuit outputs and holds a high level signal in the first time sequence high level signal stage, and the voltage on a gate scanning line is ensured not to be raised through dual low level signal guarantee in the second time sequence high level signal stage, so that the influence of subsequent time sequence level signals on the output is avoided, and the reliability of the driving circuit is improved.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A gate driving circuit for outputting a driving signal to a panel electrode, comprising:
a drive module;
a level signal holding module;
the driving module is electrically connected with the level signal holding module;
the driving module is used for turning on a switch of the gate driving circuit through a high-level input signal;
the level signal holding module is used for:
keeping the grid drive circuit outputting a high level signal in the first time sequence stage, keeping the high level signal not pulled low,
keeping the gate driving circuit to output a low-level signal in a second time sequence stage, and keeping the low-level signal not to be lifted;
and keeping the low-level signal not to be lifted by closing the first output switch of the driving circuit and starting the second output switch.
2. A gate drive circuit as claimed in claim 1, wherein the drive module comprises:
the first driving switch, the second driving switch, the third driving switch, the fourth driving switch, the fifth driving switch, the first output switch and the filtering unit;
the first driving switch or the second driving switch is used for starting and outputting a high level signal to the third driving switch and the fourth driving switch under the action of a high level signal and an initial signal so as to drive the third driving switch and the fourth driving switch to be started;
the third driving switch is used for outputting a high-level signal to the first output switch so as to drive the first output switch to be switched on;
the filtering unit is used for filtering clutter interference on the input low-level signal;
the first output switch is used for outputting a driving level signal to the panel grid.
3. The gate driving circuit of claim 2, wherein the level signal holding module comprises:
a seventh drive switch, an eighth drive switch, a ninth drive switch, and a second output switch;
the seventh driving switch is used for outputting a high-level signal to the ninth driving switch and the second output switch in a second time sequence stage so as to start the ninth driving switch and the second output switch;
the ninth driving switch is used for outputting a low level signal to the first output switch in a second time sequence stage so as to switch off the first output switch;
the eighth driving switch is used for outputting a low level signal to the first output switch in a second time sequence stage so as to switch off the first output switch;
the second output switch is used for outputting a low level signal to the output end of the driving circuit in a second time sequence stage so as to pull down the output level signal.
4. The gate driving circuit according to claim 3, wherein the first driving switch, the second driving switch, the third driving switch, the fourth driving switch, the fifth driving switch, the first output switch, and the filtering unit are respectively a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a first capacitor;
the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are respectively used for inputting a driving level signal;
the source electrode of the first MOS tube and the drain electrode of the second MOS tube are respectively used for inputting starting level signals of the first MOS tube and the second MOS tube;
the drain electrode of the first MOS tube, the source electrode of the second MOS tube, the source electrode of the third MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube are connected in common to form a first common connection point;
the drain electrode of the third MOS tube, the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube and the first end of the first capacitor are connected in common to form a second common connection point;
the source electrode of the fifth MOS tube, the drain electrode of the fourth MOS tube and the input end of the first capacitor are connected in common;
the second end of the first capacitor is used for inputting a low-level signal;
the drain electrode of the sixth MOS tube is used for inputting the level signal of the first time sequence;
and the source electrode of the sixth MOS tube is used for outputting a driving level signal.
5. The gate driving circuit according to claim 4, wherein the seventh driving switch, the eighth driving switch, the ninth driving switch and the second output switch are respectively a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a tenth MOS transistor;
the grid electrode of the seventh MOS tube is used for inputting a second time sequence level signal, the drain electrode of the seventh MOS tube is used for a high level signal, and the source electrode of the seventh MOS tube is connected with the grid electrode of the eighth MOS tube;
the source electrode of the eighth MOS tube and the drain electrode of the ninth MOS tube are connected with the second common contact point;
the drain electrode of the eighth MOS tube, the source electrode of the ninth MOS tube, the source electrode of the fourth MOS tube, the drain electrode of the fifth MOS tube and the input end of the first capacitor are connected in common;
the grid electrode of the ninth MOS tube and the grid electrode of the tenth MOS tube are connected in common to form a third common connection point;
the source electrode of the tenth MOS tube is connected with the input end of the first capacitor;
and the drain electrode of the tenth MOS tube and the source electrode of the sixth MOS tube are connected with the output end of the driving circuit in a common mode.
6. A gate driving method using the driving circuit according to any one of claims 1 to 5, comprising:
step 100, turning on a first output switch of the gate driving circuit through a high-level input signal;
step 200, a level signal holding module is arranged in the gate driving circuit, so that the gate driving circuit holds a low level signal in a second timing stage.
7. The gate driving method according to claim 6, wherein the step 100 comprises:
step 110, inputting a normal high level signal and a starting level signal to a starting switch in a normal scanning stage;
step 120, outputting a high level signal to the first output switch to start the first output switch.
8. The gate driving method according to claim 7, wherein the step 200 comprises:
step 210, the gate driving circuit outputs and maintains a high level signal at a first sequence high level signal stage;
in step 220, the gate driving circuit outputs and maintains a low level signal at the second timing high level signal stage.
9. A gate driving method according to claim 8, wherein the step 210 comprises:
step 211, setting a second output switch in the level signal holding module between the first output switch and a low level signal input end;
and step 212, turning off the second output switch when the high-level signal is output in the first sequence high-level signal stage, so as to keep the high-level signal from being pulled down.
10. A gate driving method according to claim 9, wherein the step 220 comprises:
step 221, outputting a high level signal to the second output switch, and starting the second output switch;
step 222, the second output switch outputs a low level signal to the output end of the driving circuit to pull the low level signal;
step 223, outputting a low level signal to the first output switch to turn off the first output switch.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210024524.9A CN114333701B (en) | 2022-01-10 | 2022-01-10 | Grid driving circuit and method |
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| CN202210024524.9A CN114333701B (en) | 2022-01-10 | 2022-01-10 | Grid driving circuit and method |
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| CN114333701A true CN114333701A (en) | 2022-04-12 |
| CN114333701B CN114333701B (en) | 2023-03-28 |
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| CN202210024524.9A Active CN114333701B (en) | 2022-01-10 | 2022-01-10 | Grid driving circuit and method |
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562047A (en) * | 2008-04-15 | 2009-10-21 | 北京京东方光电科技有限公司 | Shift register and liquid crystal display grate drive device |
| CN105161134A (en) * | 2015-10-09 | 2015-12-16 | 京东方科技集团股份有限公司 | Shift register unit, operation method for shift register unit and shift register |
| KR20160107916A (en) * | 2015-03-06 | 2016-09-19 | 경희대학교 산학협력단 | Shift register, driving device based on direct current type and method thereof |
| CN106023919A (en) * | 2016-06-30 | 2016-10-12 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
| CN106409259A (en) * | 2016-11-10 | 2017-02-15 | 信利（惠州）智能显示有限公司 | Bidirectional shift register, multistage tandem connection shift registering device and liquid crystal display panel |
| CN107068094A (en) * | 2017-05-10 | 2017-08-18 | 厦门天马微电子有限公司 | Gate driving circuit, display panel, display device and driving method |
| CN107301833A (en) * | 2017-08-24 | 2017-10-27 | 京东方科技集团股份有限公司 | Drive element of the grid and gate driving circuit and its driving method, display device |
| CN109509423A (en) * | 2018-05-28 | 2019-03-22 | 友达光电股份有限公司 | gate drive circuit |
| CN109859698A (en) * | 2018-08-21 | 2019-06-07 | 信利半导体有限公司 | A kind of GOA driving circuit |
| CN110322828A (en) * | 2019-08-23 | 2019-10-11 | 信利（惠州）智能显示有限公司 | Pixel-driving circuit and its driving method and display device |
| CN110459185A (en) * | 2019-07-19 | 2019-11-15 | 信利半导体有限公司 | A kind of GOA driving circuit, driving method and the display device of low noise |
| CN111696493A (en) * | 2020-06-29 | 2020-09-22 | 信利(仁寿)高端显示科技有限公司 | Grid driving circuit and positive and negative scanning grid driving circuit |
| CN112509531A (en) * | 2020-12-04 | 2021-03-16 | 武汉华星光电技术有限公司 | Integrated gate drive circuit and display device |
| CN113851173A (en) * | 2021-09-24 | 2021-12-28 | 京东方科技集团股份有限公司 | Shift register unit, drive control circuit, display device and drive method |
-
2022
- 2022-01-10 CN CN202210024524.9A patent/CN114333701B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562047A (en) * | 2008-04-15 | 2009-10-21 | 北京京东方光电科技有限公司 | Shift register and liquid crystal display grate drive device |
| KR20160107916A (en) * | 2015-03-06 | 2016-09-19 | 경희대학교 산학협력단 | Shift register, driving device based on direct current type and method thereof |
| CN105161134A (en) * | 2015-10-09 | 2015-12-16 | 京东方科技集团股份有限公司 | Shift register unit, operation method for shift register unit and shift register |
| CN106023919A (en) * | 2016-06-30 | 2016-10-12 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, driving circuit and display device |
| CN106409259A (en) * | 2016-11-10 | 2017-02-15 | 信利（惠州）智能显示有限公司 | Bidirectional shift register, multistage tandem connection shift registering device and liquid crystal display panel |
| CN107068094A (en) * | 2017-05-10 | 2017-08-18 | 厦门天马微电子有限公司 | Gate driving circuit, display panel, display device and driving method |
| CN107301833A (en) * | 2017-08-24 | 2017-10-27 | 京东方科技集团股份有限公司 | Drive element of the grid and gate driving circuit and its driving method, display device |
| CN109509423A (en) * | 2018-05-28 | 2019-03-22 | 友达光电股份有限公司 | gate drive circuit |
| CN109859698A (en) * | 2018-08-21 | 2019-06-07 | 信利半导体有限公司 | A kind of GOA driving circuit |
| CN110459185A (en) * | 2019-07-19 | 2019-11-15 | 信利半导体有限公司 | A kind of GOA driving circuit, driving method and the display device of low noise |
| CN110322828A (en) * | 2019-08-23 | 2019-10-11 | 信利（惠州）智能显示有限公司 | Pixel-driving circuit and its driving method and display device |
| CN111696493A (en) * | 2020-06-29 | 2020-09-22 | 信利(仁寿)高端显示科技有限公司 | Grid driving circuit and positive and negative scanning grid driving circuit |
| CN112509531A (en) * | 2020-12-04 | 2021-03-16 | 武汉华星光电技术有限公司 | Integrated gate drive circuit and display device |
| CN113851173A (en) * | 2021-09-24 | 2021-12-28 | 京东方科技集团股份有限公司 | Shift register unit, drive control circuit, display device and drive method |
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| CN114333701B (en) | 2023-03-28 |
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