CN101807436B - Shift register - Google Patents
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- CN101807436B CN101807436B CN 201010158415 CN201010158415A CN101807436B CN 101807436 B CN101807436 B CN 101807436B CN 201010158415 CN201010158415 CN 201010158415 CN 201010158415 A CN201010158415 A CN 201010158415A CN 101807436 B CN101807436 B CN 101807436B
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Abstract
The invention relates to a shift register, which comprises a plurality of transistors. The transistors receive the control of initial pulse signals, first clock pulse signals and second clock pulse signals in order to generate grid driving signals. The first clock pulse signals and the second clock pulse signals are mutual opposite phase. The low level of the first clock pulse signals is different from the low level of the second clock pulse signals. Moreover, each transistor is negative critical voltage transistor. When each transistor is in a cut-off state, the electric potential of the grid of the transistor is less than the electric potential of the source electrode or drain electrode of the transistor. The circuit structure of the shift register can reduce the size of the transistor and power consumption effectively.
Description
Technical field
The present invention relates to the display technique field, relate in particular to a kind of shift registor.
Background technology
In the prior art shift registor is produced on substrate, for example on the glass substrate, the technique that adopts is mainly the amorphous silicon technology technology.Because the carrier mobility of amorphous silicon material is low, therefore need the thin film transistor (TFT) of design large-size, could effectively drive the sweep trace of display panel.Yet the space of the occupied panel of thin film transistor (TFT) that size is larger is also larger, is difficult to design on the limited display panel product of narrow frame or circuit space; And the parasitic capacitance effect that produces is also larger, causes the power consumption on the clock pulse signal line also significantly to rise.Therefore shift registor is produced on the substrate, although can save the cost of gate driver circuit, if the size of thin film transistor (TFT) and power consumption problem are not improved, the application of technique also can limit to some extent.
Therefore, if the semiconductor material of high carrier mobility can be applied in the design of shift registor, then can effectively dwindle the design size of thin film transistor (TFT) and reduce power consumption.Although the semiconductor material of high carrier mobility has larger On current, often also follow larger close current.Take the semiconductor material indium gallium zinc oxide (IGZO) of recent development as example, the carrier mobility of IGZO is about 5 volt per metres second (V/ms), but the critical voltage of the thin film transistor (TFT) of making is about-5V.Therefore, if IGZO is applied to the shift register circuit structure that prior art proposes, can cause a large amount of leakage currents, cause shift registor to lose efficacy.
Summary of the invention
Purpose of the present invention is providing a kind of shift registor, the technological deficiency that exists to overcome prior art exactly.
Therefore, a kind of shift registor that one embodiment of the invention proposes, it comprises a plurality of transistors, accepts the control of initial pulse signals, the first clock pulse signal and second clock pulse signal to produce gate drive signal; Wherein the first clock pulse signal and second clock pulse signal are anti-phase each other, and the low level of the low level of the first clock pulse signal and second clock pulse signal is different.In addition, each transistor is negative critical voltage transistor; And when each transistor was in cut-off state, the current potential of this transistorized grid was less than the current potential of this transistorized source/drain electrode.
In one embodiment of this invention, above-mentioned a plurality of transistors comprise the first transistor, transistor seconds and the 3rd transistor; The grid of the first transistor receives the first clock pulse signal because of electric property coupling relation and the leakage/source electrode by coupling capacitance and the first transistor is electrically connected, the source of the first transistor/drain electrode is electrically coupled to supply voltage, and the level of this supply voltage is higher than the low level of the first clock pulse signal and is lower than the low level of second clock pulse signal; The grid of transistor seconds receives the first clock pulse signal because of the electric property coupling relation, and the source of transistor seconds/drain electrode is electrically coupled to the leakage/source electrode of the first transistor, and the leakage/source electrode of transistor seconds receives initial pulse signals because of the electric property coupling relation; The 3rd transistorized grid is electrically coupled to the leakage/source electrode of the first transistor, and the 3rd transistorized source/drain electrode is in order to exporting gate drive signal, and the 3rd transistorized leakage/source electrode receives the second clock pulse signal because of the electric property coupling relation.
In one embodiment of this invention, the 3rd above-mentioned transistorized source/drain electrode further is electrically coupled to the 3rd transistorized grid by another coupling capacitance.
In one embodiment of this invention, above-mentioned a plurality of transistors also comprise the 4th transistor, wherein the 4th transistorized grid is electrically coupled to the leakage/source electrode of the first transistor, the 4th transistorized source/drain electrode is in order to exporting another initial pulse signals, and the 4th transistorized leakage/source electrode is electrically coupled to the 3rd transistorized leakage/source electrode or source/drain electrode.
In one embodiment of this invention, above-mentioned a plurality of transistors also comprise the 5th transistor, wherein the 5th transistorized grid receives the first clock pulse signal because of the electric property coupling relation, the 5th transistorized source/drain electrode equals the low level of second clock pulse signal because electric property coupling concerns the level that receives second source voltage and this second source voltage, and the 5th transistorized leakage/source electrode is electrically coupled to the 3rd transistorized source/drain electrode.
A kind of shift registor that yet another embodiment of the invention proposes, it comprises control circuit and output circuit; Wherein control circuit receives initial pulse signals, the first clock pulse signal and supply voltage and produces enable signal according to initial pulse signals and the first clock pulse signal because of the electric property coupling relation, and the low level of the first clock pulse signal is lower than the level of supply voltage; Output circuit is accepted the control of enable signal and according to second clock pulse signal genration gate drive signal, and second clock pulse signal and the first clock pulse signal each other low level anti-phase and the second clock pulse signal are higher than the level of supply voltage.
In one embodiment of this invention, above-mentioned control circuit comprises the first control transistor and the second control transistor; Wherein, the transistorized grid of the first control is in order to receive the first clock pulse signal, and first control transistorized source/drain electrode is electrically coupled to supply voltage, and the transistorized leakage/source electrode of the first control is electrically connected by coupling capacitance and the transistorized grid of the first control; The transistorized grid of the second control is electrically coupled to the transistorized grid of the first control, second control transistorized source/drain electrode is electrically coupled to the first transistorized leakage/source electrode of control and in order to the output enable signal, the transistorized leakage/source electrode of the second control is in order to receive initial pulse signals.
In one embodiment of this invention, above-mentioned output circuit comprises the first output transistor, wherein the grid of the first output transistor is in order to receive enable signal, the source of the first output transistor/drain electrode is in order to exporting gate drive signal, and the leakage/source electrode of the first output transistor is in order to receive the second clock pulse signal.
In one embodiment of this invention, above-mentioned output circuit comprises that also the second output transistor is to produce the second initial pulse signals, wherein the grid of the second output transistor is electrically coupled to the grid of the first output transistor, the source of the second output transistor/drain electrode is in order to exporting the second initial pulse signals, and the leakage/source electrode of the second output transistor is electrically coupled to the source of the first output transistor/drain electrode or leakage/source electrode.
In one embodiment of this invention, above-mentioned shift registor also comprises reset circuit, wherein the reset circuit control that receives the first clock pulse signal is pulled to second source voltage with the current potential with the output terminal of the gate drive signal of output circuit, and the level of second source voltage equals the low level of second clock pulse signal.
A kind of shift registor that another embodiment of the present invention proposes, it comprises control circuit and the first output transistor; Wherein, control circuit has initial pulse signals input end, the first clock pulse signal input end and supply voltage input end, and comprises the first control transistor and the second control transistor; The transistorized grid of the first control is electrically coupled to the first clock pulse signal input end, first control transistorized source/drain electrode is electrically coupled to the supply voltage input end, and the transistorized leakage/source electrode of the first control is electrically connected by coupling capacitance and the transistorized grid of the first control; The transistorized grid of the second control is electrically coupled to the first clock pulse signal input end, second control transistorized source/drain electrode is electrically coupled to the transistorized leakage/source electrode of the first control, and the transistorized leakage/source electrode of the second control is electrically coupled to the initial pulse signals input end; The grid of the first output transistor is electrically coupled to the transistorized leakage/source electrode of the first control, and the source of the first output transistor/drain electrode is as the gate drive signal output terminal, and the leakage/source electrode of the first output transistor is as the second clock pulse signal input terminal.In addition, the first control transistor, the second control transistor and the first output transistor all are negative critical voltage transistors.
In one embodiment of this invention, the source of the first above-mentioned output transistor/drain electrode further is electrically connected by the grid of coupling capacitance and the first output transistor.
In one embodiment of this invention, above-mentioned shift registor also comprises the second output transistor, wherein the grid of the second output transistor is electrically coupled to the transistorized leakage/source electrode of the first control of control circuit, the source of the second output transistor/drain electrode is as the initial pulse signals output terminal, and the leakage/source electrode of the second output transistor is electrically coupled to gate drive signal output terminal or second clock pulse signal input terminal, and the second output transistor is negative critical voltage transistor.
In one embodiment of this invention, above-mentioned shift registor also comprises reset transistor, wherein the grid of reset transistor is electrically coupled to the first clock pulse signal input end of control circuit, the source of reset transistor/drain electrode is as another supply voltage input end, and the leakage/source electrode of reset transistor is electrically coupled to the gate drive signal output terminal, and reset transistor is negative critical voltage transistor.
The embodiment of the invention is carried out particular design by circuit structure and operating process thereof to shift registor, but so that still normal running after the semiconductor material of each transistor employing high carrier mobility of shift registor, to such an extent as to the circuit structure of the shift registor that the embodiment of the invention proposes can be reached the effect of effectively dwindling transistor size and reduction power consumption.
For above and other purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Fig. 1 is the circuit structure diagram that is relevant to a kind of shift registor of first embodiment of the invention.
Fig. 2 is the sequential chart that is relevant to a plurality of signals of first embodiment of the invention.
Fig. 3 is the circuit structure diagram that is relevant to the another kind of shift registor of first embodiment of the invention.
Fig. 4 is the circuit structure diagram that is relevant to a kind of shift registor of second embodiment of the invention.
Wherein, description of reference numerals is as follows:
10,20: shift registor
12,22: control circuit
14,24: output circuit
T11, T21, T22, T41, T31: transistor
Cc, Cb: coupling capacitance
26: reset circuit
ST (n-1), ST (n): initial pulse signals
XCK, CK: clock pulse signal
VSS, VSS1, VSS2: supply voltage
Q (n): enable signal
G (n): gate drive signal
Embodiment
Referring to Fig. 1, it illustrates the circuit structure diagram of a kind of shift registor that is relevant to the first embodiment of the invention proposition.As shown in Figure 1, shift registor 10 comprises control circuit 12 and output circuit 14.In this explanation be, the shift registor of a plurality of grades of coupled in series can form a gate driver circuit (not shown), gate driver circuit (Gate Driver On Array on the array for example, and the shift registor 10 of the present embodiment can be any one-level in the shift registor of these grades coupled in series GOA).
Particularly, control circuit 12 comprises transistor T 11, T41 and coupling capacitance Cc, and transistor T 11, T41 are negative critical voltage transistor, for example is the transistor that adopts the semiconductor material of high carrier mobility.Wherein, the grid of transistor T 41 as the clock pulse signal input end with receive clock pulse signal XCK, the source of transistor T 41/drain electrode is electrically coupled to supply voltage VSS with as the supply voltage input end, and the leakage/source electrode of transistor T 41 is electrically connected as the output terminal of enable signal Q (n) and the grid by coupling capacitance Cc and transistor T 41; The grid of the grid of transistor T 11 and transistor T 41 is electrically connected to accept the control of clock pulse signal XCK, the source of transistor T 11/drain electrode is electrically coupled to the leakage/source electrode of transistor T 41, the leakage/source electrode of transistor T 11 as the initial pulse signals input end to receive initial pulse signals ST (n-1).
At this, need to prove, when shift registor 10 during as the afterbody in the shift registor of a plurality of grades of coupled in series, transistor T 22 can be set in output circuit 14 usually produce initial pulse signals ST (n); In addition, those skilled in the art also can according to the consideration in when design, dispense coupling capacitance Cb.
Specifically describe the operating process of the shift registor 10 that is relevant to first embodiment of the invention below in conjunction with Fig. 1 and Fig. 2, Fig. 2 illustrates initial pulse signals ST (n-1), clock pulse signal XCK, the sequential chart of CK, gate drive signal G (n) and enable signal Q (n); At this, clock pulse signal XCK and clock pulse signal CK are anti-phase each other, and also namely when time clock signal XCK is high level, clock pulse signal CK is low level, otherwise when time clock signal CK was high level, clock pulse signal XCK was low level; And, the low level of clock pulse signal XCK is lower than the level of supply voltage VSS, and the low level of clock pulse signal CK is higher than the level of supply voltage VSS, to such an extent as to each negative critical voltage transistor T 11, T41, T21 and T22 are under cut-off state, the current potential of its grid is lower than the current potential of its source/leakage to realize less pass electric current.
Particularly, when initial pulse signals ST (n-1) and clock pulse signal XCK are high level, clock pulse signal CK is low level, transistor T 11 in the control circuit 12 and T41 conducting, enable signal Q (n) is drawn high to preset potential and to the coupling capacitance Cb in the output circuit 14 to charge so that the transistor T 21 in the output circuit 14, T22 conducting.Next, initial pulse signals ST (n-1) is low level with the equal saltus step of clock pulse signal XCK, because the low level of clock pulse signal XCK is lower than the level of supply voltage VSS, transistor T 11 and T41 in the control circuit effectively end, and the level of enable signal Q (n) is dragged down a little because of the reverse coupled effect of coupling capacitance Cc.
Afterwards, clock pulse signal CK is high level by low transition, the source of the transistor T 21 in the output circuit 14/drain electrode is exported gate drive signal G (n) (also being gate driving pulse) according to the clock pulse signal CK of input, simultaneously, the source of the transistor T 22 in the output circuit 14/drain electrode is exported initial pulse signals ST (n) with the initial pulse signals as rear one-level shift registor according to the clock pulse signal CK of input; At this moment, the level of enable signal Q (n) is further raised because of the consecutive characteristic of the both end voltage of coupling capacitance Cb, thereby so that the electric current of opening of transistor T 21 increase.Next, clock pulse signal CK saltus step is low level, and the current potential of the source of transistor T 21, T22/drain electrode all is pulled low to the low level of clock pulse signal CK and equates.
Then, clock pulse signal XCK saltus step is high level, transistor T 11 in the control circuit 12, T41 conducting, enable signal Q (n) is discharged to supply voltage VSS by transistor T 41, to such an extent as to the current potential of the transistor T 21 in the output circuit 14, the grid of T22 all is lower than the current potential of its source/drain electrode, so that transistor T 21, T22 are effectively ended.Next, clock pulse signal XCK saltus step is low level, because of the reverse coupled effect of coupling capacitance Cc, so that enable signal Q (n) is pulled to more low level.Afterwards, as time clock signal CK when saltus step is high level again, the level of enable signal Q (n) can beyond supply voltage VSS, to such an extent as to the transistor T 21 in the output circuit 14, T22 can remain on effective cut-off state.
In addition, the circuit structure of the shift registor 10 of first embodiment of the invention is not limited to shown in Figure 1, also can adopt other circuit structures for example shown in Figure 3.Particularly, the circuit structure of shift registor 10 shown in Figure 3 and shift registor 10 shown in Figure 1 are basic identical, difference is: the leakage/source electrode of the transistor T 22 among Fig. 3 is electrically coupled to the source of transistor T 21/drain electrode, but not the leakage/source electrode that is electrically coupled to transistor T 21 as shown in Figure 1 and direct receive clock pulse signal CK.
Referring to Fig. 4, it illustrates the circuit structure diagram of a kind of shift registor that is relevant to the second embodiment of the invention proposition.As shown in Figure 4, shift registor 20 comprises control circuit 22, output circuit 24 and reset circuit 26.In this explanation be, the shift registor of a plurality of grades of coupled in series can form a gate driver circuit (not shown), gate driver circuit on the array for example, and the shift registor 20 of the present embodiment can be any one-level in the shift registor of these grades coupled in series.
Particularly, control circuit 22 comprises transistor T 11, T41 and coupling capacitance Cc, and transistor T 11, T41 are negative critical voltage transistor, for example is the transistor that adopts the semiconductor material of high carrier mobility.Wherein, the grid of transistor T 41 as the clock pulse signal input end with receive clock pulse signal XCK, the source of transistor T 41/drain electrode is electrically coupled to supply voltage VSS1 with as the supply voltage input end, and the leakage/source electrode of transistor T 41 is electrically connected as the output terminal of enable signal Q (n) and the grid by coupling capacitance Cc and transistor T 41; The grid of the grid of transistor T 11 and transistor T 41 is electrically connected to accept the control of clock pulse signal XCK, the source of transistor T 11/drain electrode is electrically coupled to the leakage/source electrode of transistor T 41, the leakage/source electrode of transistor T 11 as the initial pulse signals input end to receive initial pulse signals ST (n-1).
In second embodiment of the invention, for so that each negative critical voltage transistor T 11, T41, T21, T22 and T31 under cut-off state, the current potential of its grid is lower than the current potential of its source/leakage to realize less pass electric current, clock pulse signal CK and XCK are set to anti-phase each other, the low level that the level of supply voltage VSS1 is set to be higher than the low level of clock pulse signal XCK and is lower than clock pulse signal CK, the level of supply voltage VSS2 is set to equal the low level of clock pulse signal CK.
At this, need to prove, the operating process of the shift registor 10 among shift registor 20 and the first embodiment is roughly the same, therefore do not repeat them here.In addition, when shift registor 20 during as the afterbody in the shift registor of a plurality of grades of coupled in series, transistor T 22 can be set in output circuit 24 usually produce initial pulse signals ST (n); In addition, those skilled in the art also can according to the consideration in when design, dispense coupling capacitance Cb.
In sum, the embodiment of the invention is carried out particular design by circuit structure and operating process thereof to shift registor, so that each transistor of shift registor is negative critical voltage transistor, but for example be still normal running when adopting the transistor of semiconductor material of high carrier mobility, to such an extent as to the circuit structure of the shift registor that the embodiment of the invention proposes can be reached the effect of effectively dwindling transistor size and reducing power consumption.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defines.
Claims (11)
1. shift registor comprises:
A plurality of transistors, accept the control of an initial pulse signals, one first clock pulse signal and a second clock pulse signal to produce a gate drive signal, this first clock pulse signal and this second clock pulse signal are anti-phase each other, and the low level of the low level of this first clock pulse signal and this second clock pulse signal is different;
Wherein, described a plurality of transistors are negative critical voltage transistor, and in described a plurality of transistor each is when being in cut-off state, and the current potential of this transistorized grid is less than one current potential in this transistorized source and the drain electrode;
Wherein said a plurality of transistor comprises:
One the first transistor, one of receiving in this first clock pulse signal and the leakage by a coupling capacitance and this first transistor and the source electrode because of electric property coupling relation is electrically connected this grid of this first transistor, in this source of this first transistor and the drain electrode another is electrically coupled to a supply voltage, and the level of this supply voltage is higher than this low level of this first clock pulse signal and is lower than this low level of this second clock pulse signal;
One transistor seconds, this grid of this transistor seconds receives this first clock pulse signal because of the electric property coupling relation, in this leakages that is electrically coupled to this first transistor in this source of this transistor seconds and the drain electrode and the source electrode one, and the leakage of this transistor seconds and in the source electrode another receive this initial pulse signals because electric property coupling concerns; And
One the 3rd transistor, the 3rd transistorized this grid is electrically coupled in this leakage of this first transistor and the source electrode, one in the 3rd transistorized this source and the drain electrode in order to exporting this gate drive signal, and in the 3rd transistorized leakage and the source electrode another receives this second clock pulse signal because of the electric property coupling relation.
2. shift registor as claimed in claim 1, wherein another in the 3rd transistorized this source and the drain electrode further is electrically coupled to the 3rd transistorized this grid by another coupling capacitance.
3. shift registor as claimed in claim 1, wherein said a plurality of transistors also comprise:
One the 4th transistor, the 4th transistorized this grid is electrically coupled to this leakage of this first transistor and of source electrode, one in the 4th transistorized this source and the drain electrode in order to exporting another initial pulse signals, and in the 4th transistorized leakage and the source electrode another be electrically coupled in the 3rd transistorized this leakage and the source electrode another or this source with drain in one.
4. shift registor as claimed in claim 1, wherein said a plurality of transistors also comprise:
One the 5th transistor, the 5th transistorized this grid receives this first clock pulse signal because of the electric property coupling relation, in the 5th transistorized this source and the drain electrode one level that receives a second source voltage and this second source voltage because of electric property coupling relation equals this low level of this second clock pulse signal, and another in the 5th transistorized leakage and the source electrode is electrically coupled in the 3rd transistorized this source and the drain electrode.
5. shift registor comprises:
One control circuit, this control circuit receives an initial pulse signals, one first clock pulse signal and a supply voltage and produces an enable signal according to this initial pulse signals and this first clock pulse signal because of the electric property coupling relation, and wherein the low level of this first clock pulse signal is lower than the level of this supply voltage; And
One output circuit, this output circuit is accepted the control of this enable signal and according to a second clock pulse signal genration one gate drive signal, wherein this second clock pulse signal and this first clock pulse signal each other low level anti-phase and this second clock pulse signal be higher than this level of this supply voltage;
Wherein this control circuit comprises:
One first control transistor, the transistorized grid of this first control is in order to receive this first clock pulse signal, one in this first transistorized source of control and the drain electrode is electrically coupled to this supply voltage, and another in this first transistorized leakage of control and the source electrode is electrically connected by a coupling capacitance and transistorized this grid of this first control; And
One second control transistor, the transistorized grid of this second control is electrically coupled to transistorized this grid of this first control, in this second transistorized this source of control and the drain electrode one be electrically coupled in this first control transistorized this leakage and source electrode another and in order to exporting this enable signal, this second controls in transistorized leakage and the source electrode another in order to receive this initial pulse signals;
Wherein this output circuit comprises one first output transistor, the grid of this first output transistor is in order to receive this enable signal, one in the source of this first output transistor and the drain electrode in order to exporting this gate drive signal, and the leakage of this first output transistor and in the source electrode another are in order to receive this second clock pulse signal.
6. shift registor as claimed in claim 5, wherein this output circuit comprises that also one second output transistor is to produce one second initial pulse signals, the grid of this second output transistor is electrically coupled to this grid of this first output transistor, one in the source of this second output transistor and the drain electrode in order to exporting this second initial pulse signals, and the leakage of this second output transistor and in the source electrode another are electrically coupled in this source of this first output transistor and the drain electrode one maybe another in this leakage and the source electrode.
7. shift registor as claimed in claim 5 also comprises:
One reset circuit, the control that this reset circuit receives this first clock pulse signal is pulled to a second source voltage with the current potential with the output terminal of this gate drive signal of this output circuit, and the level of this second source voltage equals this low level of this second clock pulse signal.
8. shift registor comprises:
One control circuit has an initial pulse signals input end, one first clock pulse signal input end and a supply voltage input end, and this control circuit comprises:
One first control transistor, the transistorized grid of this first control is electrically coupled to this first clock pulse signal input end, one in this first transistorized source of control and the drain electrode is electrically coupled to this supply voltage input end, and in this first control transistorized leakage and source electrode another first controlled transistorized this grid and be electrically connected by a coupling capacitance and this; And
One second control transistor, the transistorized grid of this second control is electrically coupled to this first clock pulse signal input end, in this second transistorized source of control and the drain electrode one is electrically coupled to another in this first control transistorized this leakage and source electrode, and this second is controlled in transistorized leakage and the source electrode another and be electrically coupled to this initial pulse signals input end; And
One first output transistor, the grid of this first output transistor is electrically coupled to another in this first transistorized this leakage of control and the source electrode, one in the source of this first output transistor and the drain electrode as a gate drive signal output terminal, and the leakage of this first output transistor and in the source electrode another are as a second clock pulse signal input terminal;
Wherein, this first control transistor, this second control transistor and this first output transistor all are negative critical voltage transistors, and this first clock pulse signal and this second clock pulse signal are anti-phase each other.
9. shift registor as claimed in claim 8, wherein in this source of this first output transistor and the drain electrode further is electrically connected by this grid of another coupling capacitance and this first output transistor.
10. shift registor as claimed in claim 8, also comprise one second output transistor, the grid of this second output transistor is electrically coupled to another in this first control transistorized this leakage and source electrode of this control circuit, one in the source of this second output transistor and the drain electrode as an initial pulse signals output terminal, and the leakage of this second output transistor and in the source electrode another are electrically coupled to this gate drive signal output terminal or this second clock pulse signal input terminal, and this second output transistor is a negative critical voltage transistor.
11. shift registor as claimed in claim 8, also comprise a reset transistor, the grid of this reset transistor is electrically coupled to this first clock pulse signal input end of this control circuit, one in the source of this reset transistor and the drain electrode as another supply voltage input end, and the leakage of this reset transistor and in the source electrode another are electrically coupled to this gate drive signal output terminal, and this reset transistor is a negative critical voltage transistor.
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| CN 201010158415 CN101807436B (en) | 2010-03-31 | 2010-03-31 | Shift register |
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| TWI544474B (en) * | 2014-11-19 | 2016-08-01 | 友達光電股份有限公司 | Shift register |
| CN107016972B (en) * | 2017-04-25 | 2019-08-02 | 深圳市华星光电技术有限公司 | GOA driving circuit and liquid crystal display panel |
| US10347203B2 (en) | 2017-04-25 | 2019-07-09 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | GOA drive circuit and liquid crystal display panel |
| CN109509459B (en) * | 2019-01-25 | 2020-09-01 | 深圳市华星光电技术有限公司 | GOA circuit and display device |
| CN111710286B (en) * | 2020-06-30 | 2023-01-24 | 上海中航光电子有限公司 | Display panel, driving control method thereof and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3965369A (en) * | 1972-08-25 | 1976-06-22 | Hitachi, Ltd. | MISFET (Metal-insulator-semiconductor field-effect transistor) logical circuit having depletion type load transistor |
| US4568842A (en) * | 1983-01-24 | 1986-02-04 | Tokyo Shibaura Denki Kabushiki Kaisha | D-Latch circuit using CMOS transistors |
| US4667339A (en) * | 1983-12-05 | 1987-05-19 | Texas Instruments Incorporated | Level sensitive latch stage |
| US5930323A (en) * | 1997-08-26 | 1999-07-27 | Texas Instruments Incorporation | Ultra fast shift register using resonant tunnel diodes |
| KR100583318B1 (en) * | 2003-12-17 | 2006-05-25 | 엘지.필립스 엘시디 주식회사 | Appartus and Method of Driving Liquid Crystal Display |
| US7286627B2 (en) * | 2005-07-22 | 2007-10-23 | Wintek Corporation | Shift register circuit with high stability |
| CN101083139A (en) * | 2006-06-02 | 2007-12-05 | 株式会社半导体能源研究所 | Liquid crystal display device and electronic device |
| CN101292300A (en) * | 2005-10-21 | 2008-10-22 | 惠普开发有限公司 | Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers |
-
2010
- 2010-03-31 CN CN 201010158415 patent/CN101807436B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3965369A (en) * | 1972-08-25 | 1976-06-22 | Hitachi, Ltd. | MISFET (Metal-insulator-semiconductor field-effect transistor) logical circuit having depletion type load transistor |
| US4568842A (en) * | 1983-01-24 | 1986-02-04 | Tokyo Shibaura Denki Kabushiki Kaisha | D-Latch circuit using CMOS transistors |
| US4667339A (en) * | 1983-12-05 | 1987-05-19 | Texas Instruments Incorporated | Level sensitive latch stage |
| US5930323A (en) * | 1997-08-26 | 1999-07-27 | Texas Instruments Incorporation | Ultra fast shift register using resonant tunnel diodes |
| KR100583318B1 (en) * | 2003-12-17 | 2006-05-25 | 엘지.필립스 엘시디 주식회사 | Appartus and Method of Driving Liquid Crystal Display |
| US7286627B2 (en) * | 2005-07-22 | 2007-10-23 | Wintek Corporation | Shift register circuit with high stability |
| CN101292300A (en) * | 2005-10-21 | 2008-10-22 | 惠普开发有限公司 | Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers |
| CN101083139A (en) * | 2006-06-02 | 2007-12-05 | 株式会社半导体能源研究所 | Liquid crystal display device and electronic device |
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| CN101807436A (en) | 2010-08-18 |
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