CN114330186A - Front-end chip of data transmission system - Google Patents

Abstract

The invention relates to a front-end chip of a data transmission system. The chip comprises receiving, transmitting, controlling and switching circuits. The receiving circuit operates at a first voltage and receives a first data signal. The transmitting circuit operates at a first voltage. In a normal mode of the chip, the control circuit operates at a second voltage and is used for generating a second data signal to the transmitting circuit according to the first data signal. The control circuit includes a clock source for providing a clock signal in a normal mode, wherein the control circuit operates according to the clock signal. In the normal mode, the switching circuit operates at a first voltage and is used for controlling a second voltage to be temporarily stopped from being supplied to the control circuit so that the chip enters a sleep mode of the chip. The switching circuit also controls a second voltage to be supplied to the control circuit according to the first data signal in the sleep mode so that the chip returns to the normal mode. The first voltage is higher than the second voltage.

Description

Front-end chip of data transmission system

Technical Field

The present invention relates to a chip, and more particularly, to a chip that operates in a general mode or a sleep mode according to a received signal.

Background

In the prior art, because many input/output devices have cost considerations, the transmission interface of the input/output device only uses one transmission protocol for communication, so that an additional front-end chip is generally used to convert the transmission protocol or expand the number of input/output ports according to the application of the system. However, the widespread application of front-end chips often causes the overall power consumption of the system to increase, which is a problem to be solved in the field.

Disclosure of Invention

The application provides a chip for reducing power consumption of a data transmission system, which comprises an analog receiving circuit, an analog transmitting circuit, a digital control circuit and a switching circuit. The analog receiving circuit operates at a first reference voltage and is used for receiving a first data signal. The analog transmission circuit operates at a first reference voltage. In a normal mode of the chip, the digital control circuit operates at a second reference voltage and is used for generating a second data signal to the analog transmission circuit according to the first data signal. The digital control circuit includes a first clock pulse source. The first clock pulse source is used for providing a first clock pulse signal in a normal mode, wherein the digital control circuit operates according to the first clock pulse signal. In a normal mode of the chip, the switching circuit operates at the first reference voltage, and the switching circuit is used for controlling the second reference voltage to suspend being supplied to the digital control circuit so as to enable the chip to enter a sleep mode of the chip. The switching circuit also controls a second reference voltage to be supplied to the digital control circuit to return to a normal mode in the sleep mode according to the first data signal. The first reference voltage is higher than the second reference voltage.

The application provides a chip for reducing power consumption of a data transmission system, which comprises a digital control circuit and a switching circuit. In a normal mode of the chip, the digital control circuit operates at a first reference voltage. The digital control circuit includes a first clock pulse source. The first clock pulse source is used for generating a first clock pulse signal, and the digital control circuit is used for operating according to the first clock pulse signal. The switching circuit operates at the second reference voltage, wherein when the chip is in a normal mode, the switching circuit is used for controlling the first reference voltage to be temporarily stopped from being supplied to the digital control circuit so as to enable the chip to enter a sleep mode of the chip. And when the chip is in the sleep mode, the switching circuit controls the first reference voltage to be supplied to the digital control circuit according to the hot plug signal so as to enable the chip to return to the normal mode. The second reference voltage is higher than the first reference voltage. The hot plug signal is generated by connecting the chip to the electronic device.

The chip of the application can reduce the whole power consumption of the chip in the sleep mode and maintain the function of awakening the chip from the sleep mode back to the common mode.

Drawings

The various forms of the present application will be better understood when read in conjunction with the following description and the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features of the drawings are not drawn to scale. In fact, the dimensions of some of the features may be exaggerated or minimized intentionally for clarity of illustration.

Fig. 1 is a schematic diagram of a data transmission system according to some embodiments.

Fig. 2 is a schematic diagram of a front-end chip for a data transmission system according to some embodiments.

Fig. 3 is a schematic diagram of a data transmission system according to another embodiment.

Fig. 4 is a schematic diagram of a data transmission system according to another embodiment.

Detailed Description

Please refer to fig. 1. In the data transmission system 10 of the present application, the front-end chip 200 can be switched between the normal mode and the sleep mode, and the front-end chip 200 can be switched to the sleep mode when idle to reduce power consumption. The details thereof are explained below.

The data transmission system 10 includes a transmission device 100, a front-end chip 200 and a receiving device 300. The front-end chip 200 is coupled between the transmitting device 100 and the receiving device 300. When the communication protocol used by the receiving device 300 is different from the communication protocol used by the transmitting device 100, the front-end chip 200 converts the format of the signal so that the receiving device 300 can receive the signal from the transmitting device 100.

In the present embodiment, the front-end chip 200 includes interfaces for transmitting high-speed signals and low-speed signals with the transmitting device 100 and the receiving device 300. As shown in fig. 1, the high-speed signal includes a data signal S1 transmitted through a channel CH1a between the transmission device 100 and the front-end chip 200, and a data signal S2 transmitted through a channel CH1b between the reception device 300 and the front-end chip 200. The low-speed signal includes an auxiliary signal AS1 transmitted through a channel CH2a between the transmitting device 100 and the front-end chip 200, and an auxiliary signal AS2 transmitted through a channel CH2b between the receiving device 300 and the front-end chip 200. The low-speed signal also includes a hot plug signal HS generated when the receiving device is connected to the chip 200. The hot plug signal HS is transmitted over channel CH3a and channel CH3 b.

For example, the transmission device 100 is a personal computer using only a High Definition Multimedia Interface (HDMI) transmission protocol, and the reception device 300 is a screen using only a displayport (dp) transmission protocol. When the screen is connected to the front-end chip 200, a hot plug signal HS is generated and transmitted to the front-end chip 200. Then, the front-end chip 200 transmits a hot plug signal HS to the personal computer to notify that the screen is connected. The personal computer then transmits the HDMI data signal S1 including the display content to the front-end chip 200, and the front-end chip 200 converts the HDMI signal S1 into a data signal S2 of the DP transmission protocol to transmit to the screen, so that the screen can receive the data signal S2 and present the display content.

As another example, the auxiliary signals (e.g., AS1, AS2) are used to communicate the transmission speed of the high-speed signals (e.g., S1, S2) with other information under a particular communication protocol. Generally, the devices (e.g., 100, 300) cannot determine the transmission protocol through the channel of the auxiliary signal (i.e., CH2a, CH2 b). In some embodiments, the screen is connected to the computer through the front-end chip 200 and generates a hot plug signal HS to the computer, the computer and the screen auxiliary signal adjust the high-speed signal (e.g., determine the transmission speed or the number of transmission channels), and the computer sends the high-speed signal (including the display content) to the screen through the high-speed channel. In some embodiments, the auxiliary signal AS1 and the auxiliary signal AS2 are also referred to AS sideband (sideband) signals.

The front-end chip 200 includes an analog receiving circuit 201, an analog transmitting circuit 202, a digital control circuit 220 and a switching circuit 240. The analog receiving circuit 201 is used for transmitting a data signal S1 and an auxiliary signal AS1, and the analog transmitting circuit 202 is used for transmitting a data signal S2 and an auxiliary signal AS2, wherein the analog receiving circuit 201 and the analog transmitting circuit 202 belong to a physical layer (physical layer) of the front-end chip 200. The digital control circuit 220 is coupled between the analog receiving circuit 201 and the analog transmitting circuit 202, and is used for converting the data signal S1 into the data signal S2, and for converting the auxiliary signal AS1 into the auxiliary signal AS2 or converting the auxiliary signal AS2 into the auxiliary signal AS 1. The digital control circuit 220 is further configured to directly receive the hot plug signal HS. In other words, the hot plug signal HS is not transmitted through the analog receiving circuit 201 and the analog transmitting circuit 202.

The switch circuit 240 is coupled to control the analog receiving circuit 201, the analog transmitting circuit 202 and the digital control circuit 220 to operate in a normal mode or a sleep mode. In the normal mode, the data signal S1 is continuously transmitted to the front-end chip 200, and the functions and power supplies of the analog receiving circuit 201, the analog transmitting circuit 202 and the digital control circuit 220 are all turned on completely to convert the data signal S1 and generate the data signal S2. When no signal is transmitted into the front-end chip 200 (i.e., idle), the switching circuit 240 controls the analog receiving circuit 201, the analog transmitting circuit 202 and the digital control circuit 220 to enter a sleep mode, so that the power supply of the digital control circuit 220 is completely stopped. The switch circuit 240 determines whether to leave the sleep mode according to at least one of the data signal S1, the auxiliary signal AS1, the auxiliary signal AS2, and the hot plug signal HS.

In the data transmission system 10, the front-end chip 200 operates at a reference voltage VDD1 and a reference voltage VDD2, wherein the reference voltage VDD1 (Core Power, which may be about 1.0V or 1.1V in some embodiments) is lower than the reference voltage VDD2 (Pad Power, which may be about 3.3V in some embodiments). The digital control circuit 220 operates entirely at the reference voltage VDD1, and the switching circuit 240 operates at the reference voltage VDD 2. In other words, when the reference voltage VDD1 is suspended from being supplied to the digital control circuit 220, the digital control circuit 220 is completely turned off. The analog receiving circuit 201 includes a first portion 201_1 and a second portion 201_ 2; the analog transmission circuit 202 includes a first portion 202_1 and a second portion 202_ 2. Wherein the first portion 201_1 and the first portion 202_1 operate at the reference voltage VDD2 (i.e., the pin voltage); the second portion 201_2 and the second portion 202_2 operate at a reference voltage VDD1 (i.e., a core voltage). The reference voltage VDD2 is used to provide power for the first portion 201_1 to receive the data signal S1 and the auxiliary signal AS1 from the transmitting device 100, and for the first portion 202_1 to receive the auxiliary signal AS2 from the receiving device 300 or transmit the data signal S2 and the auxiliary signal AS2 to the receiving device 300. The reference voltage VDD1 is used to provide power so that the second portion 201_2 can transmit the data signal S1 and the auxiliary signal AS1 to the digital control circuit 220, or can receive the auxiliary signal AS1 from the digital control circuit 220; the reference voltage VDD1 is used to provide power to enable the second portion 202_2 to receive the data signal S2 and the auxiliary signal AS2 from the control circuit 220 or transmit the auxiliary signal AS2 to the digital control circuit 220. The switching circuit 240 is used to control whether the reference voltage VDD1 (i.e., the core voltage) is supplied to the digital control circuit 220 for switching between the normal mode and the sleep mode. The details of the flow are described below.

Please refer to fig. 2. The digital control circuit 220 in the front-end chip 200 includes a processing unit 221, a clock source 222, a signal conversion unit 223, an auxiliary control unit 224 and a hot plug detector 225, and the switch circuit 240 in the front-end chip 200 includes a signal detector 241, a processing unit 242, a clock source 243, a storage unit 244, a level shifter 245 and a reset device 246.

In the normal mode, the clock source 222 generates a clock signal CLK1 and provides it to the processing unit 221. The clock signal CLK1 is a high-speed clock signal, such as but not limited to a high-speed clock signal having a frequency on the order of megahertz (MHz). The processing unit 221 controls the signal conversion unit 223 (not shown in connection) to convert the received data signal S1 into the data signal S2 according to the clock signal CLK1, and controls the auxiliary control unit 224 (not shown in connection) to transmit the auxiliary signal AS1 and the auxiliary signal AS 2. The processing unit 221 further controls the hot plug detector 225 to receive and transmit a hot plug signal HS.

In the sleep mode, the reference voltage VDD1 stops being supplied to the digital control circuit 220, so the clock source 222 stops generating the clock signal CLK1 to stop the operation of the processing unit 221. In some embodiments, the processing unit 221 and the clock source 222 are the most power consuming components of the front-end chip 200. Thus, when the digital control circuit 220 is completely turned off, the power consumption of the front-end chip 200 may be greatly reduced, for example, from a milliwatt (mW) level to a microwatt (μ W) level.

In the switching circuit 240, the processing unit 242 is coupled to the signal detector 241, the clock source 243, the storage unit 244 and the level shifter 245, and the level shifter 245 is further coupled to the reset 246. In the present application, the reference voltage VDD2 is continuously supplied to the front-end chip 200 in both the normal mode and the sleep mode, so the switching circuit 240 in the front-end chip 200 does not stop operating due to switching to the sleep mode.

The clock source 243 generates a clock signal CLK2 and provides it to the processing unit 242. The clock signal CLK2 is a low-speed clock signal, such as but not limited to a low-speed clock signal having a frequency in the order of kilohertz (KHz). In other words, the clock pulse signal CLK2 has a lower frequency than the clock pulse signal CLK 1. Generally, the power consumption is greater for generating the higher frequency clock pulses. Thus, the power consumption of clock source 243 is lower than the power consumption of clock source 222.

In the normal mode, the processing unit 242 controls the level shifter 245 according to the lower speed clock signal CLK2, so that the level shifter 245 shifts the operation information OD1 transmitted from the digital control circuit 220 from the voltage domain of the reference voltage VDD1 to the voltage domain of the reference voltage VDD 2. The converted operation information OD2 is stored in the storage unit 244. Since the digital control circuit 220 continues to operate in the normal mode, the level shifter 245 continues to shift the operation information OD1 and update the operation information OD2 stored in the storage unit 244. In some embodiments, storage unit 244 may be implemented using a register latch module (register latch), but is not limited thereto.

When the front-end chip 200 is to be switched from the normal mode to the sleep mode, the digital control circuit 220 notifies the processing unit 242 in the switching circuit 240 to perform mode switching. More specifically, the digital control circuit 220 transmits the operation information OD1 with the sleep information SD1 to the level shifter 245, and the level shifter 245 converts the operation information OD1 into the operation information OD2 (the content of which is the same as the operation information OD 1) and stores the operation information OD2 in the storage unit 244, so that the processing unit 242 can perform the operation of switching from the normal mode to the sleep mode according to the sleep information SD1 (included in the operation information OD 2) in the storage unit 244. In some embodiments, this may be implemented by transmitting a LOCK signal LOCK and an UNLOCK signal UNLOCK.

In some embodiments, the digital control circuit 220 is connected to the level shifter 245 by at least two channels, a first channel is used for transmitting information including the UNLOCK signal UNLOCK, and a second channel is used for transmitting information other than the UNLOCK signal UNLOCK in the operation information OD1, but not limited thereto. After the processing unit 242 accesses the sleep information SD1 (via the storage unit 244), the processing unit 242 may transmit the LOCK signal LOCK to the level shifter 245, so that the level shifter 245 closes the second channel, and the level shifter 245 will not receive the information other than the UNLOCK signal UNLOCK, so that the information other than the UNLOCK signal UNLOCK in the operation information OD2 is not updated. This is to prevent the level shifter 245 from receiving the unknown signal from the corresponding block circuit of the reference voltage VDD1 after the reference voltage VDD1 is turned off.

Subsequently, the processing unit 242 generates the reset signal RS1 and the reset signal RS2 to be transmitted to the analog receiving circuit 201 and the analog transmitting circuit 202, respectively. After the analog receiving circuit 201 and the analog transmitting circuit 202 receive the reset signal RS1 and the reset signal RS2, respectively, the analog receiving circuit 201 turns off the function of the second portion 201_2, and the analog transmitting circuit 202 turns off the function of the second portion 202_ 2.

Thereafter, the processing unit 242 controls the reference Voltage VDD1 to suspend the supply to the front-end chip 200, such as but not limited to controlling a Voltage Regulator (Voltage Regulator) on a Printed Circuit Board (PCB), controlling a power switch on the PCB, or controlling a power switch reference Voltage VDD1 (i.e., a core Voltage) inside the front-end chip 200, so that the digital control circuit 220, the second portion 201_2 of the analog receiving circuit 201, and the second portion 202_2 of the analog transmitting circuit 202 are turned off.

It should be appreciated that the reset 246 may generate the status signal SS to the level shifter 245 in response to the power state of the reference voltage VDD1 (i.e., the core voltage). In some embodiments, when the reference voltage VDD1 is not supplied to the digital control circuit 220, the reset 246 generates the status signal SS with the first value to the level shifter 245, and the level shifter 245 closes the second channel connected to the digital control circuit 220 according to the status signal SS with the first value, so that the level shifter 245 does not receive all information (including the UNLOCK signal UNLOCK). Thus, the operation information OD2 in the storage unit 244 remains unchanged, and the front-end chip 200 enters the sleep mode.

In the sleep mode, since the reference voltage VDD1 is suspended from being supplied to the front-end chip 200, the digital control circuit 220 is turned off, but the first portion 201_1 of the analog receiving circuit 201 operating at the reference voltage VDD2 can still receive the data signal S1 and the auxiliary signal AS1, and the first portion 202_1 of the analog transmitting circuit 202 operating at the reference voltage VDD2 can still receive the auxiliary signal AS 2. The signal detector 241 can detect any of the aforementioned signals. In addition, in some embodiments, the signal detector 241 may also receive the hot plug signal HS directly without passing through the analog transmitting circuit 202. In some embodiments, the aforementioned data signal S1, auxiliary signal AS1, auxiliary signal AS2 and hot plug signal HS are referred to AS wake-up conditions. Therefore, in the sleep mode, the signal detector 241 can generate the control signal CS to the processing unit 242 according to the wake-up condition (for example, when any one of the signal potentials changes) to execute the procedure leaving the sleep mode.

The front-end chip 200 of the present application may completely shut off the supply of the reference voltage VDD1 in the sleep mode to reduce the power consumption of the front-end chip 200 (e.g., to a power consumption level of microamperes (uA)), and maintain the ability to wake up the front-end chip 200 to return to the normal mode. The flow of the front-end chip 200 returning from the sleep mode to the normal mode is explained as follows.

When the front-end chip 200 wants to switch from the sleep mode to the normal mode, the processing unit 242 updates the sleep information SD1 stored in the storage unit 244 to the wake-up information SD2 in response to the control signal CS of the signal detector 241. According to the wake-up information SD2 in the storage unit 244, the processing unit 242 may control the reference voltage VDD1 (i.e., the core voltage) to resume supplying to the front-end chip 200 (e.g., control a voltage regulator on a printed circuit board, a power switch, or a power switch in the front-end chip). In response to the reference voltage VDD1 resuming power supply, the reset 246 generates the status signal SS having the second value to the level shifter 245, and the level shifter 245 releases the blocking state of the UNLOCK signal according to the status signal SS having the second value. Then, after the reference voltage VDD1 is restored, the digital control circuit 220 transmits the UNLOCK signal UNLOCK to the level shifter 245, and then the level shifter 245 transmits the UNLOCK signal UNLOCK to the storage unit 244. After the storage unit 244 receives the UNLOCK signal UNLOCK, the processing unit 242 determines that the storage unit 244 receives the UNLOCK signal UNLOCK, and then controls the level shifter 245, so that the level shifter 245 shifts the operation information OD2 stored in the storage unit 244 from the voltage domain of the reference voltage VDD2 to the voltage domain of the reference voltage VDD1, and outputs the operation information OD1 to the digital control circuit 220. The digital control circuit 220 returns to the operation state before entering the sleep mode according to the operation information OD1, thereby returning the front-end chip 200 to the normal mode. It should be noted that the digital control circuit 220 receives the operation information OD1 after receiving the reference voltage VDD1 (i.e., the core voltage) first and then recovers the operating power, so that there is no floating state (floating) in which the operation information OD1 is received first and power is not supplied.

When the sleep mode is switched to the normal mode, the processing unit 242 stops transmitting the reset signal RS1 and the reset signal RS2 after the reference voltage VDD1 is restored to the front-end chip 200, so that the analog receiving circuit 201 and the analog transmitting circuit 202 restore the functions of the second portion 201_2 and the second portion 202_ 2. The analog receiving circuit 201 and the analog transmitting circuit 202 are not in a floating state in which they are enabled first and are not powered because they are first supplied with the reference voltage VDD1 and then enabled (enabled).

The arrangement of the data transmission system 10 provided above is for exemplary purposes only. Various arrangements of the data transmission system 10 are within the contemplation and scope of the present application. For example, please refer to the data transmission system 30 and the data transmission system 40 of fig. 3 and fig. 4.

In some embodiments, such as the data transmission system 30 of fig. 3, the front-end chip 200 is disposed in the transmission device 100, coupled to the processor 105 of the transmission device 100, and controlled by the processor 105. Since the processor 105 can know whether the transmitting device 100 is to transmit the data signal S1 or the auxiliary signal AS1, the processor 105 can directly notify the front-end chip 200 of the operation status. When the transmitting device 100 does not need to transmit the data signal S1, the processor 105 may control the front-end chip 200 to enter the sleep mode. In the sleep mode, when the transmitting device 100 is ready to transmit the data signal S1, the processor 105 may control the front-end chip 200 to return to the normal mode, i.e., the front-end chip 200 does not need to detect the data signal S1 and the auxiliary device AS1 from the transmitting device 100.

In some embodiments, the front-end chip 200 is in the sleep mode when the receiving device 300 is not connected to the front-end chip 200 in the transmitting device 100. In this case, the front-end chip 200 determines whether the receiving device 300 is connected to it according to the hot plug signal HS. When the front-end chip 200 detects the hot plug signal HS, it indicates that the receiving device 300 is connected, so the front-end chip returns to the normal mode for transmitting the data signal S1.

In other embodiments, when the receiving device 300 is already connected to the front-end chip 200 in the transmitting device 100, but the receiving device 300 is turned off and cannot receive the data signal S2, the front-end chip 200 is in the sleep mode because the data signal S1 does not need to be converted to the data signal S2. In this case, the front-end chip 200 determines whether the receiving device 300 is ready to receive the data signal S2 according to the auxiliary signal AS 2. The auxiliary signal AS2 transmitted after the front-end chip 200 detects that the receiving device 300 is turned on indicates that the receiving device 300 can receive the data signal S2, thereby returning the front-end chip 200 to the normal mode. The processor 105 may proceed with the transmission of the data signal S1.

In some embodiments, such as the data transmission system 40 of fig. 4, the front-end chip 200 is disposed in the receiving device 300, coupled to the processor 305 of the receiving device 300, and controlled by the processor 305. Since the processor 305 can know whether the receiving device 300 is to transmit the auxiliary signal AS2, the processor 305 can directly inform the front-end chip 200 of the operation status. The front-end chip 200 may receive the hot plug signal HS from the receiving device 300, but only when the transmitting device 100 is connected, the hot plug signal HS needs to be transmitted to the transmitting device 100, and the auxiliary signal is a signal generated after the transmitting device 100 is connected. Therefore, the front-end chip 200 in the sleep mode only needs to detect the data signal S1 and the auxiliary signal AS1 from the transmitting device 100 to determine whether the front-end chip 200 returns to the normal mode.

The foregoing description has set forth briefly the features of certain embodiments of the application so that those skilled in the art to which the application pertains will be able to more fully understand the various forms of the disclosure of the application. Those skilled in the art who have the benefit of this disclosure will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art to which this application pertains will appreciate that such equivalent embodiments are still within the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Description of the reference numerals

10: data transmission system

30: data transmission system

40: data transmission system

100: transmission device

105: processor with a memory having a plurality of memory cells

300: receiving apparatus

305: processor with a memory having a plurality of memory cells

200: front-end chip

201: analog receiving circuit

202: analog transmission circuit

201_ 1: the first part

201_ 2: the second part

202_ 1: the first part

202_ 2: the second part

220: digital control circuit

221: processing unit

222: clock pulse source

223: signal conversion unit

224: auxiliary control unit

225: hot plug detector

240: switching circuit

241: signal detector

242: processing unit

243: clock pulse source

244: storage unit

245: electric potential converter

246: resetting device

CH1 a: channel

CH1 b: channel

CH2 a: channel

CH2 b: channel

CH3 a: channel

CH3 b: channel

S1: data signal

S2: data signal

AS 1: auxiliary signal

AS 2: auxiliary signal

HS: hot plug signal

RS 1: reset signal

RS 2: reset signal

CS: control signal

And SS: status signal

OD 1: operation information

OD 2: operation information

SD 1: dormancy information

SD 2: wake-up information

CLK 1: clock pulse signal

CLK 2: clock pulse signal

VDD 1: reference voltage

VDD 2: reference voltage

LOCK: locking signal

UNLOCK: unlock signal

Claims (10)

1. A chip for reducing power consumption of a data transmission system, comprising:

an analog receiving circuit operating at a first reference voltage and receiving a first data signal;

an analog transfer circuit operating at the first reference voltage;

a digital control circuit, operating at a second reference voltage and generating a second data signal to the analog transmission circuit according to the first data signal in a normal mode of the chip, wherein the digital control circuit comprises a first clock pulse source for providing a first clock pulse signal in the normal mode, wherein the digital control circuit operates according to the first clock pulse signal; and

a switching circuit, in the normal mode, the switching circuit operates at the first reference voltage, and the switching circuit is used for controlling the second reference voltage to suspend being supplied to the digital control circuit to enable the chip to enter a sleep mode of the chip, the switching circuit further controls the second reference voltage to be supplied to the digital control circuit according to the first data signal in the sleep mode to enable the chip to return to the normal mode, wherein the first reference voltage is higher than the second reference voltage.

2. The chip of claim 1, wherein the switching circuit comprises:

a signal detector for detecting the first data signal and generating a control signal when the chip is in the sleep mode;

the storage unit is used for storing the operation information of the digital control circuit;

a second clock source for providing a second clock signal, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal; and (c) and (d).

3. A processing unit, configured to control the second reference voltage to be supplied to the digital control circuit according to the second clock signal and the control signal when the chip is in the sleep mode to return the chip to the normal mode, and control the second reference voltage to stop being supplied to the digital control circuit according to the second clock signal and the operation information when the chip is in the normal mode to make the chip enter the sleep mode. The chip of claim 2, wherein the switching circuit further comprises:

a level shifter for converting the operation information of the digital control circuit from the second reference voltage to the first reference voltage and storing the operation information in the storage unit,

wherein, when the chip is in the sleep mode, the processing unit is further configured to control the level shifter according to the operation information, so that the level shifter keeps the operation information stored in the storage unit unchanged,

when the chip enters the normal mode from the sleep mode, the processing unit is further used for controlling the potential converter to convert the operation information from the first reference voltage to the second reference voltage for transmission to the digital control circuit; and

a reset, wherein when the second reference voltage changes from being supplied to the digital control circuit to being suspended from being supplied to the digital control circuit, the reset generates a status signal to the level shifter, the status signal having a first value, wherein the level shifter receives the status signal having the first value and transmits first information of the operation information stored in the storage unit to the processing unit, wherein the first information is used for the processing unit to control the level shifter to keep the operation information stored in the storage unit unchanged by the level shifter,

wherein the reset generates the status signal to the level shifter when the second reference voltage is changed from being temporarily supplied to the digital control circuit to being supplied to the digital control circuit, the status signal having a second value, wherein the level shifter receives the status signal having the second value and transmits second information of the operation information stored in the storage unit to the processing unit, wherein the second information is used for causing the processing unit to control the level shifter to stop the level shifter from keeping the operation information stored in the storage unit unchanged.

4. The chip of claim 2, wherein the analog receive circuit is further operative at the second reference voltage and configured to transmit the first data signal to the digital control circuit, and wherein the analog transmit circuit is further operative at the second reference voltage to receive the second data signal,

before the chip enters the sleep mode, the processing unit is further configured to generate a first reset signal to the analog receiving circuit and a second reset signal to the analog transmitting circuit, wherein the first reset signal is configured to enable the analog receiving circuit not to transmit the first data signal to the digital control circuit, and the second reset signal is configured to enable the analog transmitting circuit not to receive the second data signal from the digital control circuit.

5. The chip of claim 1, wherein the analog receiving circuit is further configured to receive an auxiliary signal, and the switching circuit is further configured to control the second reference voltage to be supplied to the digital control circuit to return the chip to the normal mode when the chip is in the sleep mode according to the auxiliary signal, wherein the auxiliary signal includes information of a kind of the first data signal, and a transmission speed of the auxiliary signal is less than a transmission speed of the first data signal.

6. A chip for reducing power consumption of a data transmission system, comprising:

a digital control circuit, which operates at a first reference voltage when the chip is in a normal mode, wherein the digital control circuit comprises a first clock pulse source for generating a first clock pulse signal, wherein the digital control circuit operates according to the first clock pulse signal; and

a switching circuit operating at a second reference voltage, wherein in the normal mode of the chip, the switching circuit is configured to control the first reference voltage to suspend being supplied to the digital control circuit to enable the chip to enter a sleep mode, and in the sleep mode of the chip, the switching circuit controls the first reference voltage to be supplied to the digital control circuit to enable the chip to return to the normal mode according to the hot plug signal,

wherein the second reference voltage is higher than the first reference voltage, and the hot plug signal is generated by connecting the chip to an electronic device.

7. The chip of claim 6, wherein the switching circuit comprises:

the signal detector is used for detecting the hot plug signal and generating a control signal when the chip is in the sleep mode;

the storage unit is used for storing the operation information of the digital control circuit;

a second clock source for providing a second clock signal; and

a processing unit for controlling the first reference voltage to be supplied to the digital control circuit according to the second clock signal and the control signal when the chip is in the sleep mode to return the chip to the normal mode, and controlling the first reference voltage to stop being supplied to the digital control circuit according to the second clock signal and the operation information when the chip is in the normal mode to make the chip enter the sleep mode,

wherein the frequency of the first clock pulse signal is higher than the frequency of the second clock pulse signal.

8. The chip of claim 7, wherein the switching circuit further comprises:

a level shifter for converting the operation information of the digital control circuit from the first reference voltage to the second reference voltage and storing the operation information in the storage unit,

wherein, when the chip is in the sleep mode, the processing unit is further configured to control the level shifter according to the operation information, so that the level shifter keeps the operation information stored in the storage unit unchanged,

when the chip enters the normal mode from the sleep mode, the processing unit is further used for controlling the potential converter to convert the operation information from the second reference voltage to the first reference voltage for transmission to the digital control circuit.

9. The chip of claim 8, wherein the switching circuit further comprises:

a reset, wherein when the first reference voltage changes from being supplied to the digital control circuit to being suspended from being supplied to the digital control circuit, the reset generates a status signal to the level shifter, the status signal having a first value, wherein the level shifter receives the status signal having the first value and transmits first information of the operation information stored in the storage unit to the processing unit, wherein the first information is used for the processing unit to control the level shifter to keep the operation information stored in the storage unit unchanged by the level shifter,

wherein the reset generates the status signal to the level shifter when the first reference voltage changes from being temporarily supplied to the digital control circuit to being supplied to the digital control circuit, the status signal having a second value, wherein the level shifter receives the status signal having the second value and transmits second information of the operation information stored in the storage unit to the processing unit, wherein the second information is used for causing the processing unit to control the level shifter to stop the level shifter from keeping the operation information stored in the storage unit unchanged.

10. The chip of claim 6, further comprising:

an analog transmission circuit operating at the second reference voltage for receiving a first auxiliary signal,

wherein, when the chip is in the sleep mode, the switching circuit is further configured to control the first reference voltage to be supplied to the digital control circuit according to the first auxiliary signal so as to return the chip to the normal mode; and

an analog receiving circuit, operating at the second reference voltage, for receiving a first data signal, wherein the analog receiving circuit further operates at the first reference voltage when the chip is in the normal mode, and transmits the first data signal to the digital control circuit, wherein the digital control circuit generates a second data signal to the analog transmitting circuit according to the first data signal,

wherein the analog transmitting circuit further operates at the first reference voltage when the chip is in the normal mode and transmits the first auxiliary signal to the digital control circuit, wherein the digital control circuit generates a second auxiliary signal to the analog receiving circuit according to the first auxiliary signal,

wherein a transmission speed of the first auxiliary signal is less than a transmission speed of the first data signal.

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