CN114330186A - Front-end chip of data transmission system - Google Patents

Abstract

The invention relates to a front-end chip of a data transmission system. The chip includes receiving, transmitting, controlling and switching circuits. The receiving circuit operates at the first voltage and is used for receiving the first data signal. The transmission circuit operates at the first voltage. In the normal mode of the chip, the control circuit operates at the second voltage and generates the second data signal to the transmission circuit according to the first data signal. The control circuit includes a clock pulse source for providing a clock pulse signal in a normal mode, wherein the control circuit operates according to the clock pulse signal. In the normal mode, the switching circuit operates at the first voltage and is used to control the second voltage to be suspended from being supplied to the control circuit so that the chip enters the sleep mode of the chip. The switching circuit also controls the second voltage to be supplied to the control circuit according to the first data signal in the sleep mode to return the chip to the normal mode. The first voltage is higher than the second voltage.

Description

Front-end chip for data transmission system

technical field

The present application relates to a chip, in particular to a chip that operates in a normal mode or a sleep mode according to a received signal.

Background technique

In the current technology, many input/output devices only use one transmission protocol for their transmission interface due to cost considerations, so additional front-end chips are generally used to convert the transmission protocol or expand the input/output ports according to the application of the system. quantity. However, the extensive application of front-end chips often leads to an increase in the overall power consumption of the system, which has become an urgent problem to be solved in the art.

SUMMARY OF THE INVENTION

The present application provides a chip for reducing the power consumption of a data transmission system, which includes an analog receiving circuit, an analog transmitting circuit, a digital control circuit and a switching circuit. The analog receiving circuit operates at the first reference voltage and is used for receiving the first data signal. The analog transmission circuit operates at the first reference voltage. In the normal mode of the chip, the digital control circuit operates at the second reference voltage and is used for generating the second data signal to the analog transmission circuit according to the first data signal. The digital control circuit includes a first clock pulse source. The first clock pulse source is used for providing the first clock pulse signal in the normal mode, wherein the digital control circuit operates according to the first clock pulse signal. In the normal mode of the chip, the switching circuit operates at the first reference voltage, and the switching circuit is used to control the second reference voltage to be suspended from being supplied to the digital control circuit so that the chip enters the sleep mode of the chip. The switching circuit also controls the second reference voltage to be supplied to the digital control circuit according to the first data signal in the sleep mode to return to the normal mode. The first reference voltage is higher than the second reference voltage.

The present application provides a chip for reducing power consumption of a data transmission system, which includes a digital control circuit and a switching circuit. In the normal mode of the chip, the digital control circuit operates at the first reference voltage. The digital control circuit includes a first clock pulse source. The first clock pulse source is used for generating the first clock pulse signal, wherein the digital control circuit is used for operating according to the first clock pulse signal. The switching circuit operates at the second reference voltage, wherein when the chip is in the normal mode, the switching circuit is used to control the first reference voltage to be suspended from being supplied to the digital control circuit so that the chip enters the sleep mode of the chip. And when the chip is in the sleep mode, the switching circuit controls the first reference voltage to be supplied to the digital control circuit according to the hot-plug signal to make the chip return to the normal mode. The second reference voltage is higher than the first reference voltage. The hot-plug signal is generated by connecting the chip to the electronic device.

The chip of the present application can reduce the overall power consumption of the chip in the sleep mode, and maintain the function of waking up the chip from the sleep mode to the normal mode.

Description of drawings

The various forms of the present application can be better understood upon reading the following description and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be exaggerated or reduced in size for clarity of description.

FIG. 1 is a schematic diagram of a data transmission system according to some embodiments.

FIG. 2 is a schematic diagram of a front-end chip used in a data transmission system according to some embodiments.

FIG. 3 is a schematic diagram of a data transmission system according to other embodiments.

FIG. 4 is a schematic diagram of a data transmission system according to other embodiments.

Detailed ways

Please refer to Figure 1. In the data transmission system 10 of the present application, the front-end chip 200 can switch between the normal mode and the sleep mode, and can switch to the sleep mode when the front-end chip 200 is idle to reduce power consumption. The details are described below.

The data transmission system 10 includes a transmission device 100 , a front-end chip 200 and a reception device 300 . The front-end chip 200 is coupled between the transmitting device 100 and the receiving device 300 . When the communication protocol used by the receiving device 300 is different from the communication protocol used by the transmitting device 100 , the front-end chip 200 converts the format of the signal so that the receiving device 300 can receive the signal from the transmitting device 100 .

In this embodiment, the front-end chip 200 and the transmitting device 100 and the receiving device 300 include interfaces for transmitting high-speed signals and low-speed signals. As shown in FIG. 1 , the high-speed signal includes a data signal S1 transmitted through the channel CH1a between the transmission device 100 and the front-end chip 200 , and a data signal S2 transmitted through the channel CH1b between the receiving device 300 and the front-end chip 200 . The low-speed signal includes the auxiliary signal AS1 transmitted through the channel CH2a between the transmission device 100 and the front-end chip 200 , and the auxiliary signal AS2 transmitted through the channel CH2b between the receiving device 300 and the front-end chip 200 . The low-speed signal also includes a hot-plug signal HS generated when the receiving device is connected to the chip 200 . The hot plug signal HS is transmitted through the channel CH3a and the channel CH3b.

For example, the transmitting device 100 is a personal computer using only the High Definition Multimedia Interface (HDMI) transmission protocol, and the receiving device 300 is a screen using only the DisplayPort (DP) transmission protocol. When the screen is connected to the front-end chip 200 , a hot-plug signal HS is generated and transmitted to the front-end chip 200 . Next, the front-end chip 200 transmits the hot-plug signal HS to the personal computer to notify that the screen has been connected. The personal computer then transmits the HDMI data signal S1 including the display content to the front-end chip 200, and the front-end chip 200 converts the HDMI signal S1 into the data signal S2 of the DP transmission protocol and transmits it to the screen, so that the screen can receive the data signal S2 and present the display content.

For another example, the auxiliary signals (eg, AS1, AS2) are used to communicate the transmission speed and other information of the high-speed signals (eg, S1, S2) under a specific communication protocol. Generally speaking, the devices (eg, 100, 300) cannot determine the transmission protocol through the channels of the auxiliary signals (ie, CH2a, CH2b). In some embodiments, the screen is connected to the computer through the front-end chip 200 and generates a hot-plug signal HS to the computer, the computer and the screen auxiliary signal adjust the high-speed signal (for example: determine the transmission speed or the number of transmission channels), and the computer sends the high-speed signal through the high-speed channel. signal (including display content) to the screen. In some embodiments, the auxiliary signal AS1 and the auxiliary signal AS2 are also referred to as sideband signals.

The front-end chip 200 includes an analog receiving circuit 201 , an analog transmitting circuit 202 , a digital control circuit 220 and a switching circuit 240 . The analog receiving circuit 201 is used for transmitting the data signal S1 and the auxiliary signal AS1, and the analog transmitting circuit 202 is used for transmitting the data signal S2 and the auxiliary signal AS2, wherein the analog receiving circuit 201 and the analog transmitting circuit 202 belong to the physical layer of the front-end chip 200. ). The digital control circuit 220 is coupled between the analog receiving circuit 201 and the analog transmitting circuit 202 for converting the data signal S1 into the data signal S2, and for converting the auxiliary signal AS1 into the auxiliary signal AS2 or converting the auxiliary signal AS2 into the auxiliary signal Signal AS1. The digital control circuit 220 is further used for directly receiving the hot plug signal HS. In other words, the hot-plug signal HS is not transmitted through the analog receiving circuit 201 and the analog transmitting circuit 202 .

The switching circuit 240 is coupled to control the analog receiving circuit 201 , the analog transmitting circuit 202 and the digital control circuit 220 to operate in a normal mode or a sleep mode. In the normal mode, the data signal S1 is continuously transmitted to the front-end chip 200, and the functions and power supply of the analog receiving circuit 201, the analog transmitting circuit 202 and the digital control circuit 220 are completely turned on to convert the data signal S1 and generate the data signal S2. When no signal is transmitted into the front-end chip 200 (ie, idle), the switching circuit 240 will control the analog receiving circuit 201, the analog transmitting circuit 202 and the digital control circuit 220 to enter the sleep mode, so that the power supply of the digital control circuit 220 is completely stopped. The switching circuit 240 determines whether to leave the sleep mode according to at least one of the data signal S1 , the auxiliary signal AS1 , the auxiliary signal AS2 and the hot-plug signal HS.

In the data transmission system 10, the front-end chip 200 operates under the reference voltage VDD1 and the reference voltage VDD2, wherein the reference voltage VDD1 (in some embodiments, the core voltage (Core Power), the voltage value may be about 1.0V or 1.1V) ) is lower than the reference voltage VDD2 (in some embodiments, the pad power, which may be about 3.3V). The digital control circuit 220 as a whole operates under the reference voltage VDD1, and the switching circuit 240 operates under the reference voltage VDD2. In other words, when the supply of the reference voltage VDD1 to the digital control circuit 220 is suspended, the digital control circuit 220 is completely turned off. The analog receiving circuit 201 includes a first part 201_1 and a second part 201_2; the analog transmitting circuit 202 includes a first part 202_1 and a second part 202_2. The first part 201_1 and the first part 202_1 operate at the reference voltage VDD2 (ie the pin voltage); the second part 201_2 and the second part 202_2 operate at the reference voltage VDD1 (ie the core voltage). The reference voltage VDD2 is used to provide power for the first part 201_1 to receive the data signal S1 and the auxiliary signal AS1 from the transmission device 100, and to enable the first part 202_1 to receive the auxiliary signal AS2 from the receiving device 300 or transmit the data signal S2 and the auxiliary signal AS2 to the receiving device. 300. The reference voltage VDD1 is used to provide power so that the second part 201_2 can transmit the data signal S1 and the auxiliary signal AS1 to the digital control circuit 220, or can receive the auxiliary signal AS1 from the digital control circuit 220; the reference voltage VDD1 is used to provide power to the second part 201_2 The section 202_2 may receive the data signal S2 and the auxiliary signal AS2 from the control circuit 220 , or transmit the auxiliary signal AS2 to the digital control circuit 220 . The switching circuit 240 is used to control whether the reference voltage VDD1 (ie, the core voltage) is supplied to the digital control circuit 220 for switching between the normal mode and the sleep mode. The details of its process are described below.

Please refer to Figure 2. The digital control circuit 220 in the front-end chip 200 includes a processing unit 221, a clock pulse source 222, a signal conversion unit 223, an auxiliary control unit 224 and a hot-plug detector 225, and the switching circuit 240 in the front-end chip 200 includes a signal detection unit A controller 241 , a processing unit 242 , a clock pulse source 243 , a storage unit 244 , a potential converter 245 and a reset device 246 .

In the normal mode, the clock pulse source 222 generates the clock pulse signal CLK1 and provides it to the processing unit 221 . The clock pulse signal CLK1 is a high-speed clock pulse signal, for example, a high-speed clock pulse signal with a frequency of the order of megahertz (MHz), but not limited thereto. The processing unit 221 controls the signal conversion unit 223 (not shown in the connection diagram) to convert the received data signal S1 into a data signal S2 according to the clock pulse signal CLK1, and controls the auxiliary control unit 224 (not shown in the connection diagram) to transmit Auxiliary signal AS1 and auxiliary signal AS2. The processing unit 221 also controls the hot-plug detector 225 to receive and transmit the hot-plug signal HS.

In the sleep mode, since the reference voltage VDD1 is suspended from being supplied to the digital control circuit 220 , the clock pulse source 222 stops generating the clock pulse signal CLK1 to stop the processing unit 221 from working. In some embodiments, the processing unit 221 and the clock pulse source 222 are the components that consume the most power in the front-end chip 200 . Therefore, when the digital control circuit 220 is completely turned off, the power consumption of the front-end chip 200 can be greatly reduced, eg, from a milliwatt (mW) level to a microwatt (μW) level.

In the switching circuit 240 , the processing unit 242 is coupled to the signal detector 241 , the clock pulse source 243 , the storage unit 244 and the potential converter 245 , and the potential converter 245 is further coupled to the reset device 246 . In the present application, the reference voltage VDD2 is continuously supplied to the front-end chip 200 in both the normal mode and the sleep mode, so the switching circuit 240 in the front-end chip 200 will not stop operating due to switching to the sleep mode.

The clock pulse source 243 generates the clock pulse signal CLK2 and provides it to the processing unit 242 . The clock pulse signal CLK2 is a low-speed clock pulse signal, for example, a low-speed clock pulse signal with a frequency of the order of kilohertz (KHz), but not limited thereto. In other words, the clock pulse signal CLK2 has a lower frequency than the clock pulse signal CLK1. In general, the higher the frequency of clock pulses required to generate more power. Therefore, the power consumption of the clock pulse source 243 is lower than the power consumption of the clock pulse source 222 .

In the normal mode, the processing unit 242 controls the level converter 245 according to the low-speed clock signal CLK2, so that the level converter 245 converts the operation information OD1 transmitted from the digital control circuit 220 from the voltage domain of the reference voltage VDD1 to the reference voltage The voltage domain of VDD2. The converted operation information OD2 is stored in the storage unit 244 . Because in the normal mode, the digital control circuit 220 continues to operate, the potential converter 245 continues to convert the operation information OD1 and update the operation information OD2 stored in the storage unit 244 . In some embodiments, the storage unit 244 may be implemented with a register latch module, but is not limited thereto.

When the front-end chip 200 is to switch from the normal mode to the sleep mode, the digital control circuit 220 notifies the processing unit 242 in the switching circuit 240 to switch the mode. More precisely, the digital control circuit 220 transmits the operation information OD1 with the sleep information SD1 to the potential converter 245, and the potential converter 245 converts the operation information OD1 into the operation information OD2 (the content is the same as that of the operation information OD1) After being stored in the storage unit 244 , the processing unit 242 can perform the operation of switching from the normal mode to the sleep mode according to the sleep information SD1 (included in the operation information OD2 ) in the storage unit 244 . In some embodiments, it may be implemented by transmitting the lock signal LOCK and the unlock signal UNLOCK.

In some embodiments, the digital control circuit 220 and the potential converter 245 are connected with at least two channels, the first channel is used to transmit information including the unlock signal UNLOCK, and the second channel is used to transmit the operation information OD1 except the unlock signal Other information other than UNLOCK, but not limited to this. After the processing unit 242 accesses the sleep information SD1 (through the storage unit 244 ), the processing unit 242 can transmit the lock signal LOCK to the level converter 245 , so that the level converter 245 closes the second channel, and the level converter 245 will no longer receive The information other than the unlocking signal UNLOCK causes other information in the operation information OD2 except the unlocking signal UNLOCK to be no longer updated. This action is to prevent the potential converter 245 from receiving an unknown signal from the block circuit corresponding to the reference voltage VDD1 after the reference voltage VDD1 is turned off.

Subsequently, the processing unit 242 generates the reset signal RS1 and the reset signal RS2 and transmits them to the analog receiving circuit 201 and the analog transmitting circuit 202 , respectively. After the analog receiving circuit 201 and the analog transmitting circuit 202 respectively receive the reset signal RS1 and the reset signal RS2, the analog receiving circuit 201 turns off the function of the second part 201_2, and the analog sending circuit 202 turns off the function of the second part 202_2.

Thereafter, the processing unit 242 controls the reference voltage VDD1 to be temporarily supplied to the front-end chip 200, such as but not limited to controlling a voltage regulator (Voltage Regulator) on a printed circuit board (PCB), controlling a power switch on the printed circuit board, Or the power switch reference voltage VDD1 (ie the core voltage) inside the front-end chip 200 turns off the digital control circuit 220 , the second part 201_2 of the analog receiving circuit 201 and the second part 202_2 of the analog transmitting circuit 202 .

It should be understood that the resetter 246 may generate the state signal SS to the potential converter 245 in response to the supply state of the reference voltage VDD1 (ie, the core voltage). In some embodiments, when the reference voltage VDD1 is not supplied to the digital control circuit 220, the resetter 246 generates the state signal SS with the first value to the level converter 245, and the level converter 245 depends on the state signal with the first value. SS turns off the second channel connected to the digital control circuit 220, so that the potentiometer 245 does not receive all information (also including the unlock signal UNLOCK). Therefore, the operation information OD2 in the storage unit 244 remains unchanged, and the front-end chip 200 enters the sleep mode.

In the sleep mode, because the reference voltage VDD1 is temporarily supplied to the front-end chip 200, the digital control circuit 220 is turned off, but the first part 201_1 of the analog receiving circuit 201 operating at the reference voltage VDD2 can still receive the data signal S1 and the auxiliary signal AS1, and operate The first part 202_1 of the analog transmission circuit 202 at the reference voltage VDD2 can still receive the auxiliary signal AS2. The signal detector 241 can detect any of the aforementioned signals. In addition, in some embodiments, the signal detector 241 can also directly receive the hot-plug signal HS without going through the analog transmission circuit 202 . In some embodiments, the aforementioned data signal S1 , auxiliary signal AS1 , auxiliary signal AS2 and hot-plug signal HS are referred to as wake-up conditions. Therefore, in the sleep mode, the signal detector 241 can generate the control signal CS to the processing unit 242 according to the wake-up condition (eg, when the level of any of the above-mentioned signals changes), so as to execute the procedure of leaving the sleep mode.

The front-end chip 200 of the present application can completely cut off the supply of the reference voltage VDD1 in the sleep mode to reduce the power consumption of the front-end chip 200 (for example, to a power consumption level of microamps (uA)), and maintain the front-end chip 200 can be woken up to The ability to return to normal mode. The flow of the front-end chip 200 returning from the sleep mode to the normal mode is described as follows.

When the front-end chip 200 wants to switch from the sleep mode to the normal mode, in response to the control signal CS of the signal detector 241 , the processing unit 242 updates the sleep information SD1 stored in the storage unit 244 to the wake-up information SD2 . According to the wake-up information SD2 in the storage unit 244, the processing unit 242 can control the reference voltage VDD1 (ie, the core voltage) to restore the supply to the front-end chip 200 (eg, control the voltage regulator on the printed circuit board, the power switch, or the power supply in the front-end chip). switch). In response to the power supply of the reference voltage VDD1 being restored, the resetter 246 generates the state signal SS with the second value to the level converter 245 , and the level converter 245 releases the blocking state of the unlock signal UNLOCK signal according to the state signal SS with the second value. Next, after the reference voltage VDD1 is powered back up, the digital control circuit 220 transmits the unlock signal UNLOCK to the level converter 245 , and then the level converter 245 transmits it to the storage unit 244 . After the storage unit 244 receives the unlock signal UNLOCK, the processing unit 242 determines that the storage unit 244 will control the potential converter 245 after receiving the unlock signal UNLOCK, so that the potential converter 245 converts the operation information OD2 stored in the storage unit 244 from the reference voltage VDD2. The voltage domain is converted to the voltage domain of the reference voltage VDD1 , and the operation information OD1 is output to the digital control circuit 220 . The digital control circuit 220 returns to the working state before entering the sleep mode according to the operation information OD1, so that the front-end chip 200 returns to the normal mode. It is worth mentioning that the digital control circuit 220 first obtains the supply of the reference voltage VDD1 (ie, the core voltage) and then restores the working power, and then receives the operation information OD1, so there is no floating state (floating state) in which the operation information OD1 is received first without power supply. ).

When switching from the sleep mode to the normal mode, after the reference voltage VDD1 is restored to the front-end chip 200, the processing unit 242 stops transmitting the reset signal RS1 and the reset signal RS2, so that the analog receiving circuit 201 and the analog transmitting circuit 202 resume the first The functions of the second part 201_2 and the second part 202_2. Since the analog receiving circuit 201 and the analog transmitting circuit 202 are firstly supplied with the reference voltage VDD1 and then enabled, there is no floating state in which they are enabled first and have no power supply.

The settings of the data transmission system 10 provided above are for example purposes only. Various different data transmission system 10 arrangements are within the contemplation and scope of this application. For example, please refer to the data transmission system 30 and the data transmission system 40 of FIG. 3 and FIG. 4 .

In some embodiments, such as the data transmission system 30 of FIG. 3 , the front end chip 200 is disposed in the transmission device 100 coupled to and controlled by the processor 105 of the transmission device 100 . Because the processor 105 can know whether the transmission device 100 wants to transmit the data signal S1 or the auxiliary signal AS1, the processor 105 can directly notify the front-end chip 200 of the operation status. When the transmission device 100 does not need to transmit the data signal S1, the processor 105 can control the front-end chip 200 to enter the sleep mode. In the sleep mode, when the transmission device 100 is ready to transmit the data signal S1, the processor 105 can control the front-end chip 200 to return to the normal mode, that is, the front-end chip 200 does not need to detect the data signal S1 from the transmission device 100 and the auxiliary device AS1 .

In some embodiments, the front-end chip 200 is in a sleep mode when the receiving device 300 is not yet connected to the front-end chip 200 in the transmitting device 100 . In this case, the front-end chip 200 determines whether the receiving device 300 is connected to it according to the hot-plug signal HS. When the front-end chip 200 detects the hot-plug signal HS, it means that the receiving device 300 is connected, so the front-end chip is returned to the normal mode to transmit the data signal S1.

In other embodiments, when the receiving device 300 has been connected to the front-end chip 200 in the transmitting device 100, but the receiving device 300 is turned off and cannot receive the data signal S2, the front-end chip 200 does not need to convert the data signal S1 to the data signal. S2 is in sleep mode. In this case, the front-end chip 200 determines whether the receiving device 300 is ready to receive the data signal S2 according to the auxiliary signal AS2. When the front-end chip 200 detects the auxiliary signal AS2 transmitted after the receiving device 300 is turned on, it means that the receiving device 300 can receive the data signal S2, so the front-end chip 200 returns to the normal mode. The processor 105 can then transmit the data signal S1.

In some embodiments, such as the data transmission system 40 of FIG. 4 , the front end chip 200 is disposed in the receiving device 300 coupled with the processor 305 of the receiving device 300 and is controlled by the processor 305 . Because the processor 305 can know whether the receiving device 300 wants to transmit the auxiliary signal AS2, the processor 305 can directly notify the front-end chip 200 of the operation status. The front-end chip 200 can receive the hot-plug signal HS from the receiving device 300 , but only when the transmission device 100 is connected, the hot-plug signal HS needs to be transmitted to the transmission device 100 , and the auxiliary signal is after the transmission device 100 is connected. signal generated. Therefore, the front-end chip 200 in the sleep mode only needs to detect the data signal S1 and the auxiliary signal AS1 from the transmission device 100 to determine whether the front-end chip 200 returns to the normal mode.

The foregoing description briefly sets forth features of certain embodiments of the application, so that those skilled in the art to which this application pertains can more fully understand the various forms of the application's content. Those skilled in the art to which this application belongs can understand that they can easily use the content of this application as a basis to design or change other processes and structures to achieve the same purpose and/or achieve the same purpose as the embodiment herein. Same advantages. Those with ordinary knowledge in the technical field to which this application belongs should understand that these equivalent embodiments still belong to the spirit and scope of the content of this application, and they can make various changes, substitutions and alterations without departing from the content of this application. spirit and scope.

Description of reference numerals

10: Data transmission system

30: Data Transmission System

40: Data Transmission System

100: Transmission device

105: Processor

300: Receiver

305: Processor

200: Front-end chip

201: Analog receiving circuit

202: Analog Transmission Circuit

201_1: Part 1

201_2: Part II

202_1: Part 1

202_2: Part II

220: Digital Control Circuits

221: Processing Unit

222: clock pulse source

223: Signal conversion unit

224: Auxiliary Control Unit

225: Hot Plug Detector

240: Switching Circuit

241: Signal Detector

242: Processing Unit

243: Clock pulse source

244: Storage Unit

245: Potential Converter

246: Resetter

CH1a: Channel

CH1b: Channel

CH2a: channel

CH2b: channel

CH3a: channel

CH3b: channel

S1: data signal

S2: data signal

AS1: Auxiliary signal

AS2: Auxiliary signal

HS: hot plug signal

RS1: reset signal

RS2: reset signal

CS: control signal

SS: Status signal

OD1: Operational Information

OD2: Operational Information

SD1: Sleep information

SD2: wakeup information

CLK1: clock pulse signal

CLK2: clock pulse signal

VDD1: reference voltage

VDD2: reference voltage

LOCK: lock signal

UNLOCK: Unlock signal

Claims (10)

1. A chip for reducing power consumption of a data transmission system, comprising:

an analog receiving circuit operating at a first reference voltage and receiving a first data signal;

an analog transfer circuit operating at the first reference voltage;

a digital control circuit, operating at a second reference voltage and generating a second data signal to the analog transmission circuit according to the first data signal in a normal mode of the chip, wherein the digital control circuit comprises a first clock pulse source for providing a first clock pulse signal in the normal mode, wherein the digital control circuit operates according to the first clock pulse signal; and

a switching circuit, in the normal mode, the switching circuit operates at the first reference voltage, and the switching circuit is used for controlling the second reference voltage to suspend being supplied to the digital control circuit to enable the chip to enter a sleep mode of the chip, the switching circuit further controls the second reference voltage to be supplied to the digital control circuit according to the first data signal in the sleep mode to enable the chip to return to the normal mode, wherein the first reference voltage is higher than the second reference voltage.

2. The chip of claim 1, wherein the switching circuit comprises:

a signal detector for detecting the first data signal and generating a control signal when the chip is in the sleep mode;

the storage unit is used for storing the operation information of the digital control circuit;

a second clock source for providing a second clock signal, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal; and (c) and (d).

3. A processing unit, configured to control the second reference voltage to be supplied to the digital control circuit according to the second clock signal and the control signal when the chip is in the sleep mode to return the chip to the normal mode, and control the second reference voltage to stop being supplied to the digital control circuit according to the second clock signal and the operation information when the chip is in the normal mode to make the chip enter the sleep mode. The chip of claim 2, wherein the switching circuit further comprises:

a level shifter for converting the operation information of the digital control circuit from the second reference voltage to the first reference voltage and storing the operation information in the storage unit,

wherein, when the chip is in the sleep mode, the processing unit is further configured to control the level shifter according to the operation information, so that the level shifter keeps the operation information stored in the storage unit unchanged,

when the chip enters the normal mode from the sleep mode, the processing unit is further used for controlling the potential converter to convert the operation information from the first reference voltage to the second reference voltage for transmission to the digital control circuit; and

a reset, wherein when the second reference voltage changes from being supplied to the digital control circuit to being suspended from being supplied to the digital control circuit, the reset generates a status signal to the level shifter, the status signal having a first value, wherein the level shifter receives the status signal having the first value and transmits first information of the operation information stored in the storage unit to the processing unit, wherein the first information is used for the processing unit to control the level shifter to keep the operation information stored in the storage unit unchanged by the level shifter,

wherein the reset generates the status signal to the level shifter when the second reference voltage is changed from being temporarily supplied to the digital control circuit to being supplied to the digital control circuit, the status signal having a second value, wherein the level shifter receives the status signal having the second value and transmits second information of the operation information stored in the storage unit to the processing unit, wherein the second information is used for causing the processing unit to control the level shifter to stop the level shifter from keeping the operation information stored in the storage unit unchanged.

4. The chip of claim 2, wherein the analog receive circuit is further operative at the second reference voltage and configured to transmit the first data signal to the digital control circuit, and wherein the analog transmit circuit is further operative at the second reference voltage to receive the second data signal,

before the chip enters the sleep mode, the processing unit is further configured to generate a first reset signal to the analog receiving circuit and a second reset signal to the analog transmitting circuit, wherein the first reset signal is configured to enable the analog receiving circuit not to transmit the first data signal to the digital control circuit, and the second reset signal is configured to enable the analog transmitting circuit not to receive the second data signal from the digital control circuit.

5. The chip of claim 1, wherein the analog receiving circuit is further configured to receive an auxiliary signal, and the switching circuit is further configured to control the second reference voltage to be supplied to the digital control circuit to return the chip to the normal mode when the chip is in the sleep mode according to the auxiliary signal, wherein the auxiliary signal includes information of a kind of the first data signal, and a transmission speed of the auxiliary signal is less than a transmission speed of the first data signal.

6. A chip for reducing power consumption of a data transmission system, comprising:

a digital control circuit, which operates at a first reference voltage when the chip is in a normal mode, wherein the digital control circuit comprises a first clock pulse source for generating a first clock pulse signal, wherein the digital control circuit operates according to the first clock pulse signal; and

a switching circuit operating at a second reference voltage, wherein in the normal mode of the chip, the switching circuit is configured to control the first reference voltage to suspend being supplied to the digital control circuit to enable the chip to enter a sleep mode, and in the sleep mode of the chip, the switching circuit controls the first reference voltage to be supplied to the digital control circuit to enable the chip to return to the normal mode according to the hot plug signal,

wherein the second reference voltage is higher than the first reference voltage, and the hot plug signal is generated by connecting the chip to an electronic device.

7. The chip of claim 6, wherein the switching circuit comprises:

the signal detector is used for detecting the hot plug signal and generating a control signal when the chip is in the sleep mode;

the storage unit is used for storing the operation information of the digital control circuit;

a second clock source for providing a second clock signal; and

a processing unit for controlling the first reference voltage to be supplied to the digital control circuit according to the second clock signal and the control signal when the chip is in the sleep mode to return the chip to the normal mode, and controlling the first reference voltage to stop being supplied to the digital control circuit according to the second clock signal and the operation information when the chip is in the normal mode to make the chip enter the sleep mode,

wherein the frequency of the first clock pulse signal is higher than the frequency of the second clock pulse signal.

8. The chip of claim 7, wherein the switching circuit further comprises:

a level shifter for converting the operation information of the digital control circuit from the first reference voltage to the second reference voltage and storing the operation information in the storage unit,

wherein, when the chip is in the sleep mode, the processing unit is further configured to control the level shifter according to the operation information, so that the level shifter keeps the operation information stored in the storage unit unchanged,

when the chip enters the normal mode from the sleep mode, the processing unit is further used for controlling the potential converter to convert the operation information from the second reference voltage to the first reference voltage for transmission to the digital control circuit.

9. The chip of claim 8, wherein the switching circuit further comprises:

a reset, wherein when the first reference voltage changes from being supplied to the digital control circuit to being suspended from being supplied to the digital control circuit, the reset generates a status signal to the level shifter, the status signal having a first value, wherein the level shifter receives the status signal having the first value and transmits first information of the operation information stored in the storage unit to the processing unit, wherein the first information is used for the processing unit to control the level shifter to keep the operation information stored in the storage unit unchanged by the level shifter,

wherein the reset generates the status signal to the level shifter when the first reference voltage changes from being temporarily supplied to the digital control circuit to being supplied to the digital control circuit, the status signal having a second value, wherein the level shifter receives the status signal having the second value and transmits second information of the operation information stored in the storage unit to the processing unit, wherein the second information is used for causing the processing unit to control the level shifter to stop the level shifter from keeping the operation information stored in the storage unit unchanged.

10. The chip of claim 6, further comprising:

an analog transmission circuit operating at the second reference voltage for receiving a first auxiliary signal,

wherein, when the chip is in the sleep mode, the switching circuit is further configured to control the first reference voltage to be supplied to the digital control circuit according to the first auxiliary signal so as to return the chip to the normal mode; and

an analog receiving circuit, operating at the second reference voltage, for receiving a first data signal, wherein the analog receiving circuit further operates at the first reference voltage when the chip is in the normal mode, and transmits the first data signal to the digital control circuit, wherein the digital control circuit generates a second data signal to the analog transmitting circuit according to the first data signal,

wherein the analog transmitting circuit further operates at the first reference voltage when the chip is in the normal mode and transmits the first auxiliary signal to the digital control circuit, wherein the digital control circuit generates a second auxiliary signal to the analog receiving circuit according to the first auxiliary signal,

wherein a transmission speed of the first auxiliary signal is less than a transmission speed of the first data signal.

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