CN114326338B

CN114326338B - Semiconductor structure and preparation method thereof

Info

Publication number: CN114326338B
Application number: CN202111661669.1A
Authority: CN
Inventors: 艾仙雄; 轩攀登; 方超; 魏禹农; 吁卫东; 袁元; 陈安
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-10-13
Anticipated expiration: 2041-12-31
Also published as: CN114326338A

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure provided by the present disclosure includes: a substrate; a plurality of storage stacked structures on the substrate, adjacent storage stacked structures being separated from each other by dicing streets; alignment marks in regions of the substrate exposed within the scribe lines for optical alignment; and a dummy auxiliary structure located on the substrate and in the scribe line including the alignment mark.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present application relates to the field of semiconductor design and fabrication, and more particularly, to semiconductor structures and methods of making the same.

Background

In recent years, semiconductor structures and their fabrication processes have been continuously developed. Among them, for example, three-dimensional memory devices are increasingly used in the market due to their high memory density and high memory capacity.

The fabrication process of the three-dimensional memory device is complicated, and it is necessary to go through several tens or more processes from the wafer to the final completion of the fabrication of a plurality of independent three-dimensional memory devices. The photolithography process is one of the most important process steps, and is mainly used for copying the pattern on the mask plate onto the silicon wafer so as to prepare for the next etching or ion implantation process. Generally, the photolithography process involves a series of processes such as cleaning and baking the surface of a silicon wafer, priming, spin coating a photoresist, soft baking, alignment exposure, post baking, development, hard baking, etching, and inspection. Photolithography is a joint between different processes, and it is often necessary to align optical alignment marks that are preformed on, for example, dicing streets (dicing lanes) of a wafer, in order to proceed to the next process. Therefore, the alignment accuracy of the photolithography process is critical, and the processing quality and the final performance of the three-dimensional memory are directly affected.

However, in the related manufacturing process, there are problems in that various factors affect the alignment accuracy of the photolithography process.

Disclosure of Invention

The present application provides a semiconductor structure and a method for fabricating the same that can at least partially solve the above-mentioned problems affecting the alignment accuracy of lithography existing in the related art.

An aspect of the present application provides a semiconductor structure comprising: a substrate; a plurality of storage stacked structures located on the substrate, adjacent storage stacked structures being separated from each other by dicing streets; an alignment mark located in an area of the substrate exposed within the scribe line for optical alignment; and a dummy auxiliary structure located on the substrate and located in the scribe line including the alignment mark.

In one embodiment according to the present application, the dummy auxiliary structure has a height equal to the height of the storage stack structure in a direction perpendicular to the substrate.

In one embodiment according to the present application, the dummy auxiliary structure is located between the alignment mark and the adjacent storage stack structure in a width direction of the dicing street including the alignment mark.

In one embodiment according to the present application, the dummy auxiliary structure and the adjacent storage stack structure are disposed parallel to each other along a length direction of the dicing streets including the alignment marks.

In one embodiment of the present application, the length of the dummy auxiliary structure is greater than the length of the alignment mark along the length direction of the scribe line including the alignment mark, and both ends of the dummy auxiliary structure protrude from both ends corresponding to the alignment mark, respectively.

In one embodiment according to the present application, there are a plurality of the dummy auxiliary structures in the scribe line including the alignment mark.

In one embodiment according to the present application, the plurality of dummy auxiliary structures are disposed at intervals from each other.

In one embodiment according to the present application, each of the dummy auxiliary structures has the same cross-sectional shape in any plane parallel to the substrate.

In one embodiment according to the present application, the cross-sectional shapes of the plurality of dummy auxiliary structures are identical to each other on the same plane parallel to the substrate.

In one embodiment according to the present application, the memory stack structure includes a plurality of sacrificial layers and interlayer insulating layers alternately stacked, and the dummy auxiliary structure has the same plurality of sacrificial layers and interlayer insulating layers alternately stacked as the memory stack structure.

In one embodiment according to the present application, the semiconductor structure further comprises: and the dielectric layer is positioned in the gap existing in the cutting channel and on the top surface of the semiconductor structure.

Another aspect of the present application provides a method of preparing a semiconductor structure, the method comprising: forming an alignment mark exposed on the surface of a substrate in the substrate, wherein the alignment mark is used for realizing optical alignment; forming a laminated structure on the substrate; and removing a portion of the stacked structure to form a scribe line extending through the stacked structure to the substrate, and retaining a portion of the stacked structure in the scribe line including the alignment mark to form a dummy auxiliary structure.

In one embodiment according to the present application, removing a portion of the stacked structure to form a scribe line extending through the stacked structure to the substrate, and forming a dummy auxiliary structure in the scribe line including the alignment mark includes: and forming a mask layer, etching the cutting channel region of the laminated structure through the mask layer, and reserving part of the laminated structure in the cutting channel region containing the alignment mark to form the dummy auxiliary shape structure.

In one embodiment according to the present application, the stacked structure includes sacrificial layers and interlayer insulating layers alternately stacked, and the dummy auxiliary structure has the same sacrificial layers and interlayer insulating layers alternately stacked as the stacked structure.

In one embodiment according to the present application, the dummy auxiliary structure has a height equal to the height of the stacked structure in a direction perpendicular to the substrate.

In one embodiment according to the present application, a portion of the stacked structure between the alignment mark and the adjacent stacked structure is left along a width direction of the dicing street including the alignment mark to form the dummy auxiliary structure.

In one embodiment according to the present application, the dummy auxiliary structure and the adjacent laminated structure are formed parallel to each other along a length direction of the dicing streets including the alignment marks.

In one embodiment according to the present application, a plurality of the dummy auxiliary structures are formed in the scribe line including the alignment mark.

In one embodiment according to the present application, the plurality of dummy auxiliary structures have a space therebetween.

In one embodiment according to the application, the method further comprises: and forming a dielectric layer which fills the gap in the cutting channel and covers the top surface of the semiconductor structure.

Drawings

Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments, which proceeds with reference to the accompanying drawings. Embodiments of the application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. Wherein:

FIG. 1 is a schematic block diagram of a related art photoresist layer over a scribe line region to create dishing;

FIG. 2 is a schematic top view of the scribe line and the structure adjacent thereto of FIG. 1;

FIG. 3 is a photograph of a prior art electron microscope scan of a photoresist layer over a scribe line region to create a dishing;

FIG. 4 is a waveform diagram of an alignment signal collected when an alignment mark is optically aligned in the related art;

fig. 5 is a schematic diagram of a semiconductor structure having a dummy assist structure in accordance with an exemplary embodiment of the application;

FIG. 6 is a cross-sectional view of FIG. 5 taken along line F-F;

fig. 7 is a schematic diagram of a semiconductor structure having a dummy assist structure in accordance with yet another exemplary embodiment of the application;

fig. 8 is a schematic diagram of a semiconductor structure having a dummy assist structure according to yet another exemplary embodiment of the present application;

FIG. 9 is a cross-sectional view of FIG. 8 along line G-G;

fig. 10 is a schematic diagram of a semiconductor structure having a dummy assist structure according to yet another exemplary embodiment of the present application;

fig. 11 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment of the present application;

fig. 12 is a schematic diagram of a semiconductor structure having a dummy assist structure in accordance with yet another exemplary embodiment of the application;

Fig. 13 is a schematic diagram of a related art semiconductor structure without a dummy auxiliary structure corresponding to the exemplary embodiment of fig. 12;

fig. 14 is an electron microscope scan picture of a semiconductor structure provided with a dummy assist structure such that a photoresist layer has a relatively flat upper surface according to still another exemplary embodiment of the present application; and

fig. 15 is an electron microscope scan image of a dishing generated by a photoresist layer on the surface of a semiconductor structure without a dummy auxiliary structure in the related art.

Detailed Description

The present application will be described in detail below with reference to the attached drawings, and the exemplary embodiments mentioned herein are only for explaining the present application, not for limiting the scope of the present application. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

In the drawings, the thickness, size, and shape of the components have been slightly adjusted for convenience of description. The figures are merely examples and are not drawn to scale. As used herein, the terms "about," "approximately," and similar terms are used to represent approximations, not to represent degrees, and are intended to illustrate inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art. It should be understood that in this specification, the expressions first, second, etc. are used merely to distinguish one feature from another feature and do not denote any limitation of features, and in particular do not denote any order of precedence.

It will be further understood that terms such as "comprises," "comprising," "includes," "including," "having," "includes," "including," and/or "containing" are open-ended, rather than closed-ended, terms that specify the presence of the stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features listed, it modifies the entire list of features rather than just modifying the individual elements in the list. Furthermore, when describing embodiments of the application, use of "may" means "one or more embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.

Furthermore, when the terms "connected," "overlying," and/or "formed over …" are used in this disclosure, it may be meant that the respective components are in direct or indirect contact, unless expressly defined otherwise or able to be deduced from the context.

Unless otherwise defined, all terms (including engineering and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application pertains. Furthermore, unless explicitly stated otherwise in the present disclosure, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic or sapphire wafer. The substrate may be a single layer or comprise multiple layers.

As used herein, the term "layer" refers to a portion of material having a thickness. The layer may be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness that is less than or greater than the thickness of the continuous structure.

As used herein, the term "three-dimensional memory" refers to a semiconductor device having a string of memory cell transistors oriented vertically on a laterally oriented substrate such that the string of memory cell transistors extends in a vertical or substantially vertical direction relative to the substrate. As used herein, the term "vertical" means perpendicular or substantially perpendicular to the lateral surface of the substrate.

Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

In addition, the embodiments of the present application and the features of the embodiments may be combined with each other without collision. Furthermore, unless explicitly defined or contradicted by context, the particular steps included in the methods described herein are not necessarily limited to the order described, but may be performed in any order or in parallel.

In connection with the foregoing description of the background art section, in the related art, as the number of layers of the stacked structure formed on the wafer increases, the difference in height between the main chip (main chip) area and the scribe line (scribe line) area is larger and larger, and the scribe line area has a certain width, so that the coating uniformity of the photoresist is poor, especially, a relatively serious dishing (PR dishing) is formed in the scribe line near the edge area of the adjacent storage stacked structure, which may seriously affect the alignment accuracy of the alignment mark in the scribe line in the subsequent alignment exposure process, thereby affecting the accuracy of the photolithography operation, and finally causing the abnormality of the device structure, and affecting the product yield.

FIG. 1 is a schematic structural view of a related art photoresist spin-coated photoresist pattern with a dicing street area to create dishing; FIG. 2 is a top view of FIG. 1; FIG. 3 is a photograph of a scanning electron microscope of a related art in which dishing is generated in a scribe line region after spin-coating a photoresist; fig. 4 is a graph of the intensity of an alignment signal obtained at different positions of an alignment mark when the alignment mark shown in fig. 3 (or fig. 1, 2) is optically aligned in a photolithography process.

Referring to fig. 1 and 2, the detecting stack structure 210' located in the scribe line 300 includes the same stack and has the same height as the storage stack structure 210 separated by the scribe line 300, and the scribe line 300 is located at a height position indicated by an arrow a in fig. 1, that is, a position where the top surface of the substrate 100 is located in fig. 1. From fig. 1, it can be seen that there is a height difference between the stack structure 210 'for detection and the scribe line 300, i.e., the height of the stack structure 210' (or the storage stack structure 210), so it can be understood that the greater the number of layers of the storage stack structure 210 in the semiconductor structure, the greater the height difference from the scribe line 300.

As can also be seen in fig. 1, a dielectric layer 500 is formed over scribe line 300, and a photoresist layer 600 is formed over dielectric layer 500. The dielectric layer 500 is deposited to fill the scribe line 300, and the dielectric layer 500 is also deposited in the non-scribe line region of the semiconductor structure (e.g., the top surface of the storage stack structure 210 or the inspection stack structure 210 '), and in the position adjacent to the scribe line in the inspection stack structure 210', the portion of the dielectric layer 500 formed on the top surface of the inspection stack structure 210' is higher than the portion filled in the scribe line 300 due to the difference in height therebetween, and the transition region of the dielectric layer 500 formed between the top surface of the inspection stack structure 210' and the top surface filled in the scribe line 300 forms a curved surface portion having a shape close to an arc, such as the region circled by the dotted line B in fig. 1, and the extension length of the transition curved surface portion from the side wall of the inspection stack structure 210' may be denoted as D2. It will be appreciated that the transition region of the dielectric layer 500 formed on the top surface of the storage stack 210 to the dielectric layer 500 formed in the scribe line 300 may also have a similar arcuate curved surface portion. On this basis, the photoresist layer 600 is coated, which further results in uneven and uniform coating of the photoresist layer 600, for example, a relatively larger area of curved transition region is generated in the portion of the photoresist layer 600 formed above the curved transition portion of the dielectric layer 500, which may be referred to as a dishing (PR dishing) of the photoresist layer, such as the portion circled by the dashed line box C in fig. 1, and the extension length of the transition curved portion from the sidewall of the stacked structure 210' for detection may be denoted as D3. In fig. 1, a distance between a side of the alignment mark 700 adjacent to the stacking structure 210 'for detection and a sidewall of the stacking structure 210' for detection may be denoted as D1, and as can be seen from fig. 1, a portion of the photoresist layer 600 where the transition curved surface portion (a portion corresponding to the distance D3) covers the alignment mark 700 may be denoted as D4 in the drawing. It can be seen that the transition surface portion of the photoresist layer 600 covers a large portion of the left side of the center O of the alignment mark 700, and the portion not covered by the transition surface portion of the photoresist layer 600 is separated from the center O of the alignment mark 700 by only the portion shown as D5 in the drawing.

Fig. 2 is a top view of fig. 1, and it should be noted that, since the photoresist layer 600 is located at the uppermost layer of the semiconductor structure, only the photoresist layer 600 located at the uppermost layer can be shown in fig. 2 according to the corresponding relationship of the views, so that the corresponding positional relationship between the structures of each portion can be more easily understood, and more details are schematically shown in fig. 2. Examples include: the position of the alignment mark 700 in the dicing street 300, the relative position of the alignment mark 700 and the stack structure 210' for detection located in the dicing street 300, the storage stack structure 210 separated by the dicing street 300 in the width direction of the dicing street 300, and the region 220 located between the storage stack structure 210 and the dicing street 300, also schematically show the dielectric layer 500 filled in the dicing street 300, the photoresist layer 600 covering the region 220, and the like. It is to be appreciated that the illustration in fig. 2 is merely exemplary, e.g., dielectric layer 500 may fill not only dicing streets 300, but also areas 220, and dielectric layer 500 may also overlie storage stack 210; for example, the photoresist layer 600 may cover not only the dielectric layer 500 formed in the region 220, but also the dielectric layer 500 filled in the scribe line 300, the dielectric layer 500 deposited on the top surface of the storage stack 210, and so on. In the exemplary semiconductor structure shown in fig. 2, the region 220 is included between the storage stack structure 210 and the scribe line 300, and the region 220 and the storage stack structure 210 are also part of a main chip (main chip) region, except that the region 220 does not have a stacked structure due to the design requirement of the semiconductor structure, i.e., the region 220 is similar to the scribe line 300 and is located on the top surface of the substrate 100. Thus, the storage stack 210 has the same height difference as the region 220 and the scribe line 300. It is understood that in other portions of the exemplary semiconductor structure or in other exemplary semiconductor structures, the two sides along the width of the scribe line do not necessarily have the regions 220 shown.

Referring to fig. 2, in conjunction with the foregoing description, it will be appreciated that, in the width direction of the scribe line 300, also due to the height difference between the storage stack 210 and the area 220 and the scribe line 300, the deposited dielectric layer 500 also creates a curved surface portion similar to the portion encircled by the dashed line box B in fig. 1 in the transition area from the top surface of the storage stack 210 to the area 220 and the scribe line 300. The portion of photoresist layer 600 formed over the curved transition region of dielectric layer 500 also creates a relatively larger area of photoresist layer curved transition region, i.e., a dishing (PR dishing) of the photoresist layer, similar to the portion encircled by dashed line box C in FIG. 1.

Referring to the electron microscope scan picture of fig. 3, in the picture, the extension length of the transition curved portion of the photoresist layer 600 shown may be denoted as D6, and the length of the region of the photoresist layer 600 where the transition curved portion (or the dished recess portion) covers the alignment mark 700 may be denoted as D7, and the size of D7 in fig. 3 is significantly greater than half the length of the alignment mark 700 along the extending direction of the dicing street.

Alignment marks 700 may be used for optical alignment in a lithographic process, and information collected and analyzed on alignment beams that reach the alignment marks and are reflected back may be used to effect alignment. It will be appreciated that the alignment beam must be deflected uncontrollably as it passes over the transition curved portion of the photoresist layer 600, i.e., the transition curved portion of the photoresist layer 600 will affect the optical path of the alignment beam and, of course, the optical path of the light returning after it reaches the alignment mark. Thus, the transitional curvature of the photoresist layer 600 may significantly affect the accuracy and integrity of the alignment signal when aligning the alignment mark 700, in other words, the alignment signal collected via the transitional curvature of the photoresist layer 600 may be incomplete, a portion of the signal may have been lost, and a portion of the signal collected may be biased and inaccurate. If the alignment signal is used as a basis for alignment operation, the alignment precision is obviously not ensured, and the precision of the subsequent semiconductor structure processing technology cannot be ensured, so that the production quality of the semiconductor structure is affected.

Referring to fig. 4, a waveform diagram representing the intensity of the collected optical alignment signal obtained when performing an optical alignment operation on an alignment mark 700 such as that shown in fig. 3 or 1 in the related art is shown. The abscissa in fig. 4 corresponds to a length value of the alignment mark 700 in the extending direction of the dicing street 300, for example, as shown in fig. 3 or fig. 1, wherein the position of the L0 point in the middle of the abscissa corresponds to the geometric center of the alignment mark 700 in the extending direction of the dicing street 300, for example, as shown in fig. 3 or fig. 1, that is, the position of the center line O in fig. 3 or fig. 1. The ordinate in fig. 4 represents the intensity information of the different optical alignment signals collected corresponding to the different positions of the alignment mark 700 in the abscissa. It should be noted that, the signal strength, integrity, and the like are mainly described and discussed herein with reference to the shape of the outer contour of the waveform diagram in fig. 4, and the local information such as different gray gradients in the waveform diagram is not a major consideration herein. As can be seen from fig. 4, on the left side centered on the L0 point shown in the abscissa, the collected optical alignment signal corresponding to the left half of the alignment mark 700 is significantly weaker and has a larger deviation, especially at the portion located at the left end far from the center L0 point, as indicated by the dashed box E in fig. 4. In contrast, on the right side centered on the L0 point shown in the abscissa, the collected optical alignment signal corresponding to the right half of the alignment mark 700 is clearer and more symmetrical, for example, the waveform outline of the right half is approximately symmetrical up and down with respect to the Sg0 line shown in the ordinate of fig. 4. As can be appreciated in connection with, for example, the distribution of photoresist layer 600 in fig. 1, above the centrally located left half of the corresponding alignment mark 700, is the dished portion of photoresist layer 600 described above, and is the portion of the dished recess where the curved waveform is greatly varying, it can be seen that dishing generated by photoresist layer 600 has a severe impact on the optical alignment operation of the photolithographic mark.

Similarly, in the width direction of scribe line 300, photoresist layer 600 also has dishing in the transition from the top surface of storage stack 210 to region 220 and scribe line 300, which can also create problems during optical alignment of lithographic alignment mark 700 that affect alignment signal integrity and accuracy as described above.

Also, it is understood that as the number of stacked layers included in the storage stack structure 210 increases, the difference in height between the storage stack structure 210 and, for example, the region 220 or the dicing street 300 increases further, the degree to which the photoresist layer 600 forms the above-described dishing is more serious, resulting in a larger region of the dicing street where the alignment mark 700 disposed on the substrate is covered by the overlying dishing, and the effect on the optical alignment operation of the alignment mark 700 is more severe.

In view of the foregoing problems in the related art, the present application provides a semiconductor structure that can reduce dishing to at least some extent and improve alignment accuracy with respect to alignment marks in a photolithography process to at least some extent.

The application will be described in detail below with reference to the drawings in connection with specific embodiments.

Fig. 5 illustrates a top view of a semiconductor structure according to an exemplary embodiment of the present application, and fig. 6 is a cross-sectional view of fig. 1 taken along line F-F. As shown in fig. 5 and 6, a semiconductor structure provided according to this exemplary embodiment of the present application may include: the substrate 100 and the plurality of storage stacks 210 on the substrate 100 are separated from each other by dicing lanes 300, and the dicing lanes 300 may include, for example, a transverse dicing lane 300-1 and a longitudinal dicing lane 300-2; alignment marks 700 located in regions of substrate 100 exposed within scribe line 300, alignment marks 700 may be used to achieve optical alignment in a photolithographic process; and a dummy assist feature 400 located on the substrate 100 and in the scribe line 300 including the alignment mark 700. In one embodiment, the semiconductor structure may further include a dielectric layer (not shown in fig. 5 and 6) that may fill the voids present within dicing streets 300 and may also overlie, for example, the top surface of storage stack structure 210.

In one embodiment, the dummy assist structure 400 may have an equal height to the storage stack structure 210 in a direction perpendicular to the substrate 100. In one embodiment, the memory stack structure 210 may include, for example, a plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked, and the dummy auxiliary structure 400 may have the same plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked as the memory stack structure 210.

In one embodiment, the scribe line 300-2 includes an alignment mark 700, and dummy auxiliary structures 400-1 and 400-2 are disposed between the alignment mark 700 and the two adjacent storage stacks 210-1 and 210-2, respectively, along the width direction of the scribe line 300-2. In the semiconductor structure shown in fig. 5, the alignment mark 700 is located approximately in the middle of the width direction of the scribe line 300-2, and the two dummy auxiliary structures 400-1 and 400-2 are arranged approximately symmetrically with respect to the center of the width direction of the scribe line 300-2. The provision of dummy assist features 400-1 and 400-2 may be advantageous in supporting a subsequent photoresist layer formed over scribe line 300-2, in reducing the formation of dishing to some extent as described above, and in improving the alignment accuracy of alignment mark 700 in a subsequent photolithography process. In other embodiments, the dummy auxiliary structure 400 may be disposed only between the alignment mark 700 and the storage stack structure 210 on the adjacent side. In other embodiments, the dummy auxiliary structures 400-1 and 400-2 disposed between the alignment mark 700 and the storage stack structures 210-1 and 210-2 adjacent to both sides, respectively, may also be asymmetric with respect to the center of the dicing lane 300-2 in the width direction. In other embodiments, the alignment mark 700 may be disposed offset from the center of the dicing street 300-2 in the width direction. The arrangement in fig. 5 and 6 is exemplary only and not limiting.

Further, the dummy auxiliary structure 400 may have the same cross section in any different plane parallel to the plane in which the substrate 100 is located, in other words, the dummy auxiliary structure 400 may be one uniform cross section body. The cross section of the dummy auxiliary structure 400 may be rectangular as shown in fig. 5, or may be designed into other shapes as needed, which is not particularly limited in the present application. In another embodiment, the dummy auxiliary structure 400 may be a non-uniform cross-section structure in a vertical direction, for example, perpendicular to the substrate 100, for example, the dummy auxiliary structure 400 may have a cross-section gradually shrinking or gradually enlarging from bottom to top in a vertical direction perpendicular to the substrate 100.

Different dummy sub-structures 400 disposed in the semiconductor structure may have the same cross section as each other in any one plane parallel to the plane in which the substrate 100 is disposed, for example, the dummy sub-structures 400-1 and 400-2 shown in fig. 5 may have the same rectangular cross section. In other embodiments, different dummy auxiliary structures may also have cross sections of the same other shape, such as trapezoidal cross sections, etc. In other embodiments, different dummy assist features are in the same plane parallel to the substrate 100, and may have cross sections of different shapes or sizes as desired.

In one embodiment, the dummy auxiliary structure 400 and the adjacent storage stack structure 210 are disposed parallel to each other along the length direction of the scribe line 300 including the alignment mark 700. For example, in FIG. 5 along the length of the longitudinal scribe line 300-2, the dummy auxiliary structure 400-1 is disposed parallel to the storage stack structure 210-1, and the dummy auxiliary structure 400-2 is disposed parallel to the storage stack structure 210-2. In other embodiments, the dummy auxiliary structure 400 and the adjacent storage stack structure 210 may be disposed in non-parallel, for example, they may have a certain angle according to the design requirement, and the present application is not limited thereto.

In one embodiment, scribe line 300-2 extends longitudinally and scribe line 300-2 includes alignment marks 700. In the longitudinal extension direction along the scribe line 300-2, the lengths of the dummy auxiliary structures 400-1 and 400-2 are both greater than the length of the alignment mark 700, and both ends of the dummy auxiliary structures 400-1 and 400-2 in the length direction protrude from both ends corresponding to the alignment mark 700, respectively. The length of the dummy auxiliary structure 400 is greater than that of the alignment mark 700, and both ends of the dummy auxiliary structure 400 along the length direction are longer than the corresponding ends of the alignment mark 700, which can be beneficial to better supporting, for example, the dielectric layer 500 and/or the photoresist layer 600 formed above the alignment mark 700 in the subsequent process, and is beneficial to reducing the generation of the dishing of the photoresist layer above the alignment mark 700 to at least a certain extent, thereby being beneficial to reducing the adverse effect of the dishing of the photoresist layer on the optical path of the alignment beam when the optical alignment is performed on the alignment mark 700, and being beneficial to ensuring the alignment precision of the alignment mark in the photolithography process. In another embodiment, the dummy auxiliary structure 400 may further be formed of several segments, the total length of the integrated structure formed by combining the segments may be greater than the length of the alignment mark 700, and both ends of the integrated structure formed by combining the segments in the length direction are longer than both ends of the alignment mark 700, as shown in fig. 7. It will be appreciated that the form and size of the graphic elements in the dummy auxiliary structure 400 may be set in compliance with industry design rules (design rules), for example, in one particular process operation of one embodiment, the form and size of the dummy auxiliary structure 400 may be set in compliance with the form and size of other graphics (patterns) on the process operation, for example, a reticle, as the application is not particularly limited in this regard.

Fig. 8 illustrates a top view of a semiconductor structure according to another exemplary embodiment of the present application, and fig. 9 is a cross-sectional view of fig. 8 taken along line G-G. As shown in fig. 8 and 9, according to the semiconductor structure of this exemplary embodiment, the vertical scribe line 300-2 includes the alignment mark 700, and a plurality of dummy auxiliary structures 400 are respectively disposed between the alignment mark 700 and the two adjacent storage stack structures 210-1 and 210-2.

In one embodiment, a plurality of dummy auxiliary structures 400 between the alignment mark 700 and an adjacent storage stack structure 210-1 or 210-2 are each disposed at a distance from each other, as shown in fig. 8. In other embodiments, the alignment marks 700 may not have a pitch with some or all of the plurality of dummy auxiliary structures 400 between adjacent storage stack structures 210. In other embodiments, the plurality of dummy auxiliary structures 400 between the alignment marks 700 and the adjacent storage stack structures 210 may have equal or unequal spacing from each other.

Similar to the previous description, each of the plurality of dummy auxiliary structures 400 located between the alignment mark 700 and the adjacent storage stack structure 210 may be a uniform cross-section body. And the respective dummy auxiliary structures may have the same cross section as each other, for example, a rectangular cross section. In other embodiments, each of the plurality of dummy auxiliary structures 400 between the alignment mark 700 and the adjacent storage stack structure 210 may also be a non-uniform cross-section, for example, may have a cross-section gradually shrinking or gradually enlarging from bottom to top in a vertical direction perpendicular to the substrate 100. And the respective dummy auxiliary structures may have cross sections different from each other as needed.

In one embodiment, the plurality of dummy auxiliary structures 400 located between the alignment mark 700 and the adjacent storage stack structure 210 may have the same height as the storage stack structure 210 in a direction perpendicular to the substrate 100. In one embodiment, the memory stack structure 210 may include, for example, a plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked, and the plurality of dummy auxiliary structures 400 may each have the same plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked as the memory stack structure 210.

In summary, in the dicing street 300 including the alignment marks 700, the dummy auxiliary structure 400 may be disposed between the alignment marks 700 and the storage stack structures 210 adjacent to both sides. Depending on the distance between the alignment mark 700 and the adjacent storage stack structures 210 on both sides, one or more dummy auxiliary structures 400 may be selectively disposed, and the dummy auxiliary structures 400 may have the same height as the adjacent storage stack structures 210 and may be disposed in parallel with the adjacent storage stack structures 210, and the dummy auxiliary structures 400 may have a length greater than that of the alignment mark 700 and both ends longer than the alignment mark 700. By providing one or more dummy assist features 400 including, but not limited to, the problem of affecting the optical alignment accuracy of the alignment mark 700 in the lithographic process due to the formation of a more severe dishing of the subsequent photoresist layer due to the large height difference between the storage stack 210 and the scribe line 300 can be alleviated (see the detailed description section above). In particular, the provision of one or more dummy assist structures 400 may provide more efficient and uniform support for a photoresist layer subsequently formed over the entire semiconductor structure, may at least somewhat mitigate the occurrence of dishing of the photoresist layer, may mitigate adverse effects of dishing on the alignment beam path when the alignment mark 700 is optically aligned with a substrate surface in a scribe line during a lithographic process using a beam, may facilitate ensuring accuracy of optical alignment of the alignment mark 700, and may thereby facilitate operation accuracy of subsequent processes such as etching to be performed after alignment, and may facilitate improving production quality of the semiconductor structure.

Referring again to fig. 2, for the case shown in fig. 2, the dicing street 300 includes the alignment mark 700, and there is also a 220 region between the dicing street 300 and the storage stack 210 adjacent to both sides in the width direction of the dicing street 300, the 220 region being located at the same height as the dicing street, and there is also a height difference between the storage stack 210. In order to improve alignment accuracy with respect to the alignment mark 700, for example, a plurality of dummy auxiliary structures 400-3 may be respectively disposed between the alignment mark and the storage stack structures 210 on both sides, as shown in fig. 10.

In addition, in the scribe line 300 shown in fig. 2, there is a detection stack structure 210 'spaced apart from the alignment mark 700 by D1 along the length direction in which the scribe line 300 extends, and as described above, the same height difference between the detection stack structure 210' and the scribe line may also have a serious influence on the alignment accuracy of the alignment mark 700 as described above. For this case, for example, one dummy auxiliary structure 400-4 may be provided between the detection stack structure 210' and the alignment mark 700, as shown in fig. 10. Similar to the technical effects of providing the dummy auxiliary structure 400 described above, in this embodiment, the provision of the dummy auxiliary structures 400-3 and 400-4 also serves to improve the alignment accuracy of the alignment mark 700, and the principle thereof will be known in conjunction with the description thereof, and will not be repeated herein.

Another aspect of the application also provides a method of fabricating a semiconductor structure as described above, and fig. 11 is a flow chart of the method 1000. Referring to fig. 11 and other related structural drawings, a method 1000 of fabricating a semiconductor structure may include the steps of:

s1: forming an alignment mark 700 in the substrate 100 exposed to a surface of the substrate 100, the alignment mark 700 being operable to achieve optical alignment;

s2: forming a stacked structure 200 on a substrate 100; and

s3: a portion of the stacked structure 200 is removed to form a scribe line 300 extending through the stacked structure 200 to the substrate 100, and a portion of the stacked structure 200 is left in the scribe line 300 including the alignment mark 700 to form a dummy auxiliary structure 400.

The specific process of each step in the preparation method 1000 described above will be described in further detail with reference to the accompanying drawings.

According to step S1 of the method 1000, the substrate 100 is first provided, and the alignment mark 700 exposed to the surface of the substrate 100 is formed in a specific area (e.g., a partial area where a scribe line is to be formed later) of the substrate 100, and the alignment mark 700 can be used to achieve optical alignment in a subsequent photolithography process, see fig. 5 and 6.

In various embodiments of the present application, the provided substrate 100 may include, for example, at least one of single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor material, II-VI compound semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate 100 is, for example, a doped monocrystalline silicon substrate. The substrate 100 may be a P-type substrate or an N-type substrate, and the substrate 100 may further include an N-well and/or a P-well. In other embodiments, the substrate 100 may also be a composite substrate. It is to be understood that the present application is not limited thereto and that the substrate 100 may be arranged and selected according to actual needs. In addition, the pattern and the disposing process of the alignment mark 700 may be selected according to the needs in the embodiment, and the present application is not limited thereto.

The stacked structure 200 is formed on the substrate 100 according to step S2 in the method 1000, which may be accomplished by one or more deposition processes. Wherein the deposition process includes, but is not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or any combination thereof. It should be understood that in particular embodiments, the number and thickness of the sacrificial layers and the interlayer insulating layers may be specifically set as desired. In addition, materials of the sacrificial layer and the interlayer insulating layer may be selected from suitable materials known in the art. For example, the interlayer insulating layer may be an oxide layer (such as silicon oxide), and the sacrificial layer may be a nitride layer (such as silicon nitride). Further, it should be understood by those skilled in the art that the stacked structure 200 may include one or more stacks, i.e., the stacked structure 200 may be formed of a single stacked stack or may be formed of a plurality of stacked stacks sequentially, wherein the stack includes a plurality of sacrificial layers and interlayer insulating layers alternately stacked in a direction perpendicular to the substrate.

According to step S3 in the method 1000, a portion of the stacked structure 200 is removed to form a scribe line 300 extending through the stacked structure 200 to the substrate 100, and a portion of the stacked structure 200 is left in the scribe line 300 including the alignment mark 700 to form a dummy auxiliary structure 400. At least one dicing street 300 is formed in the stacked structure 200 to divide the stacked structure 200 into a plurality of storage stacks 210 (see fig. 12). The method of forming the scribe line 300 may be a dry etching process such as deep ion reaction etching (edge) or a wet etching process using phosphoric acid or the like as an etchant, and in practical applications, the method of forming the scribe line 300 includes, but is not limited to, the above-described dry etching process and wet etching process.

Taking the dry etching process to form the scribe line 300 as an example, specifically, a mask layer is formed on the side of the stacked structure 200 away from the substrate 100; the mask layer is patterned to form a pattern of streets therein, and the stacked structure 200 is etched with an etchant through the pattern on the mask layer to form at least one street 300.

In the embodiment of the present application, a dummy auxiliary structure 400 may be formed in the scribe line 300 including the alignment mark 700, specifically, as described above, a mask layer is formed on the side of the stacked structure 200 away from the substrate 100; the mask layer is patterned to form therein a pattern of scribe lines and a structural pattern in the scribe lines except for the dummy auxiliary structure set in advance, the stacked structure 200 is etched by using an etchant through the above-described scribe line pattern, a portion of the stacked structure 200 is removed in the scribe line region to form the scribe line 300, and the unremoved portion of the stacked structure 200 remaining in the scribe line region forms the dummy auxiliary structure 400. The dummy auxiliary structure 400 and the stacked structure 200 may have the same alternating stacked structure and have the same height. In one embodiment, the dummy auxiliary structure 400 formed along the length direction of the scribe line 300 including the alignment mark 700 may be parallel to each other with the adjacent storage stack structure 210. In one embodiment, the length of the formed dummy auxiliary structure 400 may be greater than the length of the alignment mark adjacent thereto, and both ends of the dummy auxiliary structure 400 may be longer than both ends corresponding to the alignment mark. In different embodiments, the shape, number and arrangement of the dummy auxiliary structure 400 may be set according to specific needs, and patterning of the mask layer may be performed according to the setting, so as to finally form the dummy auxiliary structure 400 with corresponding shape, number and arrangement. For example, a dummy assist structure as shown in fig. 5, 8, or 10 may be formed in the semiconductor structure.

Still further, in one embodiment, a mask layer is formed on a side of the stacked structure 200 remote from the substrate 100; the mask layer is patterned, for example, a pattern may be set to a pattern of removing the remaining structures other than the predetermined plurality of dummy auxiliary structures 400 arranged at equal intervals from each other on the scribe line 300, the stacked structure 200 is etched by using an etchant through the pattern, a portion of the stacked structure 200 is removed in the scribe line region to form the scribe line 300, and the non-removed portion of the stacked structure 200 remaining in the scribe line region forms the plurality of dummy auxiliary structures 400 arranged at equal intervals from each other, as shown in fig. 8, 10 or 12.

In one embodiment, a mask layer is formed on a side of the stacked structure 200 remote from the substrate 100; the mask layer is patterned, for example, a pattern may be set to remove a pattern of a remaining structure other than a predetermined plurality of dummy auxiliary structures 400 having the same cross section as each other in a direction perpendicular to the substrate 100 on the scribe line 300, the stacked structure 200 is etched by using an etchant through the pattern, a portion of the stacked structure 200 is removed in a scribe line region to form the scribe line 300, and an unremoved portion of the stacked structure 200 remaining in the scribe line region forms a plurality of dummy auxiliary structures 400 having the same cross section as each other in a direction perpendicular to the substrate 100, as shown in fig. 8, 10 or 12.

In one embodiment, a mask layer is formed on a side of the stacked structure 200 remote from the substrate 100; patterning the mask layer, for example, a pattern may be set to remove a pattern of a remaining structure other than a predetermined regularly arranged plurality of dummy auxiliary structures 400 having a rectangular cross section on the scribe line 300, etching the stacked structure 200 with an etchant via the pattern, removing a portion of the stacked structure 200 in a scribe line region to form the scribe line 300, and the non-removed portion of the stacked structure 200 remaining in the scribe line region forms a plurality of regularly arranged dummy auxiliary structures 400, each dummy auxiliary structure 400 having a rectangular cross section in a direction perpendicular to the substrate 100 in a longitudinal extension direction perpendicular to the scribe line 300, as shown in fig. 8, 10, or 12.

It should be noted that the forming manner of the dummy auxiliary structure is merely exemplary, and in other embodiments, the dummy auxiliary structure may be formed by other methods or means, and the material of the dummy auxiliary structure may also include other materials, instead of a stacked structure that is completely the same as the storage stacked structure. The present application is not limited thereto.

In an embodiment, the arrangement of the dummy auxiliary structure 400 in the scribe line 300 may be specifically designed according to necessity, and in one example, referring to fig. 5, the scribe line 300 may have a width of, for example, 80 μm, the scribe line 300 may be provided with the alignment mark 700 near the center, the alignment mark 700 may have a width of, for example, 30 μm, and the space between the alignment mark 700 and the storage stack structure 210 on one side may be about 25 μm, one dummy auxiliary structure 400 may be provided on each side of the alignment mark 700 in the scribe line 300, the dummy auxiliary structure 400 may have a width of, for example, 15 μm, and the space between the dummy auxiliary structure 400 and the alignment mark may be set to, for example, 5 μm, so that the dummy auxiliary structures 400 located on both sides of the alignment mark 700 may be arranged nearly symmetrically. Of course, it will be understood by those skilled in the art that, in order to improve the uniformity and consistency of photoresist coating and reduce dishing, more or fewer dummy auxiliary structures 400 may be disposed and arranged regularly, but the application is not limited thereto, and the number and arrangement pitch and arrangement of the dummy auxiliary structures 400 may take many different designs.

Fig. 12 illustrates another embodiment of the present application in which eight dummy sub-structures 400 are illustratively formed in the region of the scribe line 300 at equal intervals, and a photoresist layer 600 may be formed thereon to have a nearly horizontal upper surface. In contrast, in the semiconductor structure shown in fig. 13, the dummy auxiliary structure 400 is not provided in the region of the scribe line 300, and in this case, the photoresist layer 600 formed thereon generates a more serious dishing, as the portion encircled by the dashed line box H in the figure.

Fig. 12 and 13 are partial views of schematic semiconductor structures, and fig. 14 and 15 show electron microscope scan pictures of example dailies actually produced. A dummy auxiliary structure 400 is provided in the scribe line 300 of the semiconductor structure shown in fig. 14. The dummy sub-feature 400 is not disposed in the scribe line 300 of the semiconductor structure shown in fig. 15, and fig. 15 may be understood as a partial view of the J region circled by the dashed frame in fig. 14. As is apparent from comparing fig. 14 and 15, the photoresist layer 600 formed over the scribe line 300 provided with the dummy auxiliary structure 400 has a relatively flatter top surface, without generating a serious dishing, while the photoresist layer 600 formed over the scribe line 300 without the dummy auxiliary structure 400 generates a relatively serious dishing. As can be seen from the foregoing description, for dicing streets containing alignment marks in a substrate, the photoresist layer formed over the dicing streets can affect the alignment accuracy of the alignment marks in the photolithography process if a more severe dishing is created. However, according to the method provided by the application, by arranging the proper dummy auxiliary structure in the dicing street, the dishing degree of the photoresist layer 600 formed above the dicing street can be reduced, the relatively flat upper surface can be ensured, the alignment precision of the alignment mark in the photolithography process can be improved, and the production quality of the semiconductor structure can be ensured.

It should be noted that, the effect of the present application for improving the alignment accuracy of the alignment mark in the scribe line is not limited to the alignment process in a specific preparation step, and it is understood that any lithography process requiring alignment of the alignment mark in the scribe line in the semiconductor structure preparation process may improve the alignment accuracy due to the effect of the process implemented by the present application. Furthermore, the lithographic alignment marks are not limited to the structures described above or shown in the drawings herein nor to the locations of the substrate in the streets as described above, but in some embodiments may also be present in other structures or disposed in any other structure above the substrate that may be used for alignment by a subsequent lithographic process, such as a layer structure. For these cases, the concept provided by the application can be adopted to perform the arrangement of similar dummy auxiliary structures in specific structures, so as to achieve the purposes and effects of reducing the dishing degree of the photoresist layer and improving the alignment precision of the photoetching alignment mark.

In one embodiment of the present application, the method of fabricating a semiconductor structure may further include, after forming the scribe line 300 and the dummy auxiliary structure 400 located in the partial scribe line 300, and forming the plurality of storage stack structures 210, depositing a dielectric layer 500 over the stacked structure 200, the dielectric layer 500 may at least partially fill the void existing in the scribe line 300 and cover the top surface of the stacked structure 200. Specifically, the material of the dielectric layer 500 may include silicon oxide, for example.

In summary, in the method for manufacturing a semiconductor structure provided by the present application, the dummy auxiliary structure between the alignment mark and the adjacent storage stack structure is disposed in the scribe line including the alignment mark, so that uniformity and consistency of the photoresist layer formed in the area above the alignment mark are improved, and the degree of dishing generated in the area due to the height difference between the storage stack structure and the scribe line is reduced, thereby being beneficial to ensuring the optical path of the light beam when the alignment mark is optically aligned in the photolithography alignment process, ensuring accuracy and integrity of optical alignment signal transmission, and improving alignment accuracy of the alignment mark. The alignment problem of the semiconductor product with the higher lamination structure can be solved, the reliability of the semiconductor structure can be improved, and the product yield can be improved.

Although exemplary methods and structures for fabricating a semiconductor structure are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. In addition, the illustrated layers and materials thereof are exemplary only.

The above description is only illustrative of the embodiments of the application and of the technical principles applied. It will be appreciated by those skilled in the art that the scope of the application is not limited to the specific combination of the above technical features, but also encompasses other technical solutions which may be formed by any combination of the above technical features or their equivalents without departing from the technical concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.

Claims

1. A semiconductor structure, comprising:

a substrate;

a plurality of storage stacked structures located on the substrate, adjacent storage stacked structures being separated from each other by dicing streets;

an alignment mark located in an area of the substrate exposed within the scribe line for optical alignment; and

and the dummy auxiliary structure is positioned on the substrate and in the cutting channel containing the alignment mark, and the cross section shape of the dummy auxiliary structure on any plane parallel to the substrate is the same.

2. The semiconductor structure of claim 1, wherein a height of the dummy assist structure is equal to a height of the storage stack structure in a direction perpendicular to the substrate.

3. The semiconductor structure of claim 1, wherein, in a width direction of the scribe line including the alignment mark,

the dummy assist structure is located between the alignment mark and the adjacent storage stack structure.

4. The semiconductor structure of claim 1, wherein along a length of said scribe line containing said alignment mark,

the dummy auxiliary structure and the adjacent storage stack structure are disposed parallel to each other.

5. The semiconductor structure of claim 1, wherein the length of the dummy auxiliary structure is greater than the length of the alignment mark along the length direction of the scribe line including the alignment mark, and both ends of the dummy auxiliary structure protrude from both ends of the alignment mark, respectively.

6. The semiconductor structure of claim 1, wherein there are a plurality of the dummy auxiliary structures in the scribe line including the alignment mark.

7. The semiconductor structure of claim 6, wherein the plurality of dummy assist structures are spaced apart from one another.

8. The semiconductor structure of claim 6, wherein the cross-sectional shapes of the plurality of dummy auxiliary structures are identical to each other on a same plane parallel to the substrate.

9. The semiconductor structure of any one of claims 1-8, wherein the memory stack structure comprises a plurality of sacrificial layers and interlayer insulating layers alternately stacked, an

The dummy auxiliary structure has a plurality of sacrificial layers and interlayer insulating layers alternately stacked as the same as the memory stack structure.

10. The semiconductor structure of any one of claims 1-8, wherein the semiconductor structure further comprises:

And the dielectric layer is positioned in the gap existing in the cutting channel and on the top surface of the semiconductor structure.

11. A method of fabricating a semiconductor structure, the method comprising:

forming an alignment mark exposed on the surface of a substrate in the substrate, wherein the alignment mark is used for realizing optical alignment;

forming a laminated structure on the substrate; and

and removing part of the laminated structure to form a cutting channel penetrating the laminated structure to the substrate, and reserving part of the laminated structure in the cutting channel containing the alignment mark to form a dummy auxiliary shape structure, wherein the cross section shape of the dummy auxiliary shape structure on any plane parallel to the substrate is the same.

12. The method of claim 11, wherein removing a portion of the laminate structure to form a scribe line through the laminate structure to the substrate, and forming a dummy auxiliary structure in the scribe line including the alignment mark comprises:

a mask layer is formed and a mask layer is formed,

etching the cutting channel region of the laminated structure through the mask layer, and reserving part of the laminated structure in the cutting channel region containing the alignment mark to form the dummy auxiliary structure.

13. The method of claim 11, wherein the stacked structure includes sacrificial layers and interlayer insulating layers alternately stacked, the dummy assist structure having the same alternately stacked sacrificial layers and interlayer insulating layers as the stacked structure.

14. The method of claim 11, wherein the substrate is oriented in a direction perpendicular to the substrate,

the height of the dummy auxiliary structure is equal to that of the laminated structure.

15. The method of claim 11, wherein, in a width direction of the dicing street including the alignment marks,

and reserving a part of the laminated structure between the alignment mark and the adjacent laminated structure to form the dummy auxiliary structure.

16. The method of claim 11, wherein the dummy auxiliary structure and the adjacent stacked structure are formed parallel to each other along a length direction of the scribe line including the alignment mark.

17. The method of claim 11, wherein, along a length of the scribe line including the alignment mark,

the length of the dummy auxiliary structure is longer than that of the alignment mark, and two ends of the dummy auxiliary structure protrude out of two ends corresponding to the alignment mark respectively.

18. The method of claim 11, wherein a plurality of the dummy auxiliary structures are formed in the scribe line including the alignment mark.

19. The method of claim 18, wherein the plurality of dummy assist features have a spacing between each other.

20. The method of claim 18, wherein the cross-sectional shapes of the plurality of dummy auxiliary structures are identical to each other on a same plane parallel to the substrate.

21. The method of any of claims 11-20, wherein the method further comprises:

and forming a dielectric layer which fills the gap in the cutting channel and covers the top surface of the semiconductor structure.