CN114326338A

CN114326338A - Semiconductor structure and preparation method thereof

Info

Publication number: CN114326338A
Application number: CN202111661669.1A
Authority: CN
Inventors: 艾仙雄; 轩攀登; 方超; 魏禹农; 吁卫东; 袁元; 陈安
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-12
Anticipated expiration: 2041-12-31
Also published as: CN114326338B

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure provided by the present disclosure includes: a substrate; a plurality of storage stack structures on the substrate, adjacent storage stack structures being separated from each other by dicing streets; the alignment mark is positioned in the area of the substrate exposed in the cutting path and used for realizing optical alignment; and a dummy auxiliary structure located on the substrate and in the scribe line including the alignment mark.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present application relates to the field of semiconductor design and fabrication, and more particularly, to semiconductor structures and methods of making the same.

Background

Semiconductor structures and processes for their fabrication have been constantly evolving in recent years. Three-dimensional memory devices, for example, are increasingly used in the market due to their high storage density and high storage capacity.

The preparation process of the three-dimensional memory device is complex, and the preparation from a wafer to a plurality of final independent three-dimensional memory devices is completed and dozens or more of working procedures are needed. The photolithography process is one of the most important process steps, and is mainly used for copying the pattern on the mask plate onto a silicon wafer to prepare for the next process of etching, ion implantation and the like. Generally, the photolithography process is performed by a series of steps including cleaning and drying the surface of a silicon wafer, priming, spin-coating a photoresist, soft baking, alignment exposure, post-baking, developing, hard baking, etching, and inspecting. Photolithography, as a link between different processes, usually requires alignment of optical alignment marks previously formed on, for example, scribe lanes (scribes lane) of a wafer, in order to enter the next process. Therefore, the alignment accuracy of the photolithography process is critical, and directly affects the processing quality and final performance of the three-dimensional memory.

However, in the related manufacturing process, various factors affect the alignment accuracy of the photolithography process.

Disclosure of Invention

The present application provides a semiconductor structure and a method of fabricating the same that can at least partially address the above-mentioned problems affecting lithographic alignment accuracy in the related art.

An aspect of the present application provides a semiconductor structure, including: a substrate; a plurality of storage stack structures on the substrate, adjacent storage stack structures being separated from each other by dicing streets; the alignment mark is positioned in the area of the substrate exposed in the cutting channel and used for realizing optical alignment; and the dummy auxiliary structure is positioned on the substrate and positioned in the cutting path containing the alignment mark.

In one embodiment according to the present application, a height of the dummy assist structure is equal to a height of the storage stack structure in a direction perpendicular to the substrate.

In one embodiment according to the present application, the dummy auxiliary structure is located between the alignment mark and the adjacent storage stack structure in a width direction of the scribe line including the alignment mark.

In one embodiment according to the present application, the dummy auxiliary structure and the adjacent storage stack structure are disposed parallel to each other along a length direction of the scribe line including the alignment mark.

In an embodiment according to the present application, along a length direction of the scribe line including the alignment mark, a length of the dummy auxiliary structure is greater than a length of the alignment mark, and two ends of the dummy auxiliary structure protrude out of two corresponding ends of the alignment mark respectively.

In one embodiment according to the present application, there are a plurality of the dummy auxiliary structures in the scribe line including the alignment mark.

In one embodiment according to the present application, the plurality of dummy auxiliary structures are disposed spaced apart from each other.

In one embodiment according to the present application, each of the dummy auxiliary shape structures has the same cross-sectional shape in any plane parallel to the substrate.

In one embodiment according to the present application, cross-sectional shapes of the plurality of dummy auxiliary structures are identical to each other on a same plane parallel to the substrate.

In one embodiment according to the present application, the memory stack structure includes a plurality of sacrificial layers and interlayer insulating layers alternately stacked, and the dummy structures have the same plurality of sacrificial layers and interlayer insulating layers alternately stacked as the memory stack structure.

In one embodiment according to the present application, the semiconductor structure further comprises: and the dielectric layer is positioned in the gap existing in the cutting channel and on the top surface of the semiconductor structure.

Another aspect of the present application provides a method of fabricating a semiconductor structure, the method comprising: forming an alignment mark exposed to the surface of the substrate in the substrate, the alignment mark being used to achieve optical alignment; forming a stacked structure on the substrate; and removing part of the laminated structure to form a cutting channel penetrating through the laminated structure to the substrate, and keeping part of the laminated structure in the cutting channel containing the alignment mark to form a dummy auxiliary structure.

In one embodiment according to the present application, removing a portion of the stacked structure to form a scribe line extending through the stacked structure to the substrate, and forming a dummy feature in the scribe line including the alignment mark comprises: and forming a mask layer, etching the cutting path region of the laminated structure through the mask layer, and reserving part of the laminated structure in the cutting path region containing the alignment mark to form the dummy auxiliary structure.

In one embodiment according to the present application, the stacked structure includes sacrificial layers and interlayer insulating layers alternately stacked, and the dummy structure has the same sacrificial layers and interlayer insulating layers alternately stacked as the stacked structure.

In one embodiment according to the present application, a height of the dummy feature is equal to a height of the stack structure in a direction perpendicular to the substrate.

In one embodiment according to the present application, a portion of the stacked structure between the alignment mark and the adjacent stacked structure is remained along a width direction of the scribe line including the alignment mark to form the dummy structure.

In one embodiment according to the present application, the dummy auxiliary feature and the adjacent stacked structure are formed parallel to each other along a length direction of the scribe line including the alignment mark.

In an embodiment according to the present application, a length of the dummy auxiliary structure formed along a length direction of the scribe line including the alignment mark is greater than a length of the alignment mark, and two ends of the dummy auxiliary structure respectively protrude from two corresponding ends of the alignment mark.

In one embodiment according to the present application, a plurality of the dummy auxiliary structures are formed in the scribe line including the alignment mark.

In one embodiment according to the present application, the plurality of dummy auxiliary structures have a space therebetween.

In one embodiment according to the present application, the method further comprises: and forming a dielectric layer which is filled in the gap existing in the cutting channel and covers the top surface of the semiconductor structure.

Drawings

Other features, objects, and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments that proceeds with reference to the following drawings. Embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. Wherein:

FIG. 1 is a schematic diagram of a related art photoresist layer over a scribe line region to create a dishing;

FIG. 2 is a schematic top view of the structure contained in the scribe line and its vicinity of FIG. 1;

FIG. 3 is an electron microscope scanning image of a dishing generated by a photoresist layer over a scribe line region in a related art;

fig. 4 is a waveform diagram of an alignment signal collected when an alignment mark is optically aligned in the related art;

FIG. 5 is a schematic diagram of a semiconductor structure having a dummy assist feature in accordance with an exemplary embodiment of the present application;

FIG. 6 is a cross-sectional view taken along line F-F of FIG. 5;

FIG. 7 is a schematic diagram of a semiconductor structure having a dummy assist feature in accordance with yet another exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a semiconductor structure having a dummy assist feature in accordance with yet another exemplary embodiment of the present application;

FIG. 9 is a cross-sectional view taken along line G-G of FIG. 8;

FIG. 10 is a schematic diagram of a semiconductor structure having a dummy assist feature in accordance with yet another exemplary embodiment of the present application;

FIG. 11 is a flow chart of a method of fabricating a semiconductor structure according to an exemplary embodiment of the present application;

FIG. 12 is a schematic diagram of a semiconductor structure having a dummy assist feature in accordance with yet another exemplary embodiment of the present application;

FIG. 13 is a schematic diagram of a semiconductor structure without dummy assist features in a related art corresponding to the exemplary embodiment of FIG. 12;

FIG. 14 is an electron microscope scanning image of a semiconductor structure with a dummy auxiliary structure disposed such that the photoresist layer has a relatively flat upper surface, according to yet another exemplary embodiment of the present application; and

FIG. 15 is an SEM image of dishing of a photoresist layer on a surface of a semiconductor structure without a dummy feature in a related art.

Detailed Description

The present application will hereinafter be described in detail with reference to the accompanying drawings, and the exemplary embodiments mentioned herein are only for explaining the present application and do not limit the scope of the present application. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately," "about," and the like are used as approximations, not as degrees of expression, and are intended to account for inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art. It should be understood that the expressions first, second, etc. in the present description are only used for distinguishing one feature from another feature, and do not indicate any limitation of the features, particularly any order of precedence.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing" are used in this specification in an open-ended as opposed to a closed-ended fashion, and that such terms are intended to specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to mean exemplary or illustrative.

Further, in this application, when expressions such as "connected," "covered," and/or "formed at …" are used, direct or indirect contact between the respective components may be meant, unless there is an explicit other limitation or can be inferred from the context.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless otherwise indicated herein, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers. The substrate may be a single layer or comprise multiple layers.

As used herein, the term "layer" refers to a portion of material having a thickness. The layer may be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness that is less than or greater than the thickness of the continuous structure.

As used herein, the term "three-dimensional memory" refers to a semiconductor device having a vertically oriented string of memory cell transistors on a laterally oriented substrate such that the string of memory cell transistors extends in a vertical or substantially vertical direction relative to the substrate. As used herein, the term "vertical" means perpendicular or substantially perpendicular to a lateral surface of a substrate.

Numerous specific details of the present application, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. Further, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel.

In the related art, with the increase of the number of stacked structures formed on a wafer, the height difference between the main chip (main chip) region and the scribe lane (scribe lane) region is larger and larger, and the scribe lane region has a certain width, so that the coating uniformity of the photoresist is poor, and particularly, a severe dish-shaped recess (PR discing) is formed in the edge region of the scribe lane close to the adjacent storage stacked structure, and the dish-shaped recess seriously affects the alignment precision of the alignment mark in the scribe lane in the subsequent alignment exposure process, thereby affecting the precision of the photolithography operation, and finally causing the device structure to be abnormal, and affecting the product yield.

FIG. 1 is a schematic diagram showing a structure of a related art method for generating a dishing in a scribe line region after spin-coating a photoresist; FIG. 2 is a top view of FIG. 1; FIG. 3 is an electron microscope scanning image of a dishing generated in a scribe line region after spin coating a photoresist in the related art; fig. 4 is a graph of the intensity of alignment signals obtained at different positions of the alignment marks in the optical alignment process of the alignment marks shown in fig. 3 (or fig. 1 and 2).

Referring to fig. 1 and 2, the stack structure 210' for detection located in the scribe line 300 and the storage stack structure 210 separated by the scribe line 300 comprise the same stack and have the same height, and the height position of the scribe line 300 in fig. 1 is the position indicated by the arrow a in fig. 1, i.e. the position of the top surface of the substrate 100. It can be seen from fig. 1 that there is a height difference between the stack structure for detection 210 'and the scribe line 300, i.e. the height of the stack structure for detection 210' (or the storage stack structure 210), and therefore it can be understood that the greater the number of layers of the storage stack structure 210 in the semiconductor structure, the greater the height difference between the semiconductor structure and the scribe line 300.

As can also be seen in FIG. 1, a dielectric layer 500 is formed over the scribe line 300 and a photoresist layer 600 is formed over the dielectric layer 500. While the dielectric layer 500 is deposited to fill the scribe line 300, the dielectric layer 500 is deposited in the non-scribe line region of the semiconductor structure (e.g., the top surface of the storage stack structure 210 or the detection stack structure 210 '), and at the position where the detection stack structure 210 ' is adjacent to the scribe line, because of the above height difference, the portion of the formed dielectric layer 500 located at the top surface of the detection stack structure 210 ' is higher than the portion filled in the scribe line 300, and the transition region of the formed dielectric layer 500 from the top surface of the detection stack structure 210 ' to the top surface filled in the scribe line 300 forms a curved portion close to an arc, as the region circled by the dotted line B in fig. 1, and the extension length of the curved portion from the sidewall of the detection stack structure 210 ' can be denoted as D2. It is understood that the transition region of the dielectric layer 500 formed on the top surface of the storage stack structure 210 to the dielectric layer 500 formed in the scribe line 300 may also have a similar curved portion. On the basis, the photoresist layer 600 is applied, which may further cause the photoresist layer 600 to be applied unevenly and uniformly, for example, a portion of the photoresist layer 600 formed on the curved transition portion of the dielectric layer 500 may generate a relatively larger range of curved transition region, which may be referred to as a dishing (PR discing) of the photoresist layer, as a portion encircled by a dashed line box C in fig. 1, and the extension length of the curved transition portion from the sidewall of the stacked structure for detection 210' may be denoted as D3. The distance between the side of the alignment mark 700 close to the stacked structure for inspection 210 'and the sidewall of the stacked structure for inspection 210' in fig. 1 can be denoted as D1, and as can be seen from fig. 1, the part of the transition curved surface portion (the portion corresponding to the distance D3) of the photoresist layer 600 covering the alignment mark 700 can be denoted as D4 in the figure. It can be seen that the transitional curved surface portion of the photoresist layer 600 covers most of the area to the left of the center O of the alignment mark 700, and the portion not covered by the transitional curved surface portion of the photoresist layer 600 is only the portion shown as D5 away from the center O of the alignment mark 700.

Fig. 2 is a top view of fig. 1, and it should be noted that since the photoresist layer 600 is located at the uppermost layer of the semiconductor structure, if the corresponding relationship is completely according to the view, only the photoresist layer 600 located at the uppermost layer will be shown in fig. 2, and in order to more conveniently understand the corresponding positional relationship between the structures of each part, more contents are schematically shown in fig. 2. Examples include: the position of the alignment mark 700 in the scribe line 300, the relative positions of the alignment mark 700 and the stack structure 210' for detection located in the scribe line 300, the storage stack structures 210 separated by the scribe line 300 in the width direction of the scribe line 300, and the region 220 located between the storage stack structures 210 and the scribe line 300, and the dielectric layer 500 filled in the scribe line 300, the photoresist layer 600 covering the region 220, and the like are schematically shown. It is understood that the illustration in fig. 2 is merely exemplary, for example, the dielectric layer 500 may be filled not only in the scribe line 300 but also in the region 220, and the dielectric layer 500 may also be covered on the storage stack structure 210; for example, the photoresist layer 600 may cover not only the dielectric layer 500 formed in the region 220, but also the dielectric layer 500 filled in the scribe line 300 and the dielectric layer 500 deposited on the top surface of the memory stack 210. In the exemplary semiconductor structure shown in fig. 2, a region 220 is included between the memory stack structure 210 and the scribe line 300, and the region 220 and the memory stack structure 210 are also part of a main chip (main chip) region, except that the region 220 has no stacked structure due to the design requirement of the semiconductor structure, i.e., the region 220 is similar to the scribe line 300 and is located on the top surface of the substrate 100. Therefore, the storage stack structure 210 has the same height difference with the region 220 and the scribe line 300. It is to be understood that in other portions of the exemplary semiconductor structure or in other exemplary semiconductor structures, the two sides along the width direction of the scribe line do not necessarily have the regions 220 shown.

Referring to fig. 2, in combination with the above description, it can be understood that, in the width direction of the scribe line 300, also due to the height difference between the storage stack structure 210 and the region 220 and the scribe line 300, the deposited dielectric layer 500 also generates an arc-shaped curved portion similar to the portion circled by the dashed line frame B in fig. 1 in the transition region from the top surface of the storage stack structure 210 to the region 220 and the scribe line 300. The portion of the photoresist layer 600 formed over the curved transition region of the dielectric layer 500 also produces a relatively larger area of curved transition region of the photoresist layer, i.e., a dishing (PR discing) of the photoresist layer, similar to the portion circled by the dashed line box C in fig. 1.

Referring to the sem image of fig. 3, the extended length of the curved transition portion of the photoresist layer 600 can be denoted as D6, and the length of the region where the curved transition portion (or the dished portion) of the photoresist layer 600 covers the alignment mark 700 can be denoted as D7, in fig. 3, the dimension of D7 obviously occupies more than half of the length of the alignment mark 700 along the extension direction of the scribe line.

Alignment marks 700 may be used for optical alignment in a lithographic process, and collecting and analyzing information of alignment beams that reach the alignment marks and are reflected back may be used to perform the alignment operation. It will be appreciated that the alignment beam tends to deflect uncontrollably as it passes through the curved transition portion of the photoresist layer 600, i.e., the curved transition portion of the photoresist layer 600 affects the optical path of the alignment beam and, of course, the return light after reaching the alignment mark. Therefore, the curved transition portions of the photoresist layer 600 may significantly affect the accuracy and integrity of the alignment signals when aligning the alignment marks 700, in other words, the alignment signals collected through the curved transition portions of the photoresist layer 600 are likely to be incomplete, some signals may have been lost, and some collected signals are likely to be biased and inaccurate. If the alignment operation is performed based on such an alignment signal, the alignment accuracy is obviously not guaranteed, and the accuracy of the subsequent semiconductor structure processing technology is further not guaranteed, which affects the production quality of the semiconductor structure.

Referring to fig. 4, a waveform diagram representing the strength of the collected optical alignment signal is obtained when the alignment mark 700 shown in fig. 3 or fig. 1 is optically aligned in the related art. The abscissa in fig. 4 corresponds to a length value of the alignment mark 700 shown in, for example, fig. 3 or fig. 1 along the extension direction of the street 300, wherein the position of the point L0 in the middle of the abscissa corresponds to the geometric center of the alignment mark 700 shown in, for example, fig. 3 or fig. 1 along the extension direction of the street 300, i.e., the position of the center line O in fig. 3 or fig. 1. The ordinate in fig. 4 represents the intensity information of different optical alignment signals collected for different positions of the alignment mark 700 in the abscissa. It should be noted that, the intensity and integrity of the signal are mainly described and discussed with reference to the shape of the outer contour of the waveform diagram in fig. 4, and the local information such as the different gray gradients in the waveform diagram is not a main consideration here. As can be seen from fig. 4, on the left side centered at point L0 on the abscissa, the collected optical alignment signals corresponding to the left half of alignment mark 700 are significantly weaker and have a larger deviation, especially at the portion located at the left end away from the center point L0, as circled by the dashed box E in fig. 4. In contrast, on the right side of the point L0 on the abscissa, the collected optical alignment signals corresponding to the right half of the alignment mark 700 are more clearly symmetric, for example, the waveform outline of the right half is approximately vertically symmetric with respect to the Sg0 line shown on the ordinate in fig. 4. As can be understood from the distribution of the photoresist layer 600 in fig. 1, above the left half of the alignment mark 700, which is located at the center, the above-mentioned dished recess portion of the photoresist layer 600 is also the portion with a large variation of the curve waveform of the dished recess, and it can be seen that the dished recess generated by the photoresist layer 600 has a serious influence on the optical alignment operation of the photoresist mark 700.

Similarly, in the width direction of the scribe line 300, the photoresist layer 600 also generates a dishing in the transition region from the top surface of the storage stack 210 to the region 220 and the scribe line 300, which also causes the above-mentioned problem affecting the integrity and accuracy of the alignment signal during the optical alignment process for the photolithography alignment mark 700.

Moreover, it can be understood that as the number of stacked layers included in the storage stack structure 210 increases, the height difference between the storage stack structure 210 and, for example, the region 220 or the scribe line 300 increases, the photoresist layer 600 forms the above-mentioned dishing more seriously, and thus the region in the scribe line, where the alignment mark 700 disposed on the substrate is covered by the overlying dishing, is larger, and the optical alignment operation for the alignment mark 700 is affected more badly.

In view of the above problems in the related art, the present application provides a semiconductor structure, which can reduce the dishing at least to some extent and improve the alignment precision with the alignment mark in the photolithography process at least to some extent.

The present application will now be described in detail with reference to the drawings and specific embodiments thereof.

Fig. 5 illustrates a top view of a semiconductor structure according to an exemplary embodiment of the present application, and fig. 6 is a cross-sectional view of fig. 1 taken along line F-F. As shown in fig. 5 and 6, the semiconductor structure provided according to the exemplary embodiment of the present application may include: a substrate 100 and a plurality of storage stack structures 210 located on the substrate 100, adjacent storage stack structures 210 being separated from each other by a scribe line 300, the scribe line 300 may include, for example, a transverse scribe line 300-1 and a longitudinal scribe line 300-2; an alignment mark 700 located in a region of the substrate 100 exposed within the scribe line 300, the alignment mark 700 being usable to achieve optical alignment in a photolithography process; and dummy shapes 400 on the substrate 100 and in the scribe line 300 including the alignment mark 700. In one embodiment, the semiconductor structure may further include a dielectric layer (not shown in fig. 5 and 6), which may be filled in the void existing in the scribe line 300 and may also cover, for example, the top surface of the storage stack structure 210.

In one embodiment, the dummy auxiliary structure 400 may have an equal height to the storage stack structure 210 in a direction perpendicular to the substrate 100. In one embodiment, the storage stack structure 210 may include, for example, a plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked, and the dummy structure 400 may have the same plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked as the storage stack structure 210.

In one embodiment, the scribe line 300-2 includes an alignment mark 700, and dummy auxiliary structures 400-1 and 400-2 are respectively disposed between the alignment mark 700 and the storage stack structures 210-1 and 210-2 adjacent to both sides along the width direction of the scribe line 300-2. In the semiconductor structure shown in fig. 5, the alignment mark 700 is located at a position near the middle in the width direction of the scribe line 300-2, and the two dummy structures 400-1 and 400-2 are disposed substantially symmetrically with respect to the center in the width direction of the scribe line 300-2. The dummy assistant structures 400-1 and 400-2 may be advantageously disposed to support a photoresist layer subsequently formed over the scribe line 300-2, thereby advantageously mitigating the formation of dishing as described above to some extent, and thus advantageously improving the alignment accuracy of the alignment mark 700 in a subsequent photolithography process. In other embodiments, the dummy auxiliary structure 400 may be disposed only between the alignment mark 700 and the adjacent storage stack structure 210. In other embodiments, the dummy auxiliary structures 400-1 and 400-2 respectively disposed between the alignment mark 700 and the two adjacent storage stack structures 210-1 and 210-2 may also be asymmetric with respect to the center of the scribe line 300-2 in the width direction. In other embodiments, the alignment mark 700 may be disposed off-center in the width direction of the scribe line 300-2. The arrangement of fig. 5 and 6 is merely exemplary and not limiting.

Furthermore, the dummy structures 400 may have the same cross-section in any of the different planes parallel to the plane of the substrate 100, in other words, the dummy structures 400 may be an equal cross-section. The cross section of the dummy auxiliary structure 400 may be a rectangular shape as shown in fig. 5, or may be designed into other shapes as needed, which is not specifically limited in this application. In another embodiment, the dummy auxiliary structure 400 may also be a non-uniform cross-section structure in a vertical direction, e.g., perpendicular to the substrate 100, e.g., the dummy auxiliary structure 400 may have a gradually narrowing or gradually enlarging cross-section from bottom to top in the vertical direction perpendicular to the substrate 100.

Different dummy structures 400 disposed in a semiconductor structure may have the same cross-section as each other in any plane parallel to the plane of the substrate 100, such as the dummy structures 400-1 and 400-2 shown in FIG. 5, which may have the same rectangular cross-section. In other embodiments, different dummy auxiliary structures may have the same cross-section with other shapes, such as a trapezoidal cross-section. In other embodiments, different dummy features may have cross-sections of different shapes or sizes in the same plane parallel to the substrate 100, as desired.

In one embodiment, the dummy auxiliary structure 400 and the adjacent storage stack structures 210 are disposed parallel to each other along the length direction of the scribe line 300 including the alignment mark 700. For example, in FIG. 5, the dummy auxiliary structure 400-1 is disposed parallel to the storage stack structure 210-1 and the dummy auxiliary structure 400-2 is disposed parallel to the storage stack structure 210-2 along the length of the longitudinal scribe line 300-2. In other embodiments, the dummy auxiliary structure 400 and the adjacent storage stack structure 210 may not be disposed in parallel, for example, they may have a certain angle therebetween according to the design requirement, which is not intended to be limited herein.

In one embodiment, the street 300-2 extends in a longitudinal direction, and the street 300-2 includes alignment marks 700 therein. In the longitudinal extension direction along the scribe line 300-2, the lengths of the dummy auxiliary structures 400-1 and 400-2 are both greater than the length of the alignment mark 700, and the two ends of the dummy auxiliary structures 400-1 and 400-2 along the length direction respectively protrude from the two corresponding ends of the alignment mark 700. The length of the dummy auxiliary structure 400 is greater than the length of the alignment mark 700, and both ends of the dummy auxiliary structure 400 are longer than both ends corresponding to the alignment mark 700 along the length direction, which may be beneficial to better support, for example, the dielectric layer 500 and/or the photoresist layer 600 formed above the alignment mark 700 in the subsequent process, and is beneficial to at least reduce the occurrence of dishing of the photoresist layer above the alignment mark 700 to a certain extent, thereby being beneficial to reducing the adverse effect of the dishing of the photoresist layer on the optical path of the alignment beam when the alignment mark 700 is optically aligned, and being beneficial to ensuring the alignment accuracy of the alignment mark in the photolithography process. In another embodiment, the dummy auxiliary structure 400 may be formed by several segments, the total length of the whole structure 400 formed by combining the segments may be greater than the length of the alignment mark 700, and both ends of the whole structure 400 formed by combining the segments in the length direction are longer than both ends of the alignment mark 700, as shown in fig. 7. It is understood that the pattern unit of the dummy auxiliary structure 400 may be configured according to industry design rule (design rule), for example, in a specific process operation of an embodiment, the dummy auxiliary structure 400 may be configured according to the pattern unit of another pattern (pattern) on the mask, for example, and the present application is not limited thereto.

Fig. 8 shows a top view of a semiconductor structure according to another exemplary embodiment of the present application, and fig. 9 is a cross-sectional view of fig. 8 along line G-G. As shown in fig. 8 and 9, according to the semiconductor structure of this exemplary embodiment, the vertical scribe line 300-2 includes an alignment mark 700 therein, and a plurality of dummy auxiliary structures 400 are respectively disposed between the alignment mark 700 and the two adjacent storage stack structures 210-1 and 210-2.

In one embodiment, a plurality of dummy shapes 400 between the alignment mark 700 and the adjacent storage stack structure 210-1 or 210-2 are disposed at a distance from each other, as shown in FIG. 8. In other embodiments, some or all of the plurality of dummy auxiliary shape structures 400 between the alignment mark 700 and the adjacent storage stack structure 210 may not have a pitch therebetween. In other embodiments, the plurality of dummy auxiliary structures 400 between the alignment mark 700 and the adjacent storage stack structures 210 may have equal spacing or unequal spacing with respect to each other.

Similar to the description above, each of the plurality of dummy auxiliary structures 400 located between the alignment mark 700 and the adjacent storage stack structure 210 may be a uniform cross-section. And each dummy auxiliary structure may have the same cross section as each other, for example, a rectangular cross section. In other embodiments, each of the plurality of dummy auxiliary structures 400 located between the alignment mark 700 and the adjacent storage stack structure 210 may also be a non-uniform cross-section, for example, may have a cross-section gradually shrinking or gradually enlarging from bottom to top along a vertical direction perpendicular to the substrate 100. And the respective dummy structures may have different cross sections from each other as necessary.

In one embodiment, the plurality of dummy auxiliary shape structures 400 located between the alignment mark 700 and the adjacent storage stack structures 210 may have an equal height to the storage stack structures 210 in a direction perpendicular to the substrate 100. In one embodiment, the storage stack structure 210 may include, for example, a plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked, and the plurality of dummy auxiliary shape structures 400 may each have the same plurality of sacrificial layers and interlayer insulating layers (not shown) alternately stacked as the storage stack structure 210.

In summary, in the scribe line 300 including the alignment mark 700, the dummy auxiliary structure 400 may be disposed between the alignment mark 700 and the storage stack structures 210 adjacent to both sides. One or more dummy auxiliary structures 400 may be selectively disposed according to a difference in a spacing distance between the alignment mark 700 and the two adjacent storage stack structures 210, the dummy auxiliary structures 400 may have the same height as the adjacent storage stack structures 210 and may be disposed in parallel with the adjacent storage stack structures 210, and the length of the dummy auxiliary structures 400 may be greater than the length of the alignment mark 700 and both ends may be longer than the alignment mark 700. By providing one or more dummy assist structures 400 including, but not limited to, the above-mentioned features, the problem of affecting the optical alignment accuracy of the alignment mark 700 in the photolithography process due to the severe dishing of the subsequent photoresist layer caused by the large height difference between the storage stack structure 210 and the scribe line 300 can be alleviated (see the above-mentioned detailed description section). Specifically, the one or more dummy auxiliary structures 400 may provide more effective and uniform support for a photoresist layer subsequently formed over the entire semiconductor structure, and at least reduce the occurrence of dishing in the photoresist layer to some extent, and when a light beam is used in a photolithography process to optically align an alignment mark 700 on a substrate surface in a scribe line, the adverse effect of the dishing on an alignment light beam path may be reduced, which is beneficial to ensuring the accuracy of optical alignment for the alignment mark 700, thereby facilitating the accuracy of operations of subsequent processes to be performed after alignment, such as etching, and the like, and providing help to improve the production quality of the semiconductor structure.

Referring to fig. 2 again, for the case shown in fig. 2, the scribe line 300 includes an alignment mark 700, and there is also a region 220 between the scribe line 300 and the storage stack structures 210 adjacent to both sides along the width direction of the scribe line 300, and the region 220 is located at the same height as the scribe line and has the same height difference with the storage stack structures 210. To improve the alignment accuracy for the alignment mark 700, a plurality of dummy auxiliary structures 400-3 may be respectively disposed between the alignment mark and the storage stack structures 210 on both sides, as shown in fig. 10, for example.

In addition, in the scribe line 300 shown in fig. 2, there is a stacked structure 210 'for detection at a distance D1 from the alignment mark 700 along the length direction of the scribe line 300, and as described above, since the stacked structure 210' for detection and the scribe line have the same height difference, the alignment accuracy of the alignment mark 700 is seriously affected. For this case, for example, a dummy structure 400-4 may be disposed between the stack structure 210' for detection and the alignment mark 700, as shown in fig. 10. Similar to the technical effect of the dummy auxiliary structure 400, the dummy auxiliary structures 400-3 and 400-4 can also be used to improve the alignment accuracy of the alignment mark 700 in this embodiment, and the principle thereof can be known in conjunction with the above description, and therefore, the detailed description thereof is omitted here.

Another aspect of the present application also provides a method of fabricating a semiconductor structure as described above, with fig. 11 being a flow chart of the method 1000. Referring to fig. 11 and other related structural drawings, a method 1000 of fabricating a semiconductor structure may include the steps of:

s1: forming an alignment mark 700 in the substrate 100 exposed to the surface of the substrate 100, the alignment mark 700 being usable to achieve optical alignment;

s2: forming a stacked structure 200 on a substrate 100; and

s3: part of the stacked structure 200 is removed to form a scribe line 300 extending through the stacked structure 200 to the substrate 100, and part of the stacked structure 200 is left in the scribe line 300 including the alignment mark 700 to form the dummy auxiliary structure 400.

The specific processes of the steps of the above-mentioned preparation method 1000 will be further described in detail with reference to the accompanying drawings.

According to step S1 of the method 1000, the substrate 100 is first set, and an alignment mark 700 exposed on the surface of the substrate 100 is formed in a specific area (e.g., a partial area where a scribe line is to be formed later) of the substrate 100, where the alignment mark 700 can be used to achieve optical alignment in a subsequent photolithography process, as shown in fig. 5 and 6.

In various embodiments of the present application, the provided substrate 100 may, for example, include at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. In one embodiment, substrate 100 is, for example, a doped monocrystalline silicon substrate. The substrate 100 may be a P-type substrate or an N-type substrate, and the substrate 100 may further include an N-well and/or a P-well. In other embodiments, the substrate 100 may also be a composite substrate. It is to be understood that the present application is not limited thereto and the substrate 100 may be arranged and selected according to actual needs. In addition, the pattern and the setting process of the alignment mark 700 may be selected according to the requirements in the embodiments, and the application is not intended to limit the same.

The stacked structure 200 is formed on the substrate 100 according to step S2 in the method 1000, which may be achieved by one or more deposition processes. Wherein the deposition process includes, but is not limited to, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof. It is to be understood that in particular embodiments, the number and thickness of the sacrificial layers and the interlayer insulating layers may be specifically set as desired. In addition, materials of the sacrificial layer and the interlayer insulating layer may be selected from suitable materials known in the art. For example, the interlayer insulating layer may be an oxide layer (such as silicon oxide), and the sacrificial layer may be a nitride layer (such as silicon nitride). Further, it should be understood by those skilled in the art that the stacked structure 200 may include one or more stacks, that is, the stacked structure 200 may be formed by a single stack of stacks, or may be formed by a plurality of stacks sequentially stacked, wherein the stack includes a plurality of sacrificial layers and interlayer insulating layers alternately stacked in a direction perpendicular to the substrate.

According to step S3 of the method 1000, a portion of the stacked structure 200 is removed to form a scribe line 300 extending through the stacked structure 200 to the substrate 100, and a portion of the stacked structure 200 is left in the scribe line 300 including the alignment mark 700 to form the dummy auxiliary structure 400. At least one dicing lane 300 is formed in the stacked structure 200 to divide the stacked structure 200 into a plurality of storage stack structures 210 (see fig. 12). The method for forming the scribe line 300 may be a dry etching process such as deep ion reactive etching (RIDE) or a wet etching process using phosphoric acid as an etchant, and in practical applications, the method for forming the scribe line 300 includes, but is not limited to, the above-mentioned dry etching process and wet etching process.

Taking the formation of the scribe line 300 by using a dry etching process as an example, specifically, a mask layer is formed on the side of the stacked structure 200 away from the substrate 100; the mask layer is patterned to form a pattern of scribe lines therein, and the stack 200 is etched through the pattern on the mask layer using an etchant to form at least one scribe line 300.

In the embodiment of the present application, the dummy auxiliary structure 400 may be formed in the scribe line 300 including the alignment mark 700, and specifically, as described above, a mask layer is formed on the side of the stacked structure 200 away from the substrate 100; patterning the mask layer to form a pattern of scribe lines therein and a structure pattern in the scribe lines except for the pre-set dummy structures, etching the stacked structure 200 with an etchant through the scribe line pattern, removing a portion of the stacked structure 200 in the scribe line region to form scribe lines 300, and forming dummy structures 400 in the unremoved portions of the stacked structure 200 remaining in the scribe line region. The dummy feature 400 and the stack 200 may have the same alternating stack structure and have the same height. In one embodiment, the dummy auxiliary structures 400 and the adjacent storage stack structures 210 may be formed parallel to each other along the length direction of the scribe line 300 including the alignment mark 700. In one embodiment, the dummy auxiliary structure 400 may be formed to have a length greater than the length of the alignment mark adjacent thereto, and both ends of the dummy auxiliary structure 400 may be longer than the corresponding ends of the alignment mark. In various embodiments, the shape, number and arrangement of the dummy auxiliary structures 400 may be set according to specific requirements, and the mask layer may be patterned according to the setting, so as to finally form the dummy auxiliary structures 400 with corresponding shape, number and arrangement. For example, a dummy assist feature as shown in fig. 5, 8, or 10 may be formed in the semiconductor structure.

Further, in one embodiment, a mask layer is formed on a side of the stacked structure 200 away from the substrate 100; the mask layer is patterned, for example, to set the pattern as a pattern of a remaining structure except for a plurality of dummy auxiliary structures 400 arranged at equal intervals on the scribe line 300, the stacked structure 200 is etched through the pattern using an etchant, a portion of the stacked structure 200 is removed in the scribe line region to form the scribe line 300, and an unremoved portion of the stacked structure 200 remaining in the scribe line region forms a plurality of dummy auxiliary structures 400 arranged at equal intervals on the scribe line region, as shown in fig. 8, 10, or 12.

In one embodiment, a mask layer is formed on the side of the stacked structure 200 away from the substrate 100; the mask layer is patterned, for example, to remove a pattern of a remaining structure other than the plurality of dummy auxiliary structures 400 having the same cross section as each other in a direction perpendicular to the substrate 100 on the scribe line 300, etch the stacked structure 200 through the pattern using an etchant, remove a portion of the stacked structure 200 in the scribe line region to form the scribe line 300, and form a plurality of dummy auxiliary structures 400 having the same cross section as each other in a direction perpendicular to the substrate 100 on the unremoved portion of the stacked structure 200 in the scribe line region, as shown in fig. 8, 10, or 12.

In one embodiment, a mask layer is formed on the side of the stacked structure 200 away from the substrate 100; the mask layer is patterned, for example, to set the pattern as a pattern of a remaining structure except for a plurality of dummy auxiliary structures 400 having a rectangular cross section, which are regularly arranged and are preset on the scribe line 300, the stacked structure 200 is etched by using an etchant through the pattern, a part of the stacked structure 200 is removed in the scribe line region to form the scribe line 300, and the unremoved part of the stacked structure 200 remaining in the scribe line region forms a plurality of dummy auxiliary structures 400 regularly arranged, each dummy auxiliary structure 400 having a rectangular cross section in a direction perpendicular to the substrate 100 in a direction perpendicular to a longitudinal extension direction of the scribe line 300, as shown in fig. 8, 10, or 12.

It should be noted that the above-mentioned formation manner of the dummy structures is only exemplary, and in other embodiments, the dummy structures may be formed by other methods or means, and the material thereof may also include other materials, rather than the exactly same stack structure as the memory stack structure. The present application is not limited thereto.

In an embodiment, the arrangement of the dummy auxiliary structures 400 in the scribe line 300 may be designed specifically as required, and in one embodiment, referring to fig. 5, the scribe line 300 has a width of, for example, 80 μm, an alignment mark 700 is disposed near the center of the scribe line 300, the alignment mark 700 has a width of, for example, 30 μm, and the space between the alignment mark 700 and the one-side storage stack structure 210 is about 25 μm, for example, one dummy auxiliary structure 400 may be disposed on each of two sides of the alignment mark 700 in the scribe line 300, the width of the dummy auxiliary structure 400 may be set to, for example, 15 μm, and the space between the dummy auxiliary structure 400 and the alignment mark may be set to, for example, 5 μm, so that the dummy auxiliary structures 400 on two sides of the alignment mark 700 are arranged approximately symmetrically. Of course, it can be understood by those skilled in the art that more or less dummy auxiliary structures 400 may be arranged regularly in order to improve the uniformity and consistency of photoresist coating and reduce dishing, but the number, arrangement pitch and arrangement of the dummy auxiliary structures 400 may have many different design forms, and the present application does not limit the number, arrangement pitch and arrangement manner.

Fig. 12 illustrates another embodiment of the present application, in which eight dummy structures 400 are exemplarily formed in the area of the scribe line 300, and a photoresist layer 600 formed thereon may have a nearly horizontal upper surface. In contrast, in the semiconductor structure shown in fig. 13, the dummy structures 400 are not disposed in the areas of the scribe lines 300, and in this case, the photoresist layer 600 formed thereon generates a relatively severe dishing, as indicated by the dotted frame H.

Fig. 12 and 13 are partial views of a schematic semiconductor structure, while fig. 14 and 15 show electron microscope scanning pictures of an example coupon actually produced. The dummy sub-structures 400 are disposed in the scribe line 300 of the semiconductor structure shown in fig. 14. The dummy sub-structure 400 is not disposed in the scribe line 300 of the semiconductor structure shown in fig. 15, and fig. 15 may be understood as a partial view corresponding to a J region circled by a dashed frame in fig. 14. As is apparent from comparing fig. 14 and 15, the photoresist layer 600 formed over the scribe line 300 in which the dummy auxiliary structure 400 is disposed has a relatively flatter top surface without generating a severe dishing, whereas the photoresist layer 600 formed over the scribe line 300 in which the dummy auxiliary structure 400 is not disposed generates a relatively severe dishing. As can be seen from the above description, for a scribe line including an alignment mark in a substrate, if a severe dishing occurs in a photoresist layer formed over the scribe line, the alignment accuracy of the alignment mark in a photolithography process is affected. However, according to the method provided by the present application, by providing the appropriate dummy auxiliary structure in the scribe line, the degree of dishing generated in the photoresist layer 600 formed above the scribe line can be reduced, and it is ensured that the photoresist layer has a relatively flat upper surface, which is beneficial to improving the alignment accuracy of the alignment mark in the photolithography process, and is further beneficial to ensuring the production quality of the semiconductor structure.

It should be noted that the improvement effect of the present application on improving the alignment accuracy of the lithographic alignment marks in the scribe lines is not limited to the lithographic alignment process in a specific manufacturing step, and it can be understood that the lithographic alignment accuracy of any lithographic process requiring alignment of the lithographic alignment marks in the scribe lines in the semiconductor structure manufacturing process can be improved due to the effect of the process implemented in the present application. Furthermore, the lithographic alignment marks are not limited to the structures described above or shown in the drawings, or to the positions in the scribe line and the substrate described above, and in some embodiments, the lithographic alignment marks may be in other structures, and may be disposed in any layer structure above the substrate that may be aligned by a subsequent lithographic process, for example. For these situations, the idea provided by the present application can be also adopted to perform the setting of the dummy auxiliary structure in the specific structure, so as to achieve the purposes and effects of reducing the dishing generation degree of the photoresist layer, and improving the alignment accuracy of the photolithography alignment mark.

In one embodiment of the present application, the method for fabricating a semiconductor structure may further include, after forming the scribe line 300 and the dummy structures 400 located in a portion of the scribe line 300 and forming the plurality of memory stack structures 210, depositing a dielectric layer 500 over the stacked structure 200, wherein the dielectric layer 500 may at least partially fill a gap existing in the scribe line 300 and cover a top surface of the stacked structure 200. Specifically, the material of the dielectric layer 500 may include silicon oxide, for example.

In summary, the method for manufacturing a semiconductor structure provided by the present application improves uniformity and consistency of a photoresist layer formed in a region above an alignment mark by providing a dummy auxiliary structure located between the alignment mark and an adjacent storage stack structure in a scribe line including the alignment mark, and reduces a degree of dishing due to a height difference between the storage stack structure and the scribe line in the region, thereby facilitating to ensure a light path of a light beam when performing optical alignment on the alignment mark in a photolithography alignment process, ensuring accuracy and integrity of optical alignment signal transmission, and improving alignment accuracy of the alignment mark. The alignment problem of the semiconductor product with a higher laminated structure can be solved, the reliability of the semiconductor structure can be improved, and the yield of the product can be improved.

Although exemplary methods and structures of fabricating semiconductor structures are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A semiconductor structure, comprising:

a substrate;

a plurality of storage stack structures on the substrate, adjacent storage stack structures being separated from each other by dicing streets;

the alignment mark is positioned in the area of the substrate exposed in the cutting channel and used for realizing optical alignment; and

and the dummy auxiliary structure is positioned on the substrate and positioned in the cutting path containing the alignment mark.

2. The semiconductor structure of claim 1, wherein a height of the dummy assist structure is equal to a height of the storage stack structure in a direction perpendicular to the substrate.

3. The semiconductor structure of claim 1, wherein, along a width direction of the scribe line including the alignment mark,

the dummy assist structure is located between the alignment mark and the adjacent storage stack structure.

4. The semiconductor structure of claim 1, wherein along a length direction of the scribe line including the alignment mark,

the dummy shapes and the adjacent storage stack structures are disposed parallel to each other.

5. The semiconductor structure of claim 1, wherein the length of the dummy auxiliary structure along the length direction of the scribe line including the alignment mark is greater than the length of the alignment mark, and two ends of the dummy auxiliary structure protrude from two corresponding ends of the alignment mark.

6. The semiconductor structure of claim 1, wherein there are a plurality of said dummy assist structures in said scribe line containing said alignment mark.

7. The semiconductor structure of claim 6, wherein the plurality of dummy auxiliary structures are spaced apart from one another.

8. The semiconductor structure of claim 6, wherein each of the dummy auxiliary structures has the same cross-sectional shape in any plane parallel to the substrate.

9. The semiconductor structure of claim 6, wherein cross-sectional shapes of the plurality of dummy auxiliary structures are the same as each other in a same plane parallel to the substrate.

10. The semiconductor structure of any one of claims 1-9, wherein the storage stack structure comprises a plurality of sacrificial layers and interlayer insulating layers alternately stacked, and

the dummy structure has a plurality of sacrificial layers and interlayer insulating layers alternately stacked as the memory stack structure.

11. The semiconductor structure of any one of claims 1-9, wherein the semiconductor structure further comprises:

and the dielectric layer is positioned in the gap existing in the cutting channel and on the top surface of the semiconductor structure.

12. A method of fabricating a semiconductor structure, the method comprising:

forming an alignment mark exposed to the surface of the substrate in the substrate, the alignment mark being used to achieve optical alignment;

forming a stacked structure on the substrate; and

and removing part of the laminated structure to form a cutting channel penetrating through the laminated structure to the substrate, and keeping part of the laminated structure in the cutting channel containing the alignment mark to form a dummy auxiliary structure.

13. The method of claim 12, wherein removing portions of the stacked structure to form saw streets extending through the stacked structure to the substrate, and forming dummy assist features in the saw streets including the alignment marks comprises:

a mask layer is formed on the substrate,

and etching the cutting path region of the laminated structure through the mask layer, and reserving part of the laminated structure in the cutting path region containing the alignment mark to form the dummy auxiliary structure.

14. The method of claim 12, wherein the stacked structure includes sacrificial layers and interlayer insulating layers alternately stacked, the dummy structure having the same sacrificial layers and interlayer insulating layers alternately stacked as the stacked structure.

15. The method of claim 12, wherein, in a direction perpendicular to the substrate,

the height of the dummy structures is equal to the height of the stack structure.

16. The method of claim 12, wherein, in a width direction of the scribe line including the alignment mark,

and reserving a part of the laminated structure between the alignment mark and the adjacent laminated structure to form the dummy auxiliary shape structure.

17. The method of claim 12, wherein the dummy feature and the adjacent stack structure are formed parallel to each other along a length of the scribe line including the alignment mark.

18. The method of claim 12, wherein, along a length of the scribe line containing the alignment mark,

the length of the formed nominal auxiliary shape structure is larger than that of the alignment mark, and two ends of the nominal auxiliary shape structure respectively protrude out of two corresponding ends of the alignment mark.

19. The method of claim 12, wherein a plurality of the dummy assist structures are formed in the scribe line including the alignment mark.

20. The method of claim 19, wherein the plurality of dummy auxiliary structures are spaced apart from each other.

21. The method of claim 19, wherein each of the dummy auxiliary shape structures has the same cross-sectional shape in any plane parallel to the substrate.

22. The method of claim 19, wherein cross-sectional shapes of the plurality of dummy auxiliary structures are the same as each other in a same plane parallel to the substrate.

23. The method according to any one of claims 12-22, wherein the method further comprises:

and forming a dielectric layer which is filled in the gap existing in the cutting channel and covers the top surface of the semiconductor structure.