CN114326236A - Array substrate, display panel and display device - Google Patents

Abstract

The application relates to an array substrate, display panel and display device, array substrate is including stacking the common electrode routing layer and the data routing layer that set up in proper order, data signal in the data routing layer walks the projection extremely projection region in the common electrode routing layer, with there is not the overlap region between the distribution region of common electrode signal walking in the common electrode routing layer. The wiring position of common electrode signal wiring in the common electrode wiring layer relative to data signal wiring in the data wiring layer is changed, so that the data signal wiring in the data wiring layer is projected to a projection area in the common electrode wiring layer, and no overlapping area exists between the data signal wiring and a distribution area of the common electrode signal wiring in the common electrode wiring layer, parasitic capacitance formed between the data signal wiring and the common electrode signal wiring due to the overlapping area is avoided, voltage change of the data signal wiring cannot influence voltage of the common electrode signal wiring, and therefore the problem of transverse crosstalk is avoided.

Description

Array substrate, display panel and display device

Technical Field

The present application relates to the field of display panel technology, and in particular, to an array substrate, a display panel, and a display device.

Background

In the implementation process, the inventor finds that at least the following problems exist in the conventional technology:

with the continuous development of lcd technology, the requirements of people on viewing experience and image quality gradually increase, but the lateral crosstalk between pixels is a phenomenon that seriously affects the display image quality, and even causes the adjacent sub-pixels to emit light, thereby affecting the display color accuracy of the adjacent sub-pixels, and causing the viewing experience of users to be poor, and thus, a display panel capable of solving the problem of the lateral crosstalk between pixels is urgently needed.

Disclosure of Invention

In view of the above, it is necessary to provide an array substrate, a display panel and a display device for solving the problem of lateral crosstalk between pixels.

In order to achieve the above object, in one aspect, the present application provides an array substrate, where the array substrate includes a common electrode routing layer and a data routing layer that are sequentially stacked, a data signal routing in the data routing layer is projected to a projection area in the common electrode routing layer, and there is no overlapping area between distribution areas of common electrode signal routing in the common electrode routing layer.

Optionally, the common electrode wiring layer includes a wiring bottom layer and a first metal layer, the first metal layer is disposed on the wiring bottom layer, the first metal layer is electrically connected to the wiring bottom layer, and the first metal layer includes a gate signal wiring and a common electrode signal wiring.

Optionally, the common electrode wiring layer further includes a first insulating layer, the first insulating layer is disposed between the wiring bottom layer and the first metal layer, a through hole is disposed on the first insulating layer, and the first metal layer is electrically connected to the wiring bottom layer through the through hole.

Optionally, the trace bottom layer is an ITO trace, and the ITO trace is electrically connected to the common electrode signal trace through the through hole.

Optionally, the ITO trace and the data signal trace are distributed along the same direction, and no overlapping area exists.

Optionally, the common electrode signal trace and the data signal trace are both distributed along the same direction, and there is no overlapping area.

Optionally, the array substrate further includes:

and the second insulating layer is arranged between the first metal layer and the data wiring layer.

On the other hand, an embodiment of the present application further provides a display panel, which includes any one of the array substrates, a color film substrate, and a liquid crystal layer located between the array substrate and the color film substrate.

On the other hand, an embodiment of the present application further provides a display device, including any one of the display panels described above.

One of the above technical solutions has the following advantages and beneficial effects:

the wiring position of common electrode signal wiring in the common electrode wiring layer relative to data signal wiring in the data wiring layer is changed, so that the data signal wiring in the data wiring layer is projected to a projection area in the common electrode wiring layer, and no overlapping area exists between the distribution areas of the common electrode signal wiring in the common electrode wiring layer, parasitic capacitance formed between the data signal wiring and the common electrode signal wiring due to the overlapping area is avoided, and the voltage change of the data signal wiring cannot influence the voltage of the common electrode signal wiring by avoiding the formation of the parasitic capacitance, so that the problem of transverse crosstalk is avoided.

Drawings

Fig. 1 is a schematic view of a projection structure of an array substrate.

Fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 3 is a schematic view of a projection structure of an array substrate according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 5 is a schematic view of a projection structure of an array substrate according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of a trace base layer according to an embodiment of the present disclosure.

Fig. 8 is a schematic view of a projection structure of an array substrate according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, when a Data signal trace (Data line) in the Data trace layer 100 is projected to a projection area in the common electrode trace layer 200, an overlapping area exists between distribution areas where a common electrode signal trace (Acomline) in the common electrode trace layer 200 is located, a part framed by a dashed line frame in fig. 1 is the overlapping area, the common electrode signal trace and the Data signal trace in the overlapping area form two poles of a parasitic capacitor, that is, the parasitic capacitor is formed, when a voltage of the Data signal trace changes due to the existence of the parasitic capacitor, the voltage of the common electrode signal trace may simultaneously affect a voltage difference and a luminance difference at two ends of an electric field of a sub-pixel, so that a lateral crosstalk phenomenon may occur.

In one embodiment, as shown in fig. 2, the present embodiment provides an array substrate, where the array substrate includes a common electrode wiring layer 200 and a data wiring layer 100 stacked in sequence, a projection area of the data signal wiring in the data wiring layer 100 is projected to the common electrode wiring layer 200, and there is no overlapping area between the distribution area of the common electrode signal wiring in the common electrode wiring layer 200.

As shown in fig. 2, the Data wiring layer 100 is disposed on the common electrode wiring layer 200, the Data wiring layer 100 includes a Data signal wiring for transmitting a Data signal, the Data signal is denoted as a Data signal, the common electrode wiring layer 200 includes a common electrode signal wiring for transmitting a common electrode signal, and the common electrode signal is denoted as an atom signal.

As shown in fig. 3, the data signal traces are projected into the common electrode trace layer 200 according to a one-to-one projection ratio, or the common electrode signal traces are projected into the data trace layer 100 according to a one-to-one projection ratio, only for the purpose of placing the traces in two layers on the same plane for comparison, thereby judging whether the data signal trace and the common electrode signal trace are overlapped in the same plane, the data signal traces and the common electrode signal traces in this embodiment are designed for the purpose of preventing the two traces from overlapping when projected onto the same plane, thereby avoiding the formation of parasitic capacitance due to the overlapping of the data signal trace and the common electrode signal trace in the three-dimensional space, the formation of parasitic capacitance is avoided by avoiding the overlapping of the two wires, and the problem of transverse crosstalk between pixels is solved. The data signal traces of the data trace layer 100 may be made of any metal conductive material, such as copper, aluminum-magnesium alloy, and the like.

In one embodiment, as shown in fig. 4, the common electrode wiring layer 200 includes a wiring substrate 202 and a first metal layer 201, the first metal layer 201 is disposed on the wiring substrate 202, the first metal layer 201 is electrically connected to the wiring substrate 202, and the first metal layer 201 includes a common electrode signal wiring and a gate signal wiring.

As shown in fig. 5, the gate signal traces and the common electrode signal traces in the first metal layer 201 are projected into the trace bottom layer 202, the gate signal traces in the first metal layer 201 are denoted as Gata lines, the common electrode signal traces in the first metal layer 201 are distributed along a first direction, the gate signal traces are distributed along a second direction, the first direction is perpendicular to the stacking direction of the trace bottom layer 202 and the first metal layer 201, the second direction is perpendicular to the first direction, and the second direction is also perpendicular to the stacking direction of the trace bottom layer 202 and the first metal layer 201, that is, the gate signal traces are distributed transversely in fig. 5, and the gate signal traces are used for transmitting gate signals and are electrically connected to the gate signal traces corresponding to the connected subpixels in the same row. The common electrode signal trace is also electrically connected to the trace bottom layer 202, so that the trace bottom layer 202 transmits the common electrode signal to the common electrode signal trace.

The common electrode signal trace comprises a first part 2011, a second part 2012, a third part 2013 and a fourth part 2014, the first part 2011, the second part 2012, the third part 2013 and the fourth part 2014 can be in any shape, such as one or a combination of more than one of rectangle, circle, triangle, polygon and the like, the second part 2012, the third part 2013 and the fourth part 2014 are arranged in parallel, the second part 2012, the third part 2013 and the fourth part 2014 are all electrically connected with the first part 2011, and the common electrode signal trace is electrically connected with the trace bottom layer 202 through the first part 2011.

In one embodiment, as shown in fig. 6, the common electrode wiring layer 200 further includes a first insulating layer 203, the first insulating layer 203 is disposed between the wiring substrate 202 and the first metal layer 201, a through hole 2031 is disposed on the first insulating layer 203, and the first metal layer 201 and the wiring substrate 202 are electrically connected through the through hole 2031.

Specifically, the first insulating layer 203 is denoted as GI1, the first insulating layer 203 has a predetermined thickness, and may be made of a silicon nitride film, and the probability that the generated conductive particles conduct the common electrode and the pixel electrode can be reduced by the gate insulating layer, so as to improve the display effect of the display panel. However, in order to electrically connect the first metal layer 201 and the trace underlayer 202, a via 2031 is formed on the insulating gate layer, so that the first metal layer 201 and the trace underlayer 202 can be electrically connected by a wire passing through the via 2031 on the insulating gate layer, specifically referring to fig. 6, but the cross-sectional shape of the via 2031 is illustrated by a rectangular frame in fig. 6, but the cross-sectional shape of the via 2031 may also be circular, triangular or any other shape.

In one embodiment, the trace bottom layer is an ITO trace, and the ITO trace is electrically connected to the common electrode signal trace through the through hole.

Specifically, as shown in fig. 7, the trace bottom layer 202 is electrically connected to a driving power source or a signal trace, and obtains driving power and a signal by electrically connecting to the trace bottom layer, so that the gate signal trace and the common electrode signal trace in the first metal layer 201 can perform signal transmission, and the common electrode signal trace in the first metal layer 201 may be made of any metal conductive material, specifically, copper, aluminum-magnesium alloy, and the like.

Specifically, the ITO trace includes a fifth component 2021, a sixth component 2022, a seventh component 2023, and an eighth component 2024. The fifth part 2021, the sixth part 2022, the seventh part 2023, and the eighth part 2024 respectively correspond to four rectangles sequentially connected from top to bottom in fig. 7, the fifth part 2021 and the eighth part 2024 serve as interfaces for connecting the sub-pixel with other sub-pixels or a driving power supply, the sixth part 2022 in the ITO trace is electrically connected to the first part 2011 in the common electrode signal trace through a wire, and the wire passes through the through hole 2031 on the first insulating layer, so that the ITO trace transmits the common electrode signal to the common electrode signal trace; the lead and the common electrode signal wiring are made of the same material and are integrally formed.

In one embodiment, the ITO traces and the data signal traces are distributed along the same direction and no overlapping area exists.

Specifically, as can be seen from fig. 7, the ITO traces are distributed along a first direction, which is shown in fig. 5 that the ITO traces are longitudinally distributed, and the fifth component 2021 and the eighth component 2024 of the ITO traces are used for being electrically connected to the driving power supply or other ITO traces corresponding to the sub-pixels.

As shown in fig. 8, the Data signal trace includes a ninth component and a tenth component, the ninth component and the tenth component are parallel to each other and distributed along the first direction, that is, the ninth component and the tenth component are respectively Data _ l and Data _ r in fig. 8, the ITO trace is projected into the Data trace layer 100, or the Data signal trace is projected into the trace bottom layer 202, or the ITO trace and the Data signal trace are projected into the same plane as they are, there is no overlapping area between the area where the ITO trace is located and the area where the Data signal trace is located, fig. 8 shows that the Data signal trace is projected into the trace bottom layer by way of example, it can be seen that although the trace bottom layer 202 where the ITO trace is located under the Data trace layer 100 where the Data signal trace is located, the area where the ITO trace is located is not vertically opposite to the area where the Data signal trace is located, but is staggered and opposite to the Data signal trace.

In one embodiment, the common electrode signal trace and the data signal trace are both distributed along the same direction and there is no overlapping area.

Specifically, the common electrode signal trace and the data signal trace are both vertically distributed along the first direction, the common electrode signal trace is projected into the data trace layer 100, or the data signal trace is projected into the first metal layer 201, or the common electrode signal trace and the data signal trace are projected into the same plane as they are, and there is no overlapping area between the area where the common electrode signal trace is located and the area where the data signal trace is located, so that it can be obtained that although the first metal layer 201 where the common electrode signal trace is located under the data trace layer 100 where the data signal trace is located, the area where the common electrode signal trace is located and the area where the data signal trace is located are not vertically opposite, but are staggered opposite, and therefore parasitic capacitance cannot be formed in space between the area where the common electrode signal trace is located and the area where the data signal trace is located.

After the data signal trace is projected to the first metal layer 201, a projection result shown in fig. 8 is obtained, the middle bit line in the first metal layer 201 passes through the center of the first metal layer 201 along a first direction, the first distance is a vertical distance from a projection area, projected to the first metal layer 201, of the data signal trace to the middle bit line in the first metal layer 201, the second distance is a vertical distance from a distribution area of the common electrode signal trace to the middle bit line in the first metal layer 201, the first distance is greater than the second distance, it is indicated that the projection area corresponding to the data signal trace is located outside the distribution area corresponding to the common electrode signal trace, and the projection area corresponding to the data signal trace is parallel to the distribution area corresponding to the pixel electrode trace.

The common electrode signal traces in fig. 1 include longitudinally distributed traces and transversely distributed traces, where the transversely distributed traces are used for electrically connecting with a driving power source or common electrode signal traces corresponding to other sub-pixels, so that the common electrode signal traces and the data signal traces form parasitic capacitances in space due to the traces. In this embodiment, the bottom ITO traces that are longitudinally distributed are electrically connected to the common electrode signal traces corresponding to other sub-pixels, and the common electrode signal traces of the first metal layer 201 are electrically connected to the trace bottom layer 202 to obtain a voltage and a common electrode signal, thereby avoiding overlapping with the data signal traces in space.

In one embodiment, as shown in fig. 9, the array substrate further includes a second insulating layer 300, and the second insulating layer 300 is disposed between the first metal layer 201 and the data wiring layer 100.

Specifically, the second insulating layer 300 is denoted as GI2, and the main function of the second insulating layer 300 is to prevent the layers made of metal conductor material from touching each other, further effectively block alkali metal ions in the array substrate, enhance the anti-static discharge capability, reduce the leakage current, and improve the equivalent capacitance.

In one embodiment, as shown in fig. 9, the array substrate further includes a plating layer 400, and the plating layer 400 is disposed between the second insulating layer 300 and the data wiring layer 100.

Specifically, the coating layer 400 is made of an AS crystal coating, and the AS coating layer 400 is disposed between the second insulating layer 300 and the data wiring layer 100, so that the coating layer 400 has high hardness, and has the protection effects of ultraviolet resistance, static resistance, dust prevention, water prevention, oxidation resistance, fine scratch prevention and the like.

In one embodiment, the present application provides an array substrate, the array substrate includes a trace base layer 202, a first insulating layer 203, a first metal layer 201, a second insulating layer 300, a film coating layer 400 and a data trace layer 100, which are sequentially stacked from bottom to top, a through hole 2031 is formed on the first insulating layer 203, an ITO trace in the trace base layer 202 passes through the through hole 2031 through a wire to be electrically connected with a common electrode signal trace in the first metal layer 201, the ITO trace is longitudinally distributed in the trace base layer 202, the common electrode signal trace is longitudinally distributed in the first metal layer 201, a gate signal trace in the first metal layer 201 is transversely distributed, the data signal trace in the data trace layer 100 is projected to a projection area in the trace base layer 202, there is not only no overlapping area between projection areas corresponding to the ITO trace, but also no overlapping area between distribution areas where the common electrode signal is located, therefore, the data signal wire for transmitting the data signal and the common electrode signal wire for transmitting the Acom signal in the space cannot form two opposite electrodes, so that parasitic capacitance cannot be formed, and the Acom signal cannot be changed along with the data signal when the data signal is changed.

In an embodiment, the present embodiment further provides a display panel, where the display panel includes an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate comprises a common electrode wiring layer 200 and a data wiring layer 100 which are sequentially stacked, wherein data signal wiring in the data wiring layer 100 is projected to a projection area in the common electrode wiring layer 200, and no overlapping area exists between distribution areas of common electrode signal wiring in the common electrode wiring layer 200.

In one embodiment, the common electrode wire layer 200 includes a wire bottom layer 202 and a first metal layer 201, the first metal layer 201 is disposed on the wire bottom layer 202, the first metal layer 201 is electrically connected to the wire bottom layer 202, and the first metal layer 201 includes the common electrode signal wire and the gate signal wire.

In one embodiment, the common electrode wiring layer 200 further includes a first insulating layer 203, the first insulating layer 203 is disposed between the wiring substrate 202 and the first metal layer 201, a through hole 2031 is disposed on the first insulating layer 203, and the first metal layer 201 and the wiring substrate 202 are electrically connected through the through hole 2031.

In one embodiment, the trace bottom layer 202 is an ITO trace, and the ITO trace is electrically connected to the common electrode signal trace through the through hole.

In one embodiment, the ITO traces and the data signal traces are distributed along the same direction and have no overlapping area.

In one embodiment, the common electrode signal trace and the data signal trace are both distributed along the same direction and there is no overlapping area.

In one embodiment, the array substrate further includes a second insulating layer 300, and the second insulating layer 300 is disposed between the first metal layer 201 and the data wiring layer 100.

The invention also provides a display device, which comprises a display panel and other circuits and devices for supporting the normal operation of the display device, wherein the display device can be one of a mobile phone, a tablet personal computer, electronic paper and an electronic photo frame.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (9)

1. The array substrate is characterized by comprising a common electrode wiring layer and a data wiring layer which are sequentially stacked, wherein data signal wiring in the data wiring layer is projected to a projection area in the common electrode wiring layer, and no overlapping area exists between the data signal wiring and a distribution area of the common electrode signal wiring in the common electrode wiring layer.

2. The array substrate of claim 1, wherein the common electrode trace layer comprises a trace bottom layer and a first metal layer, the first metal layer is disposed on the trace bottom layer and electrically connected to the trace bottom layer, and the first metal layer comprises a gate signal trace and a common electrode signal trace.

3. The array substrate of claim 2, wherein the common electrode trace layer further comprises a first insulating layer, the first insulating layer is disposed between the trace bottom layer and the first metal layer, a through hole is disposed on the first insulating layer, and the first metal layer and the trace bottom layer are electrically connected through the through hole.

4. The array substrate of claim 3, wherein the trace bottom layer is an ITO trace, and the ITO trace is electrically connected to the common electrode signal trace through the through hole.

5. The array substrate of claim 4, wherein the ITO traces and the data signal traces are distributed along a same direction without an overlapping area.

6. The array substrate of claim 2, wherein the common electrode signal trace and the data signal trace are distributed along a same direction without an overlapping area.

7. The array substrate of claim 2, further comprising:

and the second insulating layer is arranged between the first metal layer and the data wiring layer.

8. A display panel, comprising the array substrate of any one of claims 1 to 7, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate.

9. A display device characterized by comprising the display panel according to claim 8.

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