CN114312914B - Universal interlocking interface tool configuration method and device - Google Patents
Universal interlocking interface tool configuration method and device Download PDFInfo
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Abstract
The invention relates to the technical field of railway signal computer interlocking, in particular to a method and a device for configuring a universal interlocking interface tool. The method comprises the following steps: s1, decomposing and defining the interlocking interface parameters according to a Boolean logic structure, and performing complete logic operation on the Boolean logic structure corresponding to all the interlocking interface parameters to generate a tree-shaped data structure; s2, decomposing the generated tree data structure according to a Boolean logic simplification algorithm, and generating and storing the tree data structure as simple AND or data; and S3, selecting an interlocking interface parameter according to actual requirements, setting a corresponding Boolean logic structure, converting the built Boolean logic graph into interlocking data of the Boolean logic structure, and performing cycle traversal calculation on the interlocking data according to a simple AND or data structure to complete the configuration of the interlocking interface. The invention greatly improves the reliability, stability and execution efficiency of the interlocking software.
Description
Technical Field
The invention relates to the technical field of railway signal computer interlocking, in particular to a method and a device for configuring a universal interlocking interface tool.
Background
With the high-speed development of high-speed railways and urban rail transit in China, a computer interlocking system is indispensable as basic type signal equipment of a rail transit signal system.
The main function of the interlock is to ensure the correct logical relationship between the approach, switch and annunciator. The interlocking interface is complex and various, and needs to interact data with a plurality of external devices.
The computer interlocking system and the bottom external interface are relay interfaces, and because the design preference of the interlocking interface signal circuits of each design institute is different, the computer interlocking software and the external circuit interface algorithm cannot be stabilized, so that the version of the interlocking software needs to be frequently updated.
The Chinese patent No. 202010350989.4 proposes a computer interlocking station data configuration method and control system, the configuration method includes: receiving the imported station yard plane drawing, identifying each station yard device and station yard line in the drawing, calling corresponding preset information in a device library, regenerating a station yard plane drawing, and generating interlocking data by using a preset rule set according to the regenerated station yard plane drawing. Said invention utilizes automatic drawing of station field diagram to reduce manual drawing workload, and is mainly used for solving the technical problems of large manual drawing workload, easy error and long debugging time. However, the above patent of the invention does not solve the problem that the interlocking software is frequently modified due to various interlocking conditions caused by various patterns of the interlocking external interface circuit.
Disclosure of Invention
The invention aims to provide a general interlocking interface tool configuration method and device, which solve the problem that the interlocking software version needs to be frequently modified and configured due to the fact that an interlocking external interface is complex in the prior art.
In order to achieve the above object, the present invention provides a universal interlock interface tool configuration method, comprising the steps of:
s1, decomposing and defining the interlocking interface parameters according to a Boolean logic structure, and performing complete logic operation on the Boolean logic structure corresponding to all the interlocking interface parameters to generate a tree-shaped data structure;
s2, decomposing the generated tree data structure according to a Boolean logic simplification algorithm, and generating and storing the tree data structure as simple AND or data;
and S3, selecting an interlocking interface parameter according to actual requirements, setting a corresponding Boolean logic structure, converting the built Boolean logic graph into interlocking data of the Boolean logic structure, and performing cycle traversal calculation on the interlocking data according to a simple AND or data structure to complete the configuration of the interlocking interface.
In one embodiment, the boolean logic structure includes a base element, a result element, a logical or gate, and a logical and gate:
the basic elements comprise input condition parameters of an interlocking interface;
the result element comprises output driving command parameters of the interlocking interface;
the input end of the logical OR gate is connected with a plurality of basic elements, and the output end outputs logical OR operation results among the basic elements;
and the input end of the logic AND gate is connected with a plurality of basic elements, and the output end outputs a logic AND operation result among the basic elements.
In an embodiment, the boolean logic simplification algorithm in step S2 further includes:
searching all tree branch structures of the generated tree data structure according to recursive traversal, and generating tree branch structure data according to the node sequence;
storing tree branch structure data according to a two-dimensional data structure to generate simple AND or data;
wherein each row of data is tree branch structure data;
each tree branch structure data includes at least one base element, at least one logical AND gate, and one result element;
the input end of each logical AND gate corresponds to only one basic element, and the output end of each logical AND gate corresponds to only one basic element or result element.
In an embodiment, the basic elements include:
basic element type, basic element address, basic element not gate switch, and basic element type device status.
In an embodiment, the basic element types include:
the system comprises annunciators, turnouts, physical sections, logical sections, train routes, shunting routes, guiding routes, protecting routes, scattered collection and function buttons.
In an embodiment, the basic element types include a traffic signal type, and the corresponding traffic signal type device states include a red light, a double yellow light, a Huang Shanhuang light, a yellow light, a green light, a guide light, a white light, a blue light, a broken light, a double yellow light, a yellow flash light, a yellow light, a green light, and a guide light;
the basic element types comprise turnout types, and the corresponding turnout type equipment states comprise positioning, inversion and quartet;
the basic element types comprise physical section types, and the corresponding physical section type equipment states comprise idle, occupied, axle counting fault, right locking and left locking;
the basic element types comprise logic section types, and the corresponding logic section type equipment states comprise idle, AT occupied, UT occupied, right locking and left locking;
the basic element types comprise train route types and corresponding train route type equipment states, wherein the train route type equipment states comprise a selecting stage, pre-locking, signal opening, normal closing, fault closing, normal unlocking and manual unlocking;
the basic element types comprise shunting route types and corresponding shunting route type equipment states, wherein the shunting route type equipment states comprise a selecting stage, pre-locking, signal opening, normal closing, fault closing, normal unlocking, midway turning unlocking and manual unlocking;
the basic element types comprise guide route types and corresponding guide route type equipment states, wherein the guide route type equipment states comprise a selecting stage, pre-locking, signal opening, normal closing, fault closing and manual unlocking;
the basic element types comprise protection route types and corresponding protection route type equipment states, wherein the protection route type equipment states comprise a selecting stage, pre-locking, normal unlocking and manual unlocking;
the basic element types comprise scattered relay types, and the corresponding scattered relay type equipment states comprise scattered suction and scattered dropping;
the basic element types comprise function button types, and the corresponding function button type equipment states comprise button lifting and button pressing.
In an embodiment, the result element includes:
result element type, result element address, and result element type device command.
In an embodiment, the result element types include a traffic signal type, and the corresponding traffic signal type device commands include a red light, a double yellow light, a green light, a guide, a white light, a blue light, a broken light, a double yellow light, a yellow flash, a yellow light, a green light, a green light, and a guide;
the result element types comprise scattered drive types, and the corresponding scattered drive type equipment commands comprise scattered drive sucking-up and scattered drive dropping.
In an embodiment, in the step S3, the performing a loop traversal calculation on the interlock data according to a simple and or data structure further includes:
selecting a simple AND or data structure corresponding to the interlocking data of the Boolean logic structure;
performing AND operation between basic elements of each row of data in the simple AND or data structure to obtain the state of a result element;
and performing OR operation between the states of the result elements of all the row data in the simple AND OR data structure to obtain the final state of the result elements.
To achieve the above object, the present invention provides a universal interlock interface tool configuration device, including:
a memory for storing instructions executable by the processor;
a processor for executing the instructions to implement the method as claimed in any one of the preceding claims.
To achieve the above object, the present invention provides a computer storage medium having stored thereon computer instructions, wherein the computer instructions, when executed by a processor, perform a method as set forth in any of the above.
The invention provides a method and a device for configuring a universal interlocking interface tool, which simplify the parameters of an interlocking interface according to a Boolean logic structure, and can complete all Boolean logic operations by simple cyclic traversal, thereby greatly improving the reliability, stability and execution efficiency of interlocking software.
Drawings
The above and other features, properties and advantages of the present invention will become more apparent from the following description of embodiments taken in conjunction with the accompanying drawings in which like reference characters designate like features throughout the drawings, and in which:
FIG. 1 discloses a flow chart of a generic interlock interface tool configuration method according to an embodiment of the present invention;
FIG. 2 discloses a tree data structure diagram according to an embodiment of the present invention;
FIG. 3a is a schematic diagram of a simple AND or OR line of data according to one embodiment of the invention;
FIG. 3b illustrates two data or operations of simple AND OR data according to one embodiment of the present invention;
FIG. 4 discloses a Boolean logic simplified algorithm flow diagram in accordance with one embodiment of the invention;
FIG. 5 discloses a flowchart of an interlocking data format conversion algorithm according to one embodiment of the present invention;
FIG. 6 discloses a flowchart of an interlocking data cycle traversal algorithm according to one embodiment of the invention;
FIG. 7 discloses a functional block diagram of a generic interlock interface tool configuration device in accordance with an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention relates to a railway computer interlocking data generation algorithm in the field of automatic control, in particular to a data generation algorithm for supporting complex unfixed logic operation by computer interlocking data.
The method and the device for configuring the universal interlocking interface tool can be compatible with all complex unfixed external interface circuits, and can be automatically adapted to the corresponding external interface circuits only by carrying out a small amount of data configuration according to circuit logic.
Fig. 1 discloses a flowchart of a general interlocking interface tool configuration method according to an embodiment of the present invention, and as shown in fig. 1, the general interlocking interface tool configuration method provided by the present invention includes the following steps:
s1, decomposing and defining the interlocking interface parameters according to a Boolean logic structure, and performing complete logic operation on the Boolean logic structure corresponding to all the interlocking interface parameters to generate a tree-shaped data structure;
s2, decomposing the generated tree data structure according to a Boolean logic simplification algorithm, and generating and storing the tree data structure as simple AND or data;
and S3, selecting an interlocking interface parameter according to actual requirements, setting a corresponding Boolean logic structure, converting the built Boolean logic graph into interlocking data of the Boolean logic structure, and performing cycle traversal calculation on the interlocking data according to a simple AND or data structure to complete the configuration of the interlocking interface.
Each step of the method is described in detail below.
And S1, decomposing and defining the interlocking interface parameters according to a Boolean logic structure.
Fig. 2 discloses a tree data structure according to an embodiment of the present invention, and as shown in fig. 2, the boolean logic structure according to the present invention includes a basic element, a result element, a logic or gate, and a logic and gate:
the basic elements comprise input condition parameters of an interlocking interface;
the result element comprises output driving command parameters of the interlocking interface;
the input end of the logical OR gate is connected with a plurality of basic elements, and the output end outputs logical OR operation relations among the plurality of basic elements;
the input end of the logic AND gate is connected with a plurality of basic elements, and the output end outputs the logic AND operation relation among the basic elements.
In this embodiment, the definition of the element base class of the boolean logic structure is as follows, and the specific definition is shown in table 1.
class CBoolElmt
{
public:
CBoolElmt*m_ObjInput[2]；
CBoolElmt*m_ObjOutput；
BOOL_ELMT_TYPE eType；
UINT16 nDevID；
......
}
TABLE 1 elemental base classes
In this embodiment, the boolean logic structure type is defined as follows, and the specific definition is shown in table 2.
Table 2 boolean logic structure type
| Sequence number | Name of the name | Meaning of |
| 1 | eBoolEndElmt | Result element |
| 2 | eBoolAtomElmt | Basic element |
| 3 | eBoolAndDoor | AND gate |
| 4 | eBoolOrDoor | OR gate |
| 5 | eBoolLine | Connecting wire |
The basic element structure comprises: basic element type, basic element address, basic element not gate switch, and basic element type device status.
In this embodiment, the basic element structure is defined as follows, and the specific definition is shown in table 3.
TABLE 3 basic element Structure
Basic element types, including: the system comprises annunciators, turnouts, physical sections, logical sections, train routes, shunting routes, guiding routes, protecting routes, scattered collection and function buttons.
In this embodiment, the basic element type atom_elmt is defined as follows, and the specific definition is shown in table 4.
TABLE 4 basic element types
| Sequence number | Name of the name | Meaning of |
| 1 | eATOM_ELMT_TYPE_SIGNAL | Signaling device |
| 2 | eATOM_ELMT_TYPE_SWITCH | Switch |
| 3 | eATOM_ELMT_TYPE_PHYSEC | Physical section |
| 4 | eATOM_ELMT_TYPE_LGISEC | Logic section |
| 5 | eATOM_ELMT_TYPE_TRAINRT | Train route |
| 6 | eATOM_ELMT_TYPE_SHUNTRT | Shunting route |
| 7 | eATOM_ELMT_TYPE_CALONRT | Guide way |
| 8 | eATOM_ELMT_TYPE_OVELPRT | Protective approach |
| 9 | eATOM_ELMT_TYPE_OHTERIN | Scattered collection |
| 10 | eATOM_ELMT_TYPE_FUCBTN | Function button |
When the basic element type is the traffic light type, the corresponding traffic light type equipment states comprise a red light, a double yellow light, a Huang Shanhuang light, a yellow light, a green light, a light guide, a white light, a blue light, a broken light, a double yellow light, a yellow flash, a yellow light, a green light, a green light and a green light.
In this embodiment, the basic element signal type device status is defined as follows, and the specific definition is shown in the following
Table 5.
TABLE 5 basic element annunciator type device status
When the basic element type is a turnout type, the corresponding turnout type equipment state comprises positioning, inversion and quartet.
The basic element switch type equipment state is defined as follows, and the specific definition is shown in table 6.
TABLE 6 basic element switch type device State
| Sequence number | Name of the name | Meaning of |
| 1 | eSWITCH_ELMT_DW | Positioning |
| 2 | eSWITCH_ELMT_FW | Reversed position |
| 3 | eSWITCH_ELMT_SK | Four-way switch |
When the basic element type is the physical section type, the corresponding physical section type equipment states comprise idle, occupied, axle counting fault, right locking and left locking.
In this embodiment, the basic element physical section type device status is defined as follows, and the specific definition is shown in table 7.
TABLE 7 basic element physical segment type device State
| Sequence number | Name of the name | Meaning of |
| 1 | ePHYSEC_ELMT_CLEAR | Idle |
| 2 | ePHYSEC_ELMT_OCCUPIED | Occupancy of |
| 3 | ePHYSEC_ELMT_ARB | Fault of axle counter |
| 5 | ePHYSEC_ELMT_LOCK_right | Locking to the right |
| 6 | ePHYSEC_ELMT_LOCK_left | Left locking |
When the basic element type is a logic section type, the corresponding logic section type equipment states comprise idle, AT occupied, UT occupied, right locking and left locking.
In this embodiment, the basic element logical section type device status is defined as follows, and the specific definition is shown in table 8.
TABLE 8 basic element logical segment type device State
/>
When the basic element type is a train route type, the corresponding train route type equipment state comprises a selecting stage, pre-locking, signal opening, normal closing, fault closing, normal unlocking and manual unlocking.
In this embodiment, the basic element train route type device status is defined as follows, and the specific definition is shown in table 9.
TABLE 9 basic element train route type device status
When the basic element type is a shunting route type, the corresponding shunting route type equipment state comprises a selecting stage, pre-locking, signal opening, normal closing, fault closing, normal unlocking, midway turning-back unlocking and manual unlocking.
In this embodiment, the basic element shunting route type device state is defined as follows, and the specific definition is shown in table 10.
Table 10 basic element shunting route type device State
| Sequence number | Name of the name | Meaning of |
| 1 | eSHUNT_ROUTE_SELECT | Stage of selecting and arranging |
| 2 | eSHUNT_ROUTE_LOCKED | Pre-locking |
| 3 | eSHUNT_ROUTE_SIGOPEN | Signal opening |
| 4 | eSHUNT_ROUTE_SIGCLOSE | Normally closed |
| 5 | eSHUNT_ROUTE_FALTCLOSE | Failure shutdown |
| 6 | eSHUNT_ROUTE_RELEASE | Normal unlocking |
| 7 | eSHUNT_ROUTE_REVERRLS | Midway turning back unlocking |
| 8 | eSHUNT_ROUTE_MANRLS | Manual unlocking |
When the basic element type is the guiding route type, the corresponding guiding route type equipment state comprises a selecting stage, pre-locking, signal opening, normal closing, fault closing and manual unlocking.
In this embodiment, the basic element guide route type device status is defined as follows, and the specific definition is shown in table 11.
Table 11 basic element guide route type device status
| Sequence number | Name of the name | Meaning of |
| 1 | eCALLON_ROUTE_SELECT | Stage of selecting and arranging |
| 2 | eCALLON_ROUTE_LOCKED | Pre-locking |
| 3 | eCALLON_ROUTE_SIGOPEN | Signal opening |
| 4 | eCALLON_ROUTE_SIGCLOSE | Normally closed |
| 5 | eCALLON_ROUTE_FALTCLOSE | Failure shutdown |
| 6 | eCALLON_ROUTE_MANRLS | Manual unlocking |
When the basic element type is a protection route type, the corresponding protection route type equipment state comprises a selecting and arranging stage, pre-locking, normal unlocking and manual unlocking.
In this embodiment, the basic element protection approach type device status is defined as follows, and the specific definition is shown in table 12.
Table 12 basic element protection approach type device status
| Sequence number | Name of the name | Meaning of |
| 1 | eOVERLP_ROUTE_SELECT | Stage of selecting and arranging |
| 2 | eOVERLP_ROUTE_LOCKED | Pre-locking |
| 3 | eOVERLP_ROUTE_RELEASE | Normal unlocking |
| 4 | eOVERLP_ROUTE_MANRLS | Manual unlocking |
When the basic element type is a scattered relay type, the corresponding scattered relay type equipment state comprises scattered suction and scattered dropping.
In this embodiment, the basic element scattered relay type device status is defined as follows, and the specific definition is shown in table 13.
TABLE 13 status of basic element scattered relay type device
| Sequence number | Name of the name | Meaning of |
| 1 | eOTHER_ELMT_STA_UP | Scattered sucking up |
| 2 | eOTHER_ELMT_STA_DOWN | Scattered falling down |
When the basic element type is a function button type, the corresponding function button type equipment state comprises button lifting and button pressing.
In the present embodiment, the basic element function button state type device state is defined as follows, and the specific definition is shown in table 14.
Table 14 basic element function button status type device status
| Sequence number | Name of the name | Meaning of |
| 1 | eFUCBTN_ELMT_STA_UP | Push button lift |
| 2 | eFUCBTN_ELMT_STA_DOWN | Button press |
The result element structure includes: result element type, result element address, and result element type device command.
In this embodiment, the structure of the result element is defined as follows, and the specific definition is shown in table 15.
TABLE 15 results element Table Structure
The result element types comprise a signaler type and a scattered driving type.
In this embodiment, the result element type is defined as follows, and the specific definition is shown in table 16.
TABLE 16 results element type
| Sequence number | Name of the name | Meaning of |
| 1 | eEND_ELMT_TYPE_SIGNAL | Signaling device |
| 9 | eEND_ELMT_TYPE_OHTEROUT | Scattered driving |
When the result element type is the traffic light type, the corresponding traffic light type equipment commands comprise a red light, a double yellow light, a Huang Shanhuang light, a yellow light, a green light, a light guide, a white light, a blue light, a broken light, a double yellow light, a yellow flash, a yellow light, a green light and a guide.
In this embodiment, the result element annunciator type device command is defined as follows, and the specific definition is shown in table 17.
Table 17 result element signaler type device Command
| Sequence number | Name of the name | Meaning of |
| 1 | eSIGNAL_ELMT_CMD_KD_H | Lighting red light |
| 2 | eSIGNAL_ELMT_CMD_KD_UU | Double yellow lamp |
| 3 | eSIGNAL_ELMT_CMD_KD_USU | Lighting Huang Shanhuang |
| 4 | eSIGNAL_ELMT_CMD_KD_1U | Lighting yellow lamp |
| 5 | eSIGNAL_ELMT_CMD_KD_LU | Green yellow lamp |
| 6 | eSIGNAL_ELMT_CMD_KD_L | Lighting green light |
| 7 | eSIGNAL_ELMT_CMD_KD_YB | Lighting guide |
| 8 | eSIGNAL_ELMT_CMD_KD_DB | White lamp for lighting and turning on |
| 9 | eSIGNAL_ELMT_CMD_KD_A | Lighting shunting blue |
| 10 | eSIGNAL_ELMT_CMD_KD_HS | Lighting broken wire |
| 11 | eSIGNAL_ELMT_CMD_MD_H | Double yellow lamp |
| 12 | eSIGNAL_ELMT_CMD_MD_UU | Yellow flash yellow lamp |
| 13 | eSIGNAL_ELMT_CMD_MD_1U | Yellow lamp for extinguishing lamp |
| 14 | eSIGNAL_ELMT_CMD_MD_LU | Green-yellow lamp |
| 15 | eSIGNAL_ELMT_CMD_MD_L | Green lamp for lighting |
| 16 | eSIGNAL_ELMT_CMD_MD_YB | Lamp-extinguishing guide |
When the result element type is the scattered drive type, the corresponding scattered drive type equipment command comprises scattered drive sucking and scattered drive dropping.
In this embodiment, the result element scattered drive type device command is defined as follows, and the specific definition is shown in table 18.
Table 18 results element sporadic drive type device commands
| Sequence number | Name of the name | Meaning of |
| 1 | eOTHER_ELMT_CMD_UP | Scattered driving suction |
| 2 | eOTHER_ELMT_CMD_DOWN | Scattered driving falling |
And S1, performing complete logic operation on the Boolean logic structures corresponding to all the interlocking interface parameters to generate a tree-shaped data structure. As shown in fig. 2, the complete logic operation is performed on the association relationship between the interlocking data of all boolean logic structures, so as to form a tree data structure.
The objects of all the basic elements and the result elements are connected with each other through the internal pointers to form a tree structure data as shown in fig. 2.
And S2, decomposing the generated tree data structure according to a Boolean logic simplification algorithm, and generating and storing the tree data structure as simple AND or data.
FIG. 3a is a schematic diagram of a simple AND or data line according to an embodiment of the present invention, and the tree data structure shown in FIG. 2 is converted into a simple AND or structure shown in FIG. 3a for storage by a Boolean logic reduction algorithm.
Fig. 4 discloses a flowchart of a boolean logic simplification algorithm according to an embodiment of the present invention, as shown in fig. 4, the boolean logic simplification algorithm in step S2 further includes:
searching all tree branch structures of the generated tree data structure according to recursive traversal, and generating tree branch structure data according to the node sequence;
storing tree branch structure data according to a two-dimensional data structure to generate simple AND or data;
wherein each row of data is tree branch structure data;
each tree branch structure data includes at least one base element, at least one logical AND gate, and one result element;
the input end of each logical AND gate corresponds to only one basic element, and the output end of each logical AND gate corresponds to only one basic element or result element.
In the simple AND or data structure, AND operation is carried out among basic elements of each row of data, so that the state of a result element can be obtained;
the element table is defined as follows:
typedef vector < cboolclmt > bonelmtrow; the user stores a line of data for the boolean element.
typedef vector < BoolElmtRow > BoolElmtTable; boolean element table definitions, using this structure, a two-dimensional table can be used to store CBoolElmt objects, one set of data per action.
typedefvector < BOOLEAN_TABLE > BoolTable; performing Boolean operation;
ATOM_ELMT ATOM list [10] = {. This array holds all the basic elements.
The Boolean logic simplification algorithm shown in fig. 4 searches all tree branch structures by recursively traversing tree structure data shown in fig. 2 formed by CBoolELmt objects, and stores the tree branch structures in the rtTable data structure, so that data rtTable in Boolean elmtTable format is obtained through the Boolean logic simplification algorithm.
rtTable is a two-dimensional table, and the state of the result element can be obtained by performing an and operation between the basic elements stored in each individual row. The final state of the result element can be obtained by performing an OR operation between the states of the result elements obtained by all the rows.
The Boolean logic reduction algorithm table is defined as follows, and the specific definition is shown in Table 19.
Table 19 Boolean logic simplified algorithm table
| Sequence number | Name of the name | Meaning of | Remarks |
| 1 | END_ELMT EndElmt | Result element | |
| 2 | ATOM_ELMT AtoElmt[20] | Basic elements of the process and the process |
FIG. 3b is a schematic diagram of a simple AND or data structure of two rows of data or operations, wherein the states of the result elements of all rows of data are OR-ed to obtain the final states of the result elements, as shown in FIG. 3b, according to an embodiment of the present invention.
Thus, the interlocking software can complete complex Boolean logic operation functions by simple cycle traversal.
And S3, selecting an interlocking interface parameter according to actual requirements, setting a corresponding Boolean logic structure, converting the built Boolean logic graph into interlocking data of the Boolean logic structure, and performing cycle traversal calculation on the interlocking data according to a simple AND or data structure to complete the configuration of the interlocking interface.
When new requirements exist and an interlocking interface needs to be configured, a tool bar is utilized to configure according to a Boolean logic structure, a Boolean logic graph is built, attributes of basic elements and result elements are set, a generating button is clicked, the built Boolean logic graph is converted into interlocking data of the Boolean logic structure, and interlocking software reads the interlocking data to perform cycle traversal calculation, so that the configuration of the interlocking interface is completed.
Fig. 5 discloses a flowchart of an interlocking data format conversion algorithm according to an embodiment of the present invention, where the interlocking data format conversion algorithm shown in fig. 5 converts a built BOOLEAN logic graph into interlocking data with a BOOLEAN logic structure, converts a two-dimensional TABLE in rtTable into a binary TABLE with a bolean_table format, and generates data in a boltable format for interlocking, so that the interlocking is convenient for performing data operation.
Fig. 6 is a flowchart of an interlocking data cycle traversal algorithm according to an embodiment of the present invention, where the interlocking data cycle traversal algorithm shown in fig. 6 performs an and operation on each row according to a binary TABLE in a boolaen_table format, then performs an or operation on the result of each row, and finally obtains the BOOLEAN state of the result element, and the interlocking software drives the result element according to the interlocking data cycle traversal algorithm shown in fig. 6.
In this embodiment, the present invention is written in the C language, and may be implemented in other computer languages.
It should be noted that, in the embodiment, the implementation of the interlocking algorithm is based on the computer interlocking of the TECIS (time electric computer interlocking system) platform, but the computer interlocking system of other platforms can also implement the invention.
It should be noted that, in this embodiment, the implementation of the interlocking algorithm is based on the computer interlocking of the CBTC (Communication Based Train Control System, communication-based automatic train control system) system, but the present invention can also be implemented by point-type, FAO (Fully Automatic Operation, full automatic driving system), and large-speed railway interlocking.
It should be noted that the number of arrays in the data definition of the interlock algorithm in this embodiment may not be limited to the length described herein.
While, for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more embodiments, occur in different orders and/or concurrently with other acts from that shown and described herein or not shown and described herein, as would be understood and appreciated by those skilled in the art.
Fig. 7 is a functional block diagram of a generic interlock interface tool configuration device in accordance with an embodiment of the present invention. The universal interlock interface tool configuration device may include an internal communication bus 501, a processor (processor) 502, a Read Only Memory (ROM) 503, a Random Access Memory (RAM) 504, a communication port 505, and a hard disk 507. Internal communication bus 501 may enable data communication between components of the universal interlocking interface tool configuration device. The processor 502 may make the determination and issue the prompt. In some embodiments, the processor 502 may be comprised of one or more processors.
The communication port 505 may enable data transmission and communication between the universal interlock interface tool configuration device and external input/output devices. In some embodiments, the universal interlock interface tool configuration device can send and receive information and data from the network through the communication port 505. In some embodiments, the universal interlock interface tool configuration device may communicate and transfer data in a wired fashion with external input/output devices through input/output 506.
The universal interlock interface tool configuration device may also include various forms of program storage units as well as data storage units such as a hard disk 507, read Only Memory (ROM) 503 and Random Access Memory (RAM) 504, capable of storing various data files for computer processing and/or communication use, as well as possible program instructions for execution by the processor 502. The processor 502 executes these instructions to carry out the main part of the method. The results processed by the processor 502 are transmitted to an external output device through the communication port 505 and displayed on a user interface of the output device.
For example, the implementation process file of the universal interlock tool configuration prediction method may be a computer program, stored in the hard disk 507, and recorded into the processor 502 for execution, so as to implement the method of the present application.
When the implementation process file of the universal interlocking interface tool configuration method is a computer program, the implementation process file can also be stored in a computer readable storage medium as an article of manufacture. For example, computer-readable storage media may include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips), optical disks (e.g., compact Disk (CD), digital Versatile Disk (DVD)), smart cards, and flash memory devices (e.g., electrically erasable programmable read-only memory (EPROM), cards, sticks, key drives). Moreover, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term "machine-readable medium" can include, without being limited to, wireless channels and various other media (and/or storage media) capable of storing, containing, and/or carrying code and/or instructions and/or data.
The invention provides a method and a device for configuring a universal interlocking interface tool, which simplify the parameters of an interlocking interface according to a Boolean logic structure, and can complete all Boolean logic operations by simple cyclic traversal, thereby greatly improving the reliability, stability and execution efficiency of interlocking software.
As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.
Those of skill in the art would understand that information, signals, and data may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a web site, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk (disk) and disc (disk) as used herein include Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks (disk) usually reproduce data magnetically, while discs (disk) reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The embodiments described above are intended to provide those skilled in the art with a full range of modifications and variations to the embodiments described above without departing from the inventive concept thereof, and therefore the scope of the invention is not limited by the embodiments described above, but is to be accorded the broadest scope consistent with the innovative features recited in the claims.
Claims (10)
1. A method for configuring a universal interlock interface tool, comprising the steps of:
s1, decomposing and defining the interlocking interface parameters according to a Boolean logic structure, and performing complete logic operation on the Boolean logic structure corresponding to all the interlocking interface parameters to generate a tree-shaped data structure;
s2, decomposing the generated tree data structure according to a Boolean logic simplification algorithm, and generating and storing the tree data structure as simple AND or data;
step S3, selecting interlocking interface parameters according to actual requirements, setting corresponding Boolean logic structures, converting built Boolean logic graphics into interlocking data of the Boolean logic structures, and performing cycle traversal calculation on the interlocking data according to simple AND or data structures to complete the configuration of the interlocking interfaces;
the Boolean logic structure comprises basic elements, result elements, logic OR gates and logic AND gates:
the basic elements comprise input condition parameters of an interlocking interface;
the result element comprises output driving command parameters of the interlocking interface;
the input end of the logical OR gate is connected with a plurality of basic elements, and the output end outputs logical OR operation results among the basic elements;
and the input end of the logic AND gate is connected with a plurality of basic elements, and the output end outputs a logic AND operation result among the basic elements.
2. The universal interlock interface tool configuration method according to claim 1, wherein the boolean logic reduction algorithm in step S2 further comprises:
searching all tree branch structures of the generated tree data structure according to recursive traversal, and generating tree branch structure data according to the node sequence;
storing tree branch structure data according to a two-dimensional data structure to generate simple AND or data;
wherein each row of data is tree branch structure data;
each tree branch structure data includes at least one base element, at least one logical AND gate, and one result element;
the input end of each logical AND gate corresponds to only one basic element, and the output end of each logical AND gate corresponds to only one basic element or result element.
3. The universal interlock interface tool configuration method of claim 1, wherein the base elements comprise:
basic element type, basic element address, basic element not gate switch, and basic element type device status.
4. A universal interlock interface tool configuration method according to claim 3, wherein said basic element types include:
the system comprises annunciators, turnouts, physical sections, logical sections, train routes, shunting routes, guiding routes, protecting routes, scattered collection and function buttons.
5. The universal interlock interface tool configuration method of claim 3, wherein said base element types include a annunciator type, a corresponding annunciator type device status, the device comprises a red light, a double yellow light, a Huang Shanhuang light, a yellow light, a green light, a light guide, a white light, a blue light, a broken wire, a double yellow light, a yellow flash light, a yellow light, a green light and a guide;
the basic element types comprise turnout types, and the corresponding turnout type equipment states comprise positioning, inversion and quartet;
the basic element types comprise physical section types, and the corresponding physical section type equipment states comprise idle, occupied, axle counting fault, right locking and left locking;
the basic element types comprise logic section types, and the corresponding logic section type equipment states comprise idle, AT occupied, UT occupied, right locking and left locking;
the basic element types comprise train route types and corresponding train route type equipment states, wherein the train route type equipment states comprise a selecting stage, pre-locking, signal opening, normal closing, fault closing, normal unlocking and manual unlocking;
the basic element types comprise shunting route types and corresponding shunting route type equipment states, wherein the shunting route type equipment states comprise a selecting stage, pre-locking, signal opening, normal closing, fault closing, normal unlocking, midway turning unlocking and manual unlocking;
the basic element types comprise guide route types and corresponding guide route type equipment states, wherein the guide route type equipment states comprise a selecting stage, pre-locking, signal opening, normal closing, fault closing and manual unlocking;
the basic element types comprise protection route types and corresponding protection route type equipment states, wherein the protection route type equipment states comprise a selecting stage, pre-locking, normal unlocking and manual unlocking;
the basic element types comprise scattered relay types, and the corresponding scattered relay type equipment states comprise scattered suction and scattered dropping;
the basic element types comprise function button types, and the corresponding function button type equipment states comprise button lifting and button pressing.
6. The universal interlock interface tool configuration method of claim 1, wherein the result element comprises:
result element type, result element address, and result element type device command.
7. The universal interlock interface tool configuration method of claim 6, wherein the result element type comprises a annunciator type, a corresponding annunciator type device command, the device comprises a red light, a double yellow light, a Huang Shanhuang light, a yellow light, a green light, a light guide, a white light, a blue light, a broken wire, a double yellow light, a yellow flash light, a yellow light, a green light and a guide;
the result element types comprise scattered drive types, and the corresponding scattered drive type equipment commands comprise scattered drive sucking-up and scattered drive dropping.
8. The method according to claim 2, wherein in step S3, the loop-through calculation is performed on the interlock data according to a simple and or data structure, and the method further comprises:
selecting a simple AND or data structure corresponding to the interlocking data of the Boolean logic structure;
performing AND operation between basic elements of each row of data in the simple AND or data structure to obtain the state of a result element;
and performing OR operation between the states of the result elements of all the row data in the simple AND OR data structure to obtain the final state of the result elements.
9. A universal interlock interface tool configuration device, comprising:
a memory for storing instructions executable by the processor;
a processor for executing the instructions to implement the method of any one of claims 1-8.
10. A computer storage medium having stored thereon computer instructions, which when executed by a processor, perform the method of any of claims 1-8.
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