CN109760720B - Method and device for automatically generating interface code bit table based on signal plane layout diagram - Google Patents
Method and device for automatically generating interface code bit table based on signal plane layout diagram Download PDFInfo
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Abstract
The embodiment of the invention provides a method and a device for automatically generating an interface code bit table based on a signal plane layout, wherein the method comprises the following steps: reading all primitive information in the signal plane layout drawing and reading all parameters in the line configuration parameters; extracting the circuit logic topology according to the read primitive information and parameters; carrying out data numbering and equipment numbering on all signal equipment in the extracted circuit logic topology, calling a drawing updating interface, and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing; and generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology. The interface code bit table can be automatically generated based on the signal plane layout, the automation of interface code bit data is improved, the working efficiency is improved, the repetitive work is reduced, the reliability and the safety of the interface code bit data are ensured, and powerful guarantee is provided for the safety of rail transit.
Description
Technical Field
The embodiment of the invention relates to the technical field of rail transit, in particular to a method and a device for automatically generating an interface code bit table based on a signal plane layout.
Background
Along with the rapid development of the rail transit industry, market demands are diversified, so that the types of signal system products are increased, and typical signal products are divided into 4 types: traditional CBTC (communication-based train automatic control system) products, interconnection CBTC products, FAO (full automatic driving system) products, FAO interconnection products; code bit data are different among interfaces among various types of products, and the code bit quantity type comprises: CI _ ATS (computer interlocking _) interface code bit table, CI _ ZC (computer interlocking zone controller) interface code bit table, and CI _ LEU (computer interlocking _ ground electronic Unit) interface code bit table. The code bits data need to be manufactured according to a signal plane layout diagram and an interface file, the number of input files is large, the manufacture is inconvenient, and the manual manufacture error rate of the interface code data is high, and the efficiency is low.
Because the transmission information among different systems is continuously increased, the workload of the configuration data of the code bits of the interface is continuously increased, the workload of the electronic map tends to be pursued, a corresponding data generation tool is not developed, the newly added data content is completely input by manpower, and the quality cannot be ensured. The labor cost increases year by year. Moreover, along with the updating and changing of engineering input, data manufacturing often needs to be reworked, so that the construction period is more urgent, and therefore, how to automatically generate the interface code bit table can quickly process data, reduce repetitive work and improve the reliability and safety of the data becomes a technical problem to be solved at present.
Disclosure of Invention
To solve the problems in the prior art, embodiments of the present invention provide a method and an apparatus for automatically generating an interface code bit table based on a signal plane layout.
The embodiment of the invention provides a method for automatically generating an interface code bit table based on a signal plane layout, which comprises the following steps:
reading all primitive information in the signal plane layout drawing and reading all parameters in the line configuration parameters;
extracting the circuit logic topology according to the read primitive information and parameters;
carrying out data numbering and equipment numbering on all signal equipment in the extracted circuit logic topology, calling a drawing updating interface, and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing;
and generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology.
The embodiment of the invention provides a device for automatically generating an interface code bit table based on a signal plane layout, which comprises:
the reading module is used for reading all the graphic element information in the signal plane layout drawing and reading all the parameters in the line configuration parameters;
the extraction module is used for extracting the circuit logic topology according to the read primitive information and the read parameters;
the backfill module is used for carrying out data numbering and equipment numbering on all signal equipment in the extracted line logic topology, calling a drawing updating interface and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing;
and the first generation module is used for generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology.
An embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the steps of the method are implemented as described above.
The method and the device for automatically generating the interface code bit table based on the signal plane layout provided by the embodiment of the invention can automatically generate the interface code bit table based on the signal plane layout, improve the data automation of the interface code bit data, improve the working efficiency, reduce the repeated work and ensure the reliability and the safety of the interface code bit data by reading all the primitive information in the signal plane layout and all the parameters in the line configuration parameters, extracting the line logic topology according to the read primitive information and the read parameters, numbering all the signal devices in the extracted line logic topology by data and device, calling a drawing to update an interface, backfilling the data numbers and the device numbers to the signal plane layout and generating the interface code bit table according to the route input table in the signal plane layout and the structure of the extracted line logic topology, powerful guarantee is provided for the safety of track traffic.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart illustrating a method for automatically generating an interface code bit table based on a signal plane layout according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a specific flow of logic topology extraction according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a specific generation flow of a code bit table of a ZC-CI interface according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a specific generation flow of a CI-LEU interface code bit table according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a specific generation flow of an LEU-CI interface code bit table according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a specific process of generating interface code bit data according to the generated interface code bit table and the drawing device information in the signal plane layout diagram according to the embodiment of the present invention;
fig. 7 is a schematic structural diagram of an apparatus for automatically generating an interface code bit table based on a signal plane layout according to an embodiment of the present invention;
fig. 8 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic flowchart illustrating a method for automatically generating an interface code bit table based on a signal plane layout diagram according to an embodiment of the present invention, where as shown in fig. 1, the method for automatically generating an interface code bit table based on a signal plane layout diagram according to the embodiment includes:
s1, reading all primitive information in the signal floor plan, and reading all parameters in the line configuration parameters.
In a specific application, the read primitive information and parameters may be stored in a database.
And S2, extracting the circuit logic topology according to the read primitive information and parameters.
And S3, numbering all signal devices in the extracted circuit logic topology, calling a drawing updating interface, and backfilling the data numbers and the device numbers to the signal plane layout drawing.
And S4, generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology.
The method for automatically generating the interface code bit table based on the signal plane layout provided by the embodiment of the invention comprises the steps of reading all primitive information in the signal plane layout and all parameters in line configuration parameters, extracting the line logic topology according to the read primitive information and parameters, carrying out data numbering and equipment numbering on all signal equipment in the extracted line logic topology, calling a drawing to update an interface, backfilling the data numbering and the equipment numbering onto the signal plane layout, and generating the interface code bit table according to an incoming route input table and the extracted structure of the line logic topology in the signal plane layout, so that the automatic generation of the interface code bit table based on the signal plane layout can be realized, the automation of the data of the interface code bit is improved, the working efficiency is improved, the repeated work is reduced, and the reliability and the safety of the interface code bit data are ensured, powerful guarantee is provided for the safety of track traffic.
In a specific application, in order to ensure that the signal device element can smoothly generate the interface code bit data, the signal plane layout diagram described in this embodiment may have the following requirements:
firstly, wire: the layer is a P-line; in the process of drawing the line, one physical line basically requires only one straight line or a multi-endpoint broken line, so that the condition that one physical line is formed by connecting a plurality of line segments or a plurality of straight lines is avoided; when the side line is added at the turnout, the side line is required to be as close to the turnout as possible or even to be overlapped with the insertion point of the turnout.
II, reference block: all the equipment elements are defined as blocks and have the attributes and data items necessary for report generation; block insertion points are required to be on a line or deviate within a certain error, otherwise, the data extraction of line equipment is influenced; the end points of the line can only be a car bumper, a shaft counter and a turnout.
Thirdly, direction mark block: the line where the insertion point is located is represented as a positive line; the blocks must be drawn in pairs; there are at most two pairs of main lines in one drawing.
Fourthly, the kilometer scale of the equipment: the format of the kilometer post is the same as the format of the corresponding kilometer post system in the kilometer post conversion; the kilometer post conversion should include all the kilometer post systems in the drawing; the size of the kilometer post belonging to the same kilometer post system is extended in a single direction; the size of each kilometer post should be consistent with the position of its insertion point.
Fifthly, inserting points of the annunciator and the associated axle counting: the semaphores having the same number of its associated axle reading milestones require the axle counter insertion point to be offset to one side of the semaphore's direction of action.
Sixthly, a boundary line: when the dividing line is added, the dividing line is required to be close to one end of the axle counting or the corresponding axle counting position; the corresponding names of the left side and the right side of the boundary used for dividing are consistent.
Seventhly, the method comprises the following steps: line of vehicle section crossing switch: the line that crosses the switch needs to extend one section in the orientation again to avoid there being three lines in switch department.
Eighthly, the requirement of a route input table is as follows: the contents of the turnout columns of the route input table fill all turnouts which pass through the route.
Nine: other requirements are as follows: in principle, text elements are not processed in the process of extracting and processing the line data, text boxes with properties marked separately are avoided as much as possible, and for example, blocks which have to have text elements and need to be processed and can be separately defined into specific types are required.
In a specific application, the interface code bit generation principle of this embodiment may include:
firstly, writing code bits in sequence:
1. turnout:
and compiling sequentially according to the turnout numbers from small to large. Double-acting switch code positions are written with small numbers and then with large numbers. Such as 1-4, should not be written as 4-1. The number of the turnout is subject to the first number, such as turnouts No. 1-4 and No. 2-3, and 1-4 information is written first and then 2-3 information is written when the turnout is arranged in sequence. For switches, the state that interlocks can provide to a ZC (zone controller) subsystem is classified as switch position and switch lock, and the switch position state provided is classified as "locate" or "reverse".
2. Signal machine type:
the code bit sequence is a protection annunciator, an outbound annunciator, an interval division annunciator and a blocking annunciator, and if a reverse annunciator exists, the code bit sequence is placed at the last. Sequence of outbound and local signals: writing from the kilometer sign to the kilometer sign according to the line. The signal machines of the same type are arranged from small to large according to the serial numbers, such as F1, F2, F3, …, Z1 and Z2 …. And if the number type of the annunciator is S01004, writing the uplink, and generating the downlink according to the kilometer list in a sequencing manner. For the following two states in the semaphore: listing state code bits of the over-voltage signal machine; command code position is forced to the semaphore, when generating above-mentioned two code positions, needs judge according to semaphore position information whether need generate above-mentioned two code positions, for example: the end red light blocking signal and the reverse blocking signal (without reverse CBTC) do not need code bit information; and if the code bit information is not generated, setting the code bit information as an invalid value.
3. Segment class (including axle counting segment, logical segment):
and compiling from small to large according to the section number. And starting to write the turnout section after the turnout section is written. The turnout section is first small and then large, for example, 1-3DG should not be written as 3-1 DG. The sector numbers are based on a first number, such as 1-4DG in order prior to 2-3 DG.
The axle counting section information includes: direction, occupancy, locking information, and count axis field ARB (always Report blocking) information.
Direction of the axle counting section: positioning the running direction of the train according to the position of the section by taking the axle counting section as a unit;
the shaft counting section occupies: the CI (computer interlock) sends all the shaft counting sections in the jurisdiction area of the CI to the ZC to be free and occupied state information.
Locking of the counting shaft section: and the CI sends locking state information of all the axle counting sections in the jurisdiction area of the CI to the ZC.
For a non-automatic vehicle section or a parking lot, when the positive line generates the code bits of the axle counting section, the code bits of the axle counting section also need to comprise a first section at the inner side of an entry section or an entry signal machine, and the ARB code bits are not set in the section. Therefore, when generating the axle counting section information, whether to generate the ARB code bit needs to be judged according to the position.
A logic section: and judging whether the logic section corresponding to the turnout section is processed in a two-section type division mode or a one-section type mode according to the property of the project.
4. Emergency exit, emergency shutdown button, unmanned button of turning back:
and compiling from small to large according to the track section number. The code bits of the safety door and the emergency stop button take PSD as a unit, and when two PSDs exist in one physical section, U (uplink) or D (downlink) is used. If the safety door has the condition of corresponding to two stations, two code bits need to be generated when generating the safety door state code bit and respectively correspond to different stations.
5. A protection section:
the protection section is named by the terminal signal machine of the route to which the protection section belongs, and the arrangement sequence is consistent with the sequencing rule of the signal machine. The protection section only contains the axle counting section of the turnout, because when the protection section of the route or the automatic signal contains the turnout, the movement authorization range is different due to different positioning and reversing positions of the turnout. Therefore, when the protection zone state is generated, it is necessary to determine whether the protection zone includes a switch.
6. Routing:
the straight-through, then the return, and finally the auto-signal (if any) are written. For each type of route, the name of the starting end signal machine is used as the sequencing basis. The route sorting method is the same as the signaler.
Secondly, inputting:
1. segment class: and generating related code bits based on the imported physical zone logical zone.
2. Route type: and generating the code bit related to the route based on the route input table.
3. Protection segment class: support is based on the protection zone table after import, only the fork zone is reserved.
Thirdly, generating a file format: and each concentration area has a sheet and each type of code bit has an excel. Each class of code bits for each concentration zone is numbered from 1.
And fourthly, code data format: the number of code bits in the data must correspond exactly to the number of code bits in the code bit table.
And fifthly, other requirements: the section lock and section run direction code bits may be generated in units of logical sections. The code bit rule is the same as the physical section; the instability direction code bits may be generated. Taking a section with the stability stopping information as a unit, and the code bit content is 'on the uplink/not on the uplink' or 'on the downlink/not on the downlink'; the code bits can be made into configurable items, and the selection of the type of the code bits needing to be generated is realized through functions such as a pull-down selection menu and the like.
Further, on the basis of the foregoing embodiment, the step S2 may include:
performing line fitting according to all the primitive information of the read signal plane layout drawing and a set rule, searching all the equipment from a database through a fitting line list, combing the equipment on each fitting line according to the rule, and generating an on-line equipment list;
and sequentially analyzing the logic connection relations among the lines, the equipment and the equipment based on the fitting line list and the on-line equipment list to form a line logic topological structure.
Further, the logic connection relationships among the lines, between the lines and between the devices are sequentially analyzed based on the fitted line list and the on-line device list to form a line logic topology structure, and a specific process can refer to fig. 2, which can be understood as: reading line and device data (including both on-line devices and off-line devices); converting all equipment kilometer posts into uniform kilometer posts; reading the fitting line and the equipment data corresponding to the fitting line, namely constructing the association relationship between the line and the equipment; constructing an incidence relation between the devices, namely an adjacent relation of the devices; processing the connection direction of the equipment according to the principle, such as the existence of turnouts between the equipment, the connection direction and the like; acquiring a line uplink and downlink identification block, and distinguishing line uplink and downlink attributes; and completing modeling of the network model.
Further, on the basis of the above embodiment, after the step S2, the method may further include:
and performing logic verification on the extracted line logic topology according to a preset drawing inspection rule, and outputting a logic verification result in a log form (according to a specified format).
Specifically, the content for performing the logical check may include a kilometer post arrangement order of the devices, a minimum distance between the devices, and whether device data numbers overlap.
Further, on the basis of the above embodiment, after the step S4, the method may further include:
and generating interface code bit data according to the generated interface code bit data and the drawing equipment information in the signal plane layout diagram.
In a specific application, the step S4 may automatically generate the ZC-CI and CI-LEU interface code bit tables according to the signal plane layout diagram and the route input table, and may generate the interface code bit data based on the generated ZC-CI and CI-LEU interface code bit tables in a subsequent step. Specifically, a ZC-CI code bit table may be generated in units of concentrated areas, and a specific generation flow may refer to fig. 3; the CI-LEU interface code bit table and the LEU-CI interface code bit table may be generated in units of concentrated regions, a specific generation flow of the CI-LEU interface code bit table may refer to fig. 4, and a specific generation flow of the LEU-CI interface code bit table may refer to fig. 5. Accordingly, referring to fig. 6, a specific flow of generating interface code bit data according to the generated interface code bit table and the drawing device information in the signal plane layout diagram may be performed.
The method for automatically generating the interface code bit table based on the signal plane layout diagram can automatically generate the interface code bit table based on the signal plane layout diagram, improves the automation of interface code bit data, improves the working efficiency, reduces the repeated work, can adapt to different data structures, ensures the reliability and the safety of the interface code bit data, and provides powerful guarantee for the safety of rail transit.
Fig. 7 is a schematic structural diagram of an apparatus for automatically generating an interface code bit table based on a signal plane layout diagram according to an embodiment of the present invention, and as shown in fig. 7, the apparatus for automatically generating an interface code bit table based on a signal plane layout diagram according to the embodiment includes: a reading module 71, an extraction module 72, a backfill module 73, and a first generation module 74; wherein:
the reading module 71 is configured to read all primitive information in the signal plane layout diagram and all parameters in the line configuration parameters;
the extraction module 72 is configured to extract a circuit logic topology according to the read primitive information and parameters;
the backfill module 73 is configured to perform data numbering and device numbering on all signal devices in the extracted line logic topology, call a drawing update interface, and backfill the data numbering and the device numbering onto the signal plane layout drawing;
the first generating module 74 is configured to generate an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the line logic topology.
Specifically, the reading module 71 reads all primitive information in the signal plane layout diagram, and reads all parameters in the line configuration parameters; the extraction module 72 extracts the circuit logic topology according to the read primitive information and parameters; the backfill module 73 performs data numbering and equipment numbering on all signal equipment in the extracted line logic topology, calls a drawing updating interface, and backfills the data numbering and the equipment numbering onto a signal plane layout drawing; the first generating module 74 generates an interface code bit table according to the route input table in the signal floor plan and the extracted structure of the logical topology of the line.
The device for automatically generating the interface code bit table based on the signal plane layout diagram can automatically generate the interface code bit table based on the signal plane layout diagram, improves the automation of interface code bit data, improves the working efficiency, reduces the repeated work, ensures the reliability and the safety of the interface code bit data, and provides powerful guarantee for the safety of rail transit.
In a specific application, to ensure that the signal device element can smoothly generate the interface code bit data, the requirements of the signal plane layout diagram and the interface code bit generation principle described in this embodiment may refer to the description in the foregoing method embodiment, and are not described herein again.
Further, on the basis of the above embodiment, the extraction module 72 may be specifically used for
Performing line fitting according to all the primitive information of the read signal plane layout drawing and a set rule, searching all the equipment from a database through a fitting line list, combing the equipment on each fitting line according to the rule, and generating an on-line equipment list;
and sequentially analyzing the logic connection relations among the lines, the equipment and the equipment based on the fitting line list and the on-line equipment list to form a line logic topological structure.
Based on the fitted line list and the on-line device list, the logic connection relationships among the lines, between the lines and the devices and between the devices are sequentially analyzed to form a line logic topology structure, and a specific process can refer to fig. 2, which can be understood as follows: reading line and device data (including both on-line devices and off-line devices); converting all equipment kilometer posts into uniform kilometer posts; reading the fitting line and the equipment data corresponding to the fitting line, namely constructing the association relationship between the line and the equipment; constructing an incidence relation between the devices, namely an adjacent relation of the devices; processing the connection direction of the equipment according to the principle, such as the existence of turnouts between the equipment, the connection direction and the like; acquiring a line uplink and downlink identification block, and distinguishing line uplink and downlink attributes; and completing modeling of the network model.
Further, on the basis of the above embodiment, the apparatus of this embodiment may further include:
and the verification module is used for performing logic verification on the extracted line logic topology according to a preset drawing inspection rule and outputting a logic verification result in a log form.
Specifically, the content for performing the logical check may include a kilometer post arrangement order of the devices, a minimum distance between the devices, and whether device data numbers overlap.
Further, on the basis of the above embodiment, the apparatus of this embodiment may further include:
and the second generation module is used for generating the interface code bit data according to the generated interface code bit table and the drawing equipment information in the signal plane layout diagram.
In a specific application, in step S4, the ZC-CI and CI-LEU interface code bit tables may be automatically generated according to the signal plane layout diagram and the route input table, and interface code bit data may be generated based on the generated ZC-CI and CI-LEU interface code bit tables in the following.
The device for automatically generating the interface code bit table based on the signal plane layout diagram can automatically generate the interface code bit table based on the signal plane layout diagram, improves the automation of interface code bit data, improves the working efficiency, reduces the repeated work, can adapt to different data structures, ensures the reliability and the safety of the interface code bit data, and provides powerful guarantee for the safety of rail transit.
The apparatus for automatically generating an interface code bit table based on a signal plane layout diagram according to the embodiments of the present invention may be used to implement the technical solution of the foregoing method embodiments, and its implementation principle and technical effect are similar, which are not described herein again.
Fig. 8 shows a schematic physical structure diagram of an electronic device according to an embodiment of the present invention, as shown in fig. 8, the electronic device may include a memory 802, a processor 801, and a computer program stored in the memory 802 and executable on the processor 801, where the processor 801 implements the steps of the method when executing the program, for example, the method includes: reading all primitive information in the signal plane layout drawing and reading all parameters in the line configuration parameters; extracting the circuit logic topology according to the read primitive information and parameters; carrying out data numbering and equipment numbering on all signal equipment in the extracted circuit logic topology, calling a drawing updating interface, and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing; and generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology.
An embodiment of the present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the above method, for example, including: reading all primitive information in the signal plane layout drawing and reading all parameters in the line configuration parameters; extracting the circuit logic topology according to the read primitive information and parameters; carrying out data numbering and equipment numbering on all signal equipment in the extracted circuit logic topology, calling a drawing updating interface, and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing; and generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. A method for automatically generating an interface code bit table based on a signal floor plan, comprising:
reading all primitive information in the signal plane layout drawing and reading all parameters in the line configuration parameters;
extracting the circuit logic topology according to the read primitive information and parameters;
carrying out data numbering and equipment numbering on all signal equipment in the extracted circuit logic topology, calling a drawing updating interface, and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing;
generating an interface code bit table according to a route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology;
the extracting of the line logic topology according to the read primitive information and parameters includes:
performing line fitting according to all the primitive information of the read signal plane layout drawing and a set rule, retrieving all signal devices from a database through a fitting line list, combing the signal devices on each fitting line according to the rule, and generating an on-line device list;
based on the fitting line list and the on-line equipment list, sequentially analyzing the logic connection relations among lines, between lines and signal equipment and between signal equipment to form a line logic topological structure;
after generating the interface code bit table according to the route input table in the signal floor plan and the extracted structure of the logical topology of the route, the method further comprises:
and generating interface code bit data according to the generated interface code bit data and the drawing equipment information in the signal plane layout diagram.
2. The method of claim 1, wherein after the extracting of the line logic topology according to the read primitive information and parameters, the method further comprises:
and performing logic verification on the extracted line logic topology according to a preset drawing checking rule, and outputting a logic verification result in a log form.
3. An apparatus for automatically generating an interface code bit table based on a signal floor plan, comprising:
the reading module is used for reading all the graphic element information in the signal plane layout drawing and reading all the parameters in the line configuration parameters;
the extraction module is used for extracting the circuit logic topology according to the read primitive information and the read parameters;
the backfill module is used for carrying out data numbering and equipment numbering on all signal equipment in the extracted line logic topology, calling a drawing updating interface and backfilling the data numbering and the equipment numbering onto a signal plane layout drawing;
the first generation module is used for generating an interface code bit table according to the route input table in the signal plane layout diagram and the extracted structure of the circuit logic topology;
the extraction module is particularly used for
Performing line fitting according to all the primitive information of the read signal plane layout drawing and a set rule, retrieving all signal devices from a database through a fitting line list, combing the signal devices on each fitting line according to the rule, and generating an on-line device list;
based on the fitting line list and the on-line equipment list, sequentially analyzing the logic connection relations among lines, between lines and signal equipment and between signal equipment to form a line logic topological structure;
and the second generation module is used for generating the interface code bit data according to the generated interface code bit table and the drawing equipment information in the signal plane layout diagram.
4. The apparatus of claim 3, further comprising:
and the verification module is used for performing logic verification on the extracted line logic topology according to a preset drawing inspection rule and outputting a logic verification result in a log form.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to claim 1 or 2 are implemented when the processor executes the program.
6. A non-transitory computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to claim 1 or 2.
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