CN114296896A

CN114296896A - Method, device, computer storage medium and terminal for realizing command scheduling

Info

Publication number: CN114296896A
Application number: CN202111613708.0A
Authority: CN
Inventors: 卓越; 孙超; 张宾
Original assignee: Hefei Datang Storage Technology Co ltd
Current assignee: Hefei Datang Storage Technology Co ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-04-08

Abstract

Disclosed herein are a method, an apparatus, a computer storage medium and a terminal for implementing command scheduling, including: determining whether a first position for inserting a first command exists in a command queue when a Dynamic Random Access Memory (DRAM) receives the first command; when a first location exists, determining whether the first location passes a consistency conflict check; inserting a first command into a first location that passes a consistency conflict check; wherein the first command comprises: a read command or a write command. The embodiment of the invention carries out insertion processing after the consistency conflict check on the newly received first command under the condition of not carrying out read-write grouping on the command queue, thereby improving the read-write performance of a System On Chip (SOC).

Description

Method, device, computer storage medium and terminal for realizing command scheduling

Technical Field

The present disclosure relates to, but not limited to, system-on-a-chip technologies, and in particular, to a method, an apparatus, a computer storage medium, and a terminal for implementing command scheduling.

Background

With the scale of a System On Chip (SOC) becoming larger and larger, modules such as a Central Processing Unit (CPU), a Data Processing Unit (DPU) and the like integrated inside the SOC become more and more; the efficiency of the system to perform the DRAM caching of each module will directly impact the overall performance of the SOC.

A Dynamic Random Access Memory (DRAM) controller is a basic component for analyzing and processing SOC bus commands, and the read-write commands are mainly scheduled according to read-write classification or queue rearrangement technology; the method comprises the following steps of reading and writing classification, fixed rule and queue scheduling strategy of strong coupling logic in the related technology; the complexity of the current scheduling strategy is higher and higher, and the problems of low flexibility, tight logic coupling, poor compatibility and the like exist; is a big problem in the design of the current DRAM controller.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the invention provides a method and a device for realizing command scheduling, a computer storage medium and a terminal, which can improve the data read-write performance of a system on a chip.

The embodiment of the invention provides a method for realizing command scheduling, which comprises the following steps:

when a Dynamic Random Access Memory (DRAM) receives a new first command, determining whether the DRAM in a command queue receives the first command or not, and determining whether a first position for inserting the first command exists in the command queue or not;

when a first location exists, determining whether the first location passes a consistency conflict check;

inserting a first command into a first location that passes a consistency conflict check;

wherein the first command comprises: a read command or a write command.

On the other hand, an embodiment of the present invention further provides a computer storage medium, where a computer program is stored in the computer storage medium, and when the computer program is executed by a processor, the method for implementing command scheduling is implemented.

In another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory having a computer program stored therein; wherein the content of the first and second substances,

the processor is configured to execute the computer program in the memory;

the computer program, when executed by the processor, implements a method of implementing command scheduling as described above.

In another aspect, an embodiment of the present invention further provides a device for implementing command scheduling, where the device includes: a position determining unit, a conflict checking unit and an insertion processing unit; wherein the content of the first and second substances,

the position determination unit is configured to: when a first command is received, determining whether a first position for inserting the first command exists in a command queue;

the conflict checking unit is configured to: when a first location exists, determining whether the first location passes a consistency conflict check;

the insertion processing unit is configured to: inserting a first command into a first location that passes a consistency conflict check;

wherein the first command comprises: a read command or a write command.

The technical scheme of the application includes: determining whether a first position for inserting a first command exists in a command queue when a Dynamic Random Access Memory (DRAM) receives the first command; when a first location exists, determining whether the first location passes a consistency conflict check; inserting a first command into a first location that passes a consistency conflict check; wherein the first command comprises: a read command or a write command. The embodiment of the invention carries out insertion processing after the consistency conflict check on the newly received first command under the condition of not carrying out read-write grouping on the command queue, thereby improving the read-write performance of a System On Chip (SOC).

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a flowchart of a method for implementing command scheduling according to an embodiment of the present invention;

FIG. 2 is a schematic view of a first position in accordance with an embodiment of the present invention;

FIG. 3 is a schematic view of a first position in accordance with another embodiment of the present invention;

FIG. 4 is a schematic view of a first position in accordance with yet another embodiment of the present invention;

FIG. 5 is a diagram illustrating the insertion of a fourth command according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating the insertion of a fourth command according to another embodiment of the present invention;

FIG. 7 is a diagram illustrating a data cache according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating alarm processing according to an embodiment of the present invention;

fig. 9 is a block diagram of an apparatus for implementing command scheduling according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Fig. 1 is a flowchart of a method for implementing command scheduling according to an embodiment of the present invention, as shown in fig. 1, including:

step 101, when a Dynamic Random Access Memory (DRAM) receives a first command, determining whether a first position for inserting the first command exists in a command queue;

in an illustrative example, the first command in the embodiment of the present invention includes a newly received command.

In one illustrative example, determining whether a first location for inserting a first command exists in a command queue comprises:

it is determined whether a first position for inserting the first command exists in the command queue in order from the tail to the head of the command queue.

Step 102, when the first position exists, determining whether the first position passes consistency conflict check;

103, inserting a first command into a first position which passes consistency conflict check;

wherein the first command comprises: a read command or a write command.

It should be noted that, in the embodiment of the present invention, the read command and the write command in the command queue are processed serially, so that only one first command is processed at a time of command scheduling.

The embodiment of the invention carries out insertion processing after the consistency conflict check on the newly received first command under the condition of not carrying out read-write grouping on the command queue, thereby improving the read-write performance of a System On Chip (SOC).

determining a position after a command conforming to a Page Hit as a first position when the command conforming to the Page Hit (Page Hit, accessing the same Bank or Row) exists in the command queue;

when two commands with group Conflict (Bank Conflict) exist in the command queue, determining the middle position of the two commands with group Conflict as a first position;

it should be noted that two fourth commands with group conflicts should be adjacent commands, and only adjacent commands may have group conflicts.

When two adjacent commands with the same operation type exist in the command queue, determining the middle position of the two adjacent commands with the same operation type as a first position;

wherein the operation types include: a read operation and a write operation.

The difference in determining the first position is briefly explained below by way of example; FIG. 2 is a diagram illustrating a first position of the present invention, as shown in FIG. 2, wherein WR _ Bx _ Rx _ Cx represents a write operation, Bx represents xBank, Rx represents the x-th row, and Cx represents the x-th column, and the command represents writing the x-th row and the x-th column of xBank; RD in RD _ Bx _ Rx _ Cx represents reading, and the command represents reading x rows and x columns of an xbank; the

reference numerals

1, 2 and 3 in fig. 2 respectively indicate the determined three first positions where the command conforming to Page Hit exists; the first position of the identifier 1 is close to the head of the command queue, and when the first command insertion processing is carried out, the priority of the first position of the identifier 1 is greater than that of the first position of the identifier 2; the priority of the first position of the identifier 2 is greater than that of the first position of the identifier 3; when consistency conflict check is performed, the embodiment of the present invention performs judgment processing one by one according to the order of the priority from high to low.

FIG. 3 is a schematic diagram of a first position according to another embodiment of the present invention, as shown in FIG. 3, where the

symbols

1, 2 and 3 respectively represent the first position when there are three two commands with group conflicts; the mark 1 is close to the head of the command queue, and when the first command insertion processing is carried out, the priority of the first position of the mark 1 is greater than that of the first position of the mark 2; the priority of the first position of the identifier 2 is greater than that of the first position of the identifier 3; when consistency conflict check is performed, the embodiment of the present invention performs judgment processing one by one according to the order of the priority from high to low.

FIG. 4 is a schematic diagram of a first position according to yet another embodiment of the present invention, as shown in FIG. 4, where the

symbols

1, 2 and 3 respectively represent the first positions when there are two adjacent commands with the same operation type; the mark 1 is close to the head of the command queue, and when the first command insertion processing is carried out, the priority of the first position of the mark 1 is greater than that of the first position of the mark 2; the priority of the first position of the identifier 2 is greater than that of the first position of the identifier 3; when consistency conflict check is performed, the embodiment of the present invention performs judgment processing one by one according to the order of the priority from high to low.

In an exemplary example, the embodiment of the present invention may determine the first position only according to the judgment of whether there is a command conforming to a page hit; in an exemplary example, embodiments of the present invention may determine the first location based only on a determination of whether there are two commands with a group conflict; in an exemplary example, the embodiment of the present invention may determine the first position according to a judgment whether there are two commands whose operation types are consistent and adjacent in order. In one illustrative example, embodiments of the invention may be derived from: selecting two of the judgment of whether a command meeting page hit exists, whether two commands with group conflict exist, and whether two adjacent commands with consistent operation types exist, according to the following steps: whether a command meeting page hit exists, whether two commands with group conflict exist, and whether the two commands with the same operation type and adjacent orders exist, and the judgment processing of the first position is executed in sequence. In one illustrative example, embodiments of the invention may be based on: judging whether a command meeting page hit exists, whether two commands with group conflict exist, and whether two adjacent commands with consistent operation types exist, according to the following steps: whether a command meeting page hit exists, whether two commands with group conflict exist, and whether two commands with the same operation type and adjacent orders exist, and the judgment processing of the first position is executed one by one.

In one illustrative example, an embodiment of the present invention determines whether a first location passes a consistency conflict check, comprising:

according to the sequence from the head to the tail of the command queue, carrying out consistency conflict check on the first command and the second command on the first position;

when the first command and the second command pass consistency conflict check, determining that the first position passes the consistency conflict check;

wherein the second command comprises: a read command and/or a write command immediately adjacent to the first location.

It should be noted that the consistency conflict check in the embodiment of the present invention is defined based on the address of the module and the attribute of reading and writing, and may include: module address conflicts and/or read-write conflicts; for example, according to the data processing process of the module, the read-write sequence of the module is preset, and therefore once the read-write sequence does not accord with the preset sequence, the conflict exists. In an exemplary embodiment, the rule of the consistency conflict in the embodiment of the present invention may be set by a person skilled in the art according to an implementation scenario. In an exemplary example, the modules in the embodiment of the present invention include a Central Processing Unit (CPU), a Data Processing Unit (DPU), a display module, and the like, which are integrated in an SOC, and which need to read and write data through a DRAM; in an exemplary embodiment, the embodiments of the present invention may distinguish each module in the SOC by a preset number, distinguish a command and an address of each module based on the number, and further perform a consistency conflict check. When the consistency conflict detection of the embodiment of the invention determines that the consistency conflict exists, the first position is deleted from the position where the first instruction can be inserted.

In one illustrative example, an embodiment of the present invention inserts a first command into a first location that passes a consistency conflict check, comprising:

the first command is inserted into the first position closest to the head of the command queue and passing the consistency conflict check.

In an illustrative example, embodiments of the invention may also insert the first command into another first location that passes the consistency conflict check. The first command is inserted into the first position which is closest to the head of the command queue and passes the consistency conflict check, so that the processing efficiency of the first command is improved, and the problem of time sequence (the later received command is inserted in front of the first command) caused by the position of the first command when the subsequent command is inserted is also avoided.

In an illustrative example, a method of an embodiment of the present invention further includes:

when it is determined that the first position for inserting the first command does not exist in the command queue, the first command is written to the tail of the command queue.

When the first position does not exist, the ordering of the command queue is kept unchanged, and the newly added first command is written into the tail of the command queue.

setting a timeout threshold for more than one third command in the command queue;

the third command is inserted at the head of the command queue if the third command is not executed within a timeout threshold.

In an illustrative example, embodiments of the invention may have a timeout threshold set by a technician depending on the system application; for example, the access unique Identifier (ID) of the sixth command is a read operation of a pen Display module (Display), and the timeout threshold may be dynamically configured according to the Display resolution. The setting of the overtime threshold value in the embodiment of the invention can be understood as an overtime mechanism or an aging mechanism, and the jamming of the command with the time limit requirement is avoided through the setting of the overtime threshold value.

determining a fourth command which can be operated in parallel in the command queue;

inserting more than one fourth command capable of operating in parallel in a first time delay interval of a group Conflict (Bank Conflict) of the first fourth command;

wherein the fourth command comprises: a multiple group (Muti-Bank) command and/or a group (BankGroup) command; the first and fourth commands include: a fourth command near the head of the command queue; the inserted one or more fourth commands operable in parallel include: a fourth command which is operable in parallel except for the first fourth command; the cumulative sum of the second latency intervals for group collisions of the inserted more than one fourth command operable in parallel is less than the first latency interval.

In an exemplary embodiment, in a usage scenario of the DRAM according to the embodiment of the present invention, a fixed number of fourth commands capable of being operated in parallel are inserted into the first delay interval; for example, two fourth commands are inserted that can be operated in parallel. The fixed number is directly set, so that the calculation step of the accumulated sum of the second time delay interval can be reduced, and the processing speed is improved. In an illustrative example, embodiments of the invention may look for the fourth command that may operate in parallel in order from head to tail. The fourth commands that can be operated in parallel may include multiple groups, and the embodiment of the present invention performs the above-mentioned processing separately for each group of the fourth commands. In one illustrative example, the inserted one or more parallel-operable fourth commands are fourth commands determined by command queue ordering, i.e., the ordering of the inserted fourth commands in the command queue is consistent with that before the non-inserted commands.

FIG. 5 is a diagram illustrating the insertion of a fourth command according to an embodiment of the present invention, as shown in FIG. 5, where the time permission parameter in FIG. 5 is a standard defined parameter of JEDEC, and the embodiment of the present invention hides the write operations of B4-R3 in the first delay interval (group conflict period) of the group conflict of B0; according to the partition operation attribute (the characteristic of needing long delay waiting) among the group conflicts, the read or write commands of other subsequent groups capable of being operated in parallel are executed in advance in the first time delay interval of the group conflicts; the delay of group collisions is hidden in a parallel manner.

The embodiment of the invention can avoid designing a complex logic mechanism of queue insertion ordering by inserting the fourth command, and reduce the logic coupling degree of the DRAM. In an exemplary embodiment, when the operation executed by the fourth command is a write operation, the first latency interval TCFH ═ tWR + tRP + tRCD of the group conflict of the write operation; wherein tWR denotes the time of write recovery, tRP denotes the time of precharge, and tRCD denotes the activation time, and the above time information can be obtained from Joint Electron devices engineering Commission JEDEC Manual. Correspondingly, theoretically, the number of the inserted multiple groups of write commands is equal to the first time delay interval/(data bus (DQ) collision Length (Burst Length)/2), and here, it should be noted that, when the number of the multiple groups of write commands included in the command queue is smaller than the number of commands that can be inserted in the calculation, only the multiple groups of write commands included in the command queue need to be inserted; fig. 6 is a schematic diagram illustrating insertion of a fourth command according to another embodiment of the present invention, and as shown in fig. 6, the time permission parameter in fig. 6 is a parameter defined by JEDEC standards, and in the embodiment of the present invention, more than 3 groups of commands are inserted in the first delay interval than in fig. 5, and through the insertion process of parallel operation, the bandwidth utilization of the data bus is improved according to the embodiment of the present invention.

In an exemplary embodiment, after inserting more than one fourth command that can be operated in parallel, the method of the embodiment of the present invention further comprises:

performing consistency conflict check on each fourth command in the more than one fourth commands capable of operating in parallel and the fifth command respectively;

when the fourth command and the fifth command pass consistency conflict check, performing data operation according to the fourth command when reading the fourth command;

when the fourth command and the fifth command do not pass the consistency conflict check, executing activation operation on the fourth command when the fourth command is read;

wherein the fifth command includes: the first command in the command queue after the more than one fourth command that can be operated on in parallel.

when the addresses of N commands in the command queue are determined to be continuous according to the address information of the commands, reading the data of the (N + 1) th address, and caching the read data and the address information in a preset cache region;

and when an instruction containing the (N + 1) th address is received, reading the cached data from the cache region according to the address information.

According to the embodiment of the invention, the continuity judgment is carried out on the addresses of the commands, and when the addresses of N commands are continuous, the data of the (N + 1) th address is read, so that the pre-reading of the data is realized; FIG. 7 is a diagram illustrating a data buffer according to an embodiment of the present invention, as shown in FIG. 7, the address of the pre-read is Bank2-Row1-Col 4; pre-reading data in a corresponding DRAM address, storing the data in a Buffer (Buffer) and recording address information of the data; if no write operation is carried out to the address subsequently, the Buffer is always the latest data, and if the write operation is carried out to the address, the write data in the Buffer is updated. If a new read command hits the Buffer, the data is read directly from the Buffer without reading the data from the DRAM granule.

It should be noted that, the addresses of the embodiment of the present invention continuously include: the group and row addresses are the same, and the column addresses are continuous; such as bank1-row1-c1- > bank1-row1-c2- > bank1-row1-c3- > bank1-row1-c 4; the value of N is set by the user according to the application scenario of the DRAM. The cache depth D can be set by a user according to system performance and application requirements; in an exemplary embodiment, the embodiment of the present invention may perform simulation through batch performance test to determine reasonable values of D and N, so that the system can achieve optimal performance.

deleting the data when the data cached in the cache area is not read and updated within a preset time length;

when the data cached in the cache region is not read within the preset time length but is updated, the data is output to the DRAM, and then the data output to the DRAM in the cache region is deleted.

In an exemplary embodiment, the preset time period may be set by a person skilled in the art according to an empirical value.

determining whether the first command is inserted into the first location;

and when the first command is not inserted into the first position, performing alarm processing.

According to the embodiment of the invention, by setting the self-checking function, when the problems including logic operation errors occur, the first command is not inserted into the first position, and then alarm processing is carried out; fig. 8 is a schematic diagram of alarm processing according to an embodiment of the present invention, and as shown in fig. 8, when no other group command is inserted between two group conflicts, alarm processing is performed; in an exemplary embodiment, the performing alarm processing according to the embodiment of the present invention includes: a module for generating an error report according to the first command not inserted into the first position, and feeding back the generated error report to a user through system information, mails or other modes or automatically processing alarms set in the system; the execution of the user or the module for automatically processing the alarm according to the received error report comprises the following steps: closing the plug-in function, and the like.

The embodiment of the invention determines the first position where the first command can be inserted, thereby realizing the rearrangement of the command queue and avoiding the read-write conflict through the consistency conflict check; by setting the overtime threshold, the problem of overlong waiting time of command waiting is avoided. By inserting the fourth command which can be operated in parallel into the interval time between the group conflicts, the complexity and the coupling degree of command scheduling are simplified, and the execution efficiency of the DRAM is improved. The data is pre-read through the continuity judgment of the address, so that fewer queue resources are used, and better reading efficiency can be obtained under the condition of continuous reading; the embodiment of the invention realizes the real-time discovery of the queue scheduling problem through the alarm processing and provides a basis for timely adjusting the command scheduling.

The embodiment of the invention also provides a computer storage medium, wherein a computer program is stored in the computer storage medium, and when being executed by a processor, the computer program realizes the method for realizing the command scheduling.

An embodiment of the present invention further provides a terminal, including: a memory and a processor, the memory having stored therein a computer program; wherein the content of the first and second substances,

the processor is configured to execute the computer program in the memory;

the computer program, when executed by a processor, implements a method of implementing command scheduling as described above.

Fig. 9 is a block diagram of an apparatus for implementing command scheduling according to an embodiment of the present invention, as shown in fig. 9, including: a position determining unit, a conflict checking unit and an insertion processing unit; wherein the content of the first and second substances,

wherein the first command comprises: a read command or a write command.

In one illustrative example, an embodiment of the present invention determines that the location unit is configured to:

when the command which accords with page hit exists in the command queue, determining the position behind the command which accords with page hit as a first position;

when two commands with group conflict exist in the command queue, determining the middle position of the two commands with group conflict as a first position;

when two adjacent commands with the same operation type exist in the command queue, determining the middle position of the two adjacent commands with the same operation type as a first position; wherein the operation types include: a read operation and a write operation.

In an exemplary embodiment, the conflict checking unit of the embodiment of the present invention is configured to:

In an illustrative example, an insertion processing unit of an embodiment of the present invention is configured to:

In an exemplary embodiment, the insertion processing unit of the embodiment of the present invention is further configured to:

the determine position unit writes the first command to the tail of the command queue when determining that the first position for inserting the first command does not exist in the command queue.

In an exemplary embodiment, the apparatus of the embodiment of the present invention further includes a timeout processing unit configured to:

setting a timeout threshold for more than one third command in the command queue; the third command is inserted at the head of the command queue if the third command is not executed within a timeout threshold.

In an exemplary embodiment, the apparatus of the present invention further includes a parallel processing unit configured to:

determining a fourth command which can be operated in parallel in the command queue; inserting more than one fourth command which can be operated in parallel in a first time delay interval of the group conflict of the first fourth command;

wherein the fourth command comprises: multiple sets of commands and/or group commands; the first and fourth commands include: a fourth command near the head of the command queue; the inserted one or more fourth commands operable in parallel include: a fourth command which is operable in parallel except for the first fourth command; the cumulative sum of the second latency intervals for group collisions of the inserted more than one fourth command operable in parallel is less than the first latency interval.

In an exemplary embodiment, the parallel processing unit according to the embodiment of the present invention is further configured to:

In an exemplary embodiment, the apparatus of the present invention further includes a pre-reading unit configured to:

In an exemplary embodiment, the pre-reading unit of the embodiment of the present invention is further configured to:

In an exemplary embodiment, the apparatus of the embodiment of the present invention further includes an alarm unit, configured to:

determining whether the first command is inserted into the first location; and when the first command is not inserted into the first position, performing alarm processing.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A method of implementing command scheduling, comprising:

when a Dynamic Random Access Memory (DRAM) receives a first command, determining whether a first position for inserting the first command exists in a command queue;

wherein the first command comprises: a read command or a write command.

2. The method of claim 1, wherein determining whether a first position exists in the command queue for inserting the first command comprises:

when the command which accords with page hit exists in the command queue, determining the position behind the command which accords with page hit as the first position;

when two commands with group conflict exist in the command queue, determining the middle position of the two commands with group conflict as the first position;

when two adjacent commands with the same operation type exist in the command queue, determining the middle position of the two adjacent commands with the same operation type as the first position;

wherein the operation types include: a read operation and a write operation.

3. The method of claim 1, wherein determining whether the first location passes a consistency conflict check comprises:

according to the sequence from the head to the tail of the command queue, performing consistency conflict check on the first command and the second command on the first position;

when the first command and the second command pass the consistency conflict check, determining that the first position passes the consistency conflict check;

4. The method of claim 1, wherein inserting the first command into the first location that passes consistency conflict checking comprises:

inserting the first command into a first location closest to the head of the command queue and passing the consistency conflict check.

5. The method according to any one of claims 1 to 4, further comprising:

and writing the first command into the tail part of the command queue when determining that the first position for inserting the first command does not exist in the command queue.

6. The method according to any one of claims 1 to 4, further comprising:

the third command is inserted at the head of the command queue if the third command is not executed within the timeout threshold.

7. The method according to any one of claims 1 to 4, further comprising:

determining a fourth command in the command queue that is operable in parallel;

inserting more than one fourth command which can be operated in parallel in a first time delay interval of the group conflict of the first fourth command;

wherein the fourth command comprises: multiple sets of commands and/or group commands; the first fourth command includes: a fourth command near the head of the command queue; the inserted one or more fourth commands operable in parallel include: a fourth command other than the first fourth command and operable in parallel; the cumulative sum of the second latency intervals for group collisions of the inserted more than one fourth command operable in parallel is less than the first latency interval.

8. The method of claim 7, wherein after said inserting more than one fourth command that is operable in parallel, the method further comprises:

performing consistency conflict check on each fourth command in the more than one fourth commands capable of operating in parallel and a fifth command respectively;

when the fourth command and the fifth command do not pass the consistency conflict check, executing an activation operation on the fourth command when the fourth command is read;

wherein the fifth command comprises: a first command in the command queue that is ordered after the more than one fourth command that is operable in parallel.

9. The method according to any one of claims 1 to 4, further comprising:

and when an instruction containing the (N + 1) th address is received, reading cached data from the cache region according to the address information.

10. The method of claim 9, further comprising:

deleting the data cached in the cache area when the data is not read and updated within a preset time length;

when the data cached in the cache region is not read within a preset time period but is updated, the data is output to the DRAM, and then the data output to the DRAM in the cache region is deleted.

11. The method according to any one of claims 1 to 4, further comprising:

determining whether the first command is inserted into the first location;

12. A computer storage medium having a computer program stored thereon, which, when being executed by a processor, carries out the method of carrying out command scheduling according to any one of claims 1 to 11.

13. A terminal, comprising: a memory and a processor, the memory having a computer program stored therein; wherein the content of the first and second substances,

the processor is configured to execute the computer program in the memory;

the computer program, when executed by the processor, implementing a method of implementing command scheduling as claimed in any of claims 1 to 11.

14. An apparatus for implementing command scheduling, comprising: a position determining unit, a conflict checking unit and an insertion processing unit; wherein the content of the first and second substances,

wherein the first command comprises: a read command or a write command.