CN114287060A

CN114287060A - Pixel structure and manufacturing method thereof

Info

Publication number: CN114287060A
Application number: CN201980099784.9A
Authority: CN
Inventors: 施琛; 潘撼; 巩啸风; 唐样洋
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-09-10
Filing date: 2019-09-10
Publication date: 2022-04-05
Also published as: EP4024458A4; EP4024458A1; WO2021046730A1

Abstract

A pixel structure (2003) and a method of manufacturing a pixel structure (2003), the pixel structure (2003) comprising: a modulation gate set, the modulation gate set comprising: at least one first modulation gate (PGA) and at least one second modulation gate (PGB) disposed on the first surface (2011) of the substrate (201), the second modulation gate (PGB) and the first modulation gate (PGA) each being complementarily modulated; and a substrate (201) comprising: two carrier storage regions respectively located on two sides of the substrate (201) in a first direction, wherein the first direction is a direction parallel to the first surface (2011); and a carrier collection region (202) located between the two carrier storage regions in the first direction and in contact with the modulation gate group on the first surface (2011), wherein the carrier collection region (202) is of the same doping type as the two carrier storage regions, the carrier collection region (202) is of the opposite doping type as the substrate (201), and the doping concentration of the carrier collection region (202) is greater than the doping concentration of the substrate (201).

Description

Pixel structure and manufacturing method thereof

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a pixel structure and a manufacturing method of the pixel structure.

Background

Time Of Flight (TOF) based 3D imaging is a technique that can measure the Time Of Flight Of light waves to generate depth information. The light wave generated by the laser and passing through the modulation is reflected after encountering the object and is received by the sensor, and the 3D information of the shot object is converted by calculating the time difference between the light ray emission and the light ray reflection.

As shown in fig. 1, the Indirect Time Of Flight (i-TOF) technique is to compare the phase difference between the received reflected light and the transmitted light, calculate the Time Of Flight, and then obtain the depth information Of the object to be measured. The specific implementation method is that control signals with different phases are used for modulating and collecting photo-generated carriers, so that the photo-generated carriers are integrated in different time periods, and finally the phase difference between reflection information and an emission signal is calculated.

As mentioned above, the pixel design of i-TOF is to realize the modulation inside the pixel structure, i.e. collecting and reading the photogenerated carriers generated by the device in different time periods. In a specific design as shown in fig. 2, there are typically two complementary TAPs: TAPA and TAPB, ideally, the photogenerated carriers generated in the period a are Sa, which is all collected by TAPA, and the photogenerated carriers generated in the other period (period B) are Sb, which is all collected by TAPB. Generally, the switching frequency of TAPA and TAPB is consistent with the Modulation frequency of the infrared light emitted by the laser, and one performance index for evaluating the design quality of the pixel is Modulation Contrast (MC), also called Modulation-demodulation efficiency, where MC satisfies the following formula:

MC (Sa-Sb)/(Sa + Sb) (formula 1).

Based on the above, if the light is turned on only in the a period, TAPA will collect all photogenerated carriers Sa, and TAPB will collect carriers Sb of 0. When Sb is 0, MC is 100% in formula 1. But due to non-idealities in device design, part of the photogenerated carriers generated during period a are collected by TAPB, and the actual MC may be less than 100%.

In 3D imaging, object distances measured from an i-TOF camera are not 100% accurate due to the presence of noise, limitations in modulation frequency, and the like. The basic idea for improving the ranging accuracy is to let the pixels absorb as much as possible of the effectively modulated light and to distribute the generated carriers more accurately to the different gates. At the same time, the higher the frequency of this modulation process, the higher the resulting accuracy.

Currently, to improve the spatial resolution of i-TOF cameras, TOF pixel structures are evolving towards small pixel structures. The small pixel structure causes a decrease in the amount of incoming light, thereby degrading the range finding accuracy of the i-TOF. To compensate for the loss of the amount of incoming light, the pixels of the i-TOF need to obtain high modulation contrast at high modulation frequencies.

One of the main reasons for affecting MC at high frequencies (>100MHz) is the carrier collection speed. As shown in fig. 3, TOF devices require thicker silicon (>4um) to absorb sufficient infrared light due to the low absorption coefficient of silicon devices for near infrared light. And the potential change at the bottom of the device is small, so that the speed of carriers is low, and a long time is needed for reaching a collection point at the top.

If these bottom-generated carriers are not collected efficiently to a designated collection point in a sufficiently short time, they may be collected by other collection points in a subsequent period of time, resulting in a drop in MC, affecting the ranging accuracy. And this MC degradation problem due to too long carrier collection time is more serious at high frequencies.

Disclosure of Invention

The embodiment of the application provides a pixel structure and a manufacturing method of the pixel structure, and solves the problem of low modulation and demodulation efficiency of a small pixel structure.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect of embodiments of the present application, a pixel structure is provided, including: a modulation gate set comprising: the first modulation grid electrodes are respectively and sequentially arranged on the first surface of the substrate; at least one second modulation grid electrode is respectively and sequentially arranged on the first surface, and the at least one second modulation grid electrode and the at least one first modulation grid electrode are respectively subjected to complementary modulation; and the substrate, comprising: at least two carrier storage regions, the at least two carrier storage regions comprising: a first carrier storage region and a second carrier storage region respectively located on both sides of the substrate in a first direction, the first direction being a direction parallel to the first surface; and a carrier collection region located between the at least two carrier storage regions in the first direction and in contact with the at least one first modulation gate and the at least one second modulation gate at the first surface, wherein the carrier collection region is of the same doping type as the at least two carrier storage regions and the carrier collection region is of an opposite doping type to the substrate. Thus, a PN junction depletion region is formed at the position where the carrier collection region is adjacent to the substrate, substrate ions at two sides of the PN junction depletion region are opposite in electrical property, an electric field is created, and when the electric field is enough to prevent further transfer of holes and electrons, the PN junction depletion region reaches the equilibrium size.

In addition, the carrier collection region has a doping concentration greater than a doping concentration of the substrate. Thus, in the process of forming the PN junction depletion region, the formed PN junction depletion region is also more biased toward the substrate. When the substrate is irradiated by light, carriers are generated in the substrate, and the carriers in the substrate enter the carrier collection region under the action of an electric field of the PN junction depletion region because the PN junction depletion region is more inclined to the substrate. In the prior art, the carrier concentration at the bottom of the substrate is low, and the potential change is only limited in a shallow region from one surface to the inside, so that the speed of the carrier at the bottom of the substrate is low, and a long time is required for reaching a carrier collection point of the first surface, thereby affecting the modulation and demodulation efficiency of the pixel structure. The substrate potential changes from the first surface to the bottom of the substrate more uniformly, the carrier speed of the bottom of the substrate is improved, the carriers can be collected quickly, the modulation and demodulation efficiency of the pixel structure is improved, and the distance measurement precision is improved.

In an alternative implementation, the carrier collection region includes: a first doped region and a second doped region respectively located at both sides of the carrier collection region in the first direction; and a third doped region located between the first doped region and the second doped region, wherein the doping concentration of the first doped region and the doping concentration of the second doped region are both greater than the doping concentration of the third doped region. Therefore, when the pixel structure is reset, the current carriers in the substrate are all concentrated on the first surface of the substrate, if the current carrier collecting region adopts a single doping concentration, a local potential well is formed in the middle position of the surface of the substrate, so that the current carriers cannot be pumped away in the resetting process, if the current carrier collecting region adopts a doping mode that the doping concentrations of the first doping region and the second doping region on the two sides of the current carrier collecting region are high, and the doping concentration of the third doping region in the middle position of the current carrier collecting region is low, the formation of the local potential well in the middle is avoided, the current carriers in the middle position of the first surface of the substrate are favorably pumped away in the resetting process, and the pixel structure is easier to reset.

In an alternative implementation, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region, the first carrier storage region being close to the first modulation gate and far from the second modulation gate, the second carrier storage region being close to the second modulation gate and far from the first modulation gate, wherein: the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, and the at least one first modulation gate includes a first end closest to the first carrier storage region and a second end farthest from the first carrier storage region, and the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end farthest from the second carrier storage region; wherein the first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction, and the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction. Therefore, a distance for regulating the first modulation grid is reserved between the first carrier storage region and the first doping region, and a distance for regulating the second modulation grid is reserved between the second carrier storage region and the second doping region.

In an alternative implementation manner, the doping concentration of the first doping region is 10 to 100 times that of the third doping region, and the doping concentration of the second doping region is 10 to 100 times that of the third doping region. Therefore, the concentration difference between the first doping area and the third doping area is increased, the concentration difference between the second doping area and the third doping area is increased, and the resetting of the pixel structure is facilitated.

In an alternative implementation manner, the first doped region and the second doped region are symmetrically disposed about a first axis, and the third doped region is symmetric about the first axis, wherein the first axis is perpendicular to the first surface. Thus, when the at least one first modulation gate and the at least one second modulation gate are complementarily modulated, carriers in the substrate have the same ability to enter the first carrier storage region and the second carrier storage region.

In an alternative implementation, the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region, the first carrier storage region is close to the first modulation gate and far from the second modulation gate, the second carrier storage region is close to the second modulation gate and far from the first modulation gate, wherein: the at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region, and the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region; wherein the carrier collection region is located between the first end of the at least one first modulation gate and the first end of the at least one second modulation gate in the first direction. Thus, a distance for the first modulation gate to regulate is left between the first carrier storage region and the carrier collection region, and a distance for the second modulation gate to regulate is left between the second carrier storage region and the carrier collection region.

In an alternative implementation, the carrier collection region has a length, in a direction perpendicular to the first surface, equal to the length of the substrate. Therefore, PN junction depletion regions can be formed on the substrates on the two sides of the carrier collection region, carriers in the substrates on the two sides of the carrier collection region can flow into the carrier collection region under the action of an electric field of the PN junction depletion regions, and the modulation and demodulation efficiency of the pixel structure is improved.

In an alternative implementation, the carrier collection region has a length, in a direction perpendicular to the first surface, that is less than the length of the substrate. Therefore, a PN junction depletion region can be formed at the bottom of the substrate, so that carriers at the bottom of the substrate can flow into the carrier collection region under the action of an electric field of the PN junction depletion region, and the modulation and demodulation efficiency of the pixel structure is improved.

In an alternative implementation, the carrier storage region includes: a first carrier storage region proximate the at least one first modulation gate and a second carrier storage region proximate the at least one second modulation gate; a first grid is arranged between the at least one first modulation grid and the first carrier storage region, and a second grid is arranged between the at least one second modulation grid and the second carrier storage region; the at least one first modulation grid and the at least one second modulation grid are used for receiving alternating current modulation signals, and the first grid and the second grid are used for receiving direct current modulation signals. Therefore, the direct current signal received by the first grid can shield the influence of the alternating current signal received by the at least one first modulation grid on the first carrier storage region. Similarly, the dc signal received by the second gate may shield the ac signal received by the at least one second modulation gate from affecting the second carrier storage region.

In an alternative implementation manner, the doping concentration of the carrier collection region is 1000-10000 times of the doping concentration of the substrate. Therefore, the concentration difference of the doping concentration between the carrier collection region and the substrate is improved, the PN junction depletion region is favorable for deviating to the substrate, carriers in the substrate can easily enter the carrier collection region under the action of an electric field, and the modulation and demodulation efficiency of the pixel structure is improved.

In an alternative implementation, the carrier collection region is doped P-type, and the substrate is doped N-type; or the carrier collection region is doped with N type, and the substrate is doped with P type. Therefore, a PN junction depletion region is formed between the substrate and the carrier collection region, and the modulation and demodulation efficiency of the pixel structure is improved.

In an optional implementation manner, the modulation gate group further includes: at least one third modulation grid electrode which is respectively arranged on the first surface of the substrate in sequence; at least one fourth modulation grid which is respectively and sequentially arranged on the first surface, wherein the at least one first modulation grid, the at least one second modulation grid, the at least one third modulation grid and the at least one fourth modulation grid are respectively subjected to complementary modulation; the first and second modulation gates are symmetric about a center of the first surface, and the third and fourth modulation gates are symmetric about the center of the first surface; the at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region respectively located on two sides of the substrate in a second direction, wherein the second direction is parallel to the first surface and is perpendicular to the first direction; the carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction. Thereby, the modulation of the modulation gate is made more flexible.

In a second aspect of the embodiments of the present application, a method for manufacturing a pixel structure is provided, where the method includes: forming at least two carrier storage regions on a substrate by ion implantation, wherein the at least two carrier storage regions comprise: a first carrier storage region and a second carrier storage region respectively located on both sides of the substrate in a first direction, the first direction being a direction parallel to the first surface; forming a carrier collection region on the substrate by ion implantation; wherein the carrier collection region is located between the first carrier storage region and the second carrier storage region in the first direction, the doping concentration of the carrier collection region is greater than the doping concentration of the substrate, the doping types of the carrier collection region and the at least two carrier storage regions are the same, and the doping types of the carrier collection region and the substrate are opposite; providing at least one first modulation gate and at least one second modulation gate on a first surface of the substrate; wherein the at least one second modulation gate and the at least one first modulation gate are complementarily modulated, respectively, and the carrier collection region is in contact with the first surface with the at least one first modulation gate and the at least one second modulation gate.

In an alternative implementation, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region, the first carrier storage region being close to the first modulation gate and far from the second modulation gate, the second carrier storage region being close to the second modulation gate and far from the first modulation gate, wherein: the at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region, and the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region; the disposing at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes: the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction such that the carrier collection region is located between a first end of the at least one first modulation gate and a first end of the at least one second modulation gate in the first direction.

In an alternative implementation, the forming a carrier collection region on a substrate by ion implantation includes: forming a first doped region and a second doped region on the substrate by ion implantation; the first doping area and the second doping area are respectively positioned at two sides of the carrier collection area in the first direction; and forming a third doped region on the substrate by ion implantation, wherein the doping concentration of the first doped region and the second doped region is greater than that of the third doped region, and the third doped region is positioned between the first doped region and the second doped region.

In an alternative implementation, the forming a carrier collection region on a substrate by ion implantation includes: forming a first doped region and a second doped region on the substrate by ion implantation; the first doping area and the second doping area are respectively positioned at two sides of the carrier collection area in the first direction; the ions of the first doped region and the second doped region are diffused to a third region to form a third doped region, wherein the doping concentration of the first doped region and the doping concentration of the second doped region are both greater than the doping concentration of the third doped region, and the third doped region is located between the first doped region and the second doped region.

In an alternative implementation, the at least two carrier storage regions include a first carrier storage region and a second carrier storage region, the first carrier storage region being close to the first modulation gate and far from the second modulation gate, the second carrier storage region being close to the second modulation gate and far from the first modulation gate, wherein: the at least one first modulation gate includes a first end closest to the first carrier storage region and a second end furthest from the first carrier storage region, and the at least one second modulation gate includes a first end closest to the second carrier storage region and a second end furthest from the second carrier storage region; the disposing at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes: the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction such that the first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction and such that the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction.

In an alternative implementation manner, the doping concentration of the first doping region is 10 to 100 times that of the third doping region, and the doping concentration of the second doping region is 10 to 100 times that of the third doping region.

In an alternative implementation manner, the first doped region and the second doped region are symmetrically disposed about a first axis, and the third doped region is symmetric about the first axis, wherein the first axis is perpendicular to the first surface.

In an alternative implementation, the carrier collection region has a length, in a direction perpendicular to the first surface, that is less than or equal to the length of the substrate.

In an alternative implementation, the at least two carrier storage regions include: a first carrier storage region proximate the at least one first modulation gate, and a second carrier storage region proximate the at least one second modulation gate, the method further comprising: disposing a first gate between the at least one first modulation gate and the first carrier storage region; disposing a second gate between the at least one second modulation gate and the second carrier storage region; the first modulation grid and the second modulation grid are used for receiving alternating current modulation signals, and the first grid and the second grid are used for receiving direct current modulation signals.

In an alternative implementation manner, the doping concentration of the carrier collection region is 1000-10000 times of the doping concentration of the substrate.

In an alternative implementation, the carrier collection region is doped P-type, and the substrate is doped N-type; or the carrier collection region is doped with N type, and the substrate is doped with P type.

In an optional implementation manner, the modulation gate group further includes: at least one third modulation grid electrode which is respectively arranged on the first surface of the substrate in sequence; at least one fourth modulation grid which is respectively and sequentially arranged on the first surface, wherein the at least one first modulation grid, the at least one second modulation grid, the at least one third modulation grid and the at least one fourth modulation grid are respectively subjected to complementary modulation; the first and second modulation gates are symmetric about a center of the first surface, and the third and fourth modulation gates are symmetric about the center of the first surface; the at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region respectively located on two sides of the substrate in a second direction, wherein the second direction is parallel to the first surface and is perpendicular to the first direction; the carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction.

Drawings

FIG. 1 is a schematic diagram of an i-TOF image acquisition in the prior art;

FIG. 2 is a schematic diagram of a prior art pixel structure showing the transfer of carriers;

FIG. 3 is a schematic diagram of another prior art pixel structure for transferring carriers;

fig. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of the display module shown in FIG. 4;

fig. 6a is a schematic structural diagram of another terminal device provided in the embodiment of the present application;

fig. 6b is a schematic diagram of a depth image acquisition according to an embodiment of the present disclosure;

FIG. 7 is a schematic view of a configuration of the camera head of FIG. 6 b;

fig. 7a is a top view of a pixel structure provided in an embodiment of the present application;

FIG. 7b is a cross-sectional view A-A of FIG. 7 a;

FIG. 7c is a schematic view of a carrier transport in the pixel structure of FIG. 7 b;

fig. 7d is a top view of another pixel structure provided in the embodiments of the present application;

fig. 8 is a graph illustrating the variation of the internal potential of the pixel structure according to the embodiment of the present disclosure;

fig. 9 is a schematic diagram of another pixel structure according to an embodiment of the present disclosure;

fig. 10 is a graph illustrating a variation in potential of a first surface of a pixel structure according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of another pixel structure according to an embodiment of the present disclosure;

fig. 12a is a schematic structural diagram of another pixel structure provided in this embodiment of the present application;

fig. 12b is a schematic structural diagram of another pixel structure provided in this embodiment of the present application;

fig. 13a is a schematic structural diagram of another pixel structure provided in this embodiment of the present application;

fig. 13b is a schematic structural diagram of another pixel structure provided in this embodiment of the present application;

fig. 14 is a schematic structural diagram of another pixel structure according to an embodiment of the present disclosure;

fig. 15 is a flowchart of a method for manufacturing a pixel structure according to an embodiment of the present disclosure;

15a, 15b, 15c are schematic views of the product structure obtained after the steps in FIG. 15 are performed;

fig. 16 is a flowchart of a method for manufacturing another pixel structure according to an embodiment of the present disclosure;

FIGS. 16a and 16b are schematic views of the product structure obtained after the steps in FIG. 16 are performed;

fig. 17 is a flowchart of a method for manufacturing another pixel structure according to an embodiment of the present disclosure;

fig. 18 is a flowchart of a method for manufacturing another pixel structure according to an embodiment of the present disclosure;

fig. 18a is a schematic diagram of a product structure obtained after the steps in fig. 18 are performed.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

Further, in the present application, directional terms such as "upper" and "lower" are defined with respect to a schematically-disposed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts that are used for descriptive and clarity purposes and that will vary accordingly with respect to the orientation in which the components are disposed in the drawings.

Hereinafter, terms that may appear in the embodiments of the present application are explained.

N-type doping (N is Negative prefix, which is the name given to the charge due to the Negative charge): in a silicon crystal (or germanium crystal) doped with a small amount of phosphorus (or antimony), since a semiconductor atom (e.g., a silicon atom) is replaced by an impurity atom, four of the five outer electrons in the outer layer of the phosphorus atom form covalent bonds with the surrounding semiconductor atoms, and the extra electron is hardly bound and is easily a free electron. Thus, the N-type semiconductor becomes a semiconductor having a high electron concentration, and its conductivity is mainly due to conduction of free electrons.

P-type doping (P is Positive, since the hole is positively charged, the name is given): in a silicon crystal (or germanium crystal) doped with a small amount of boron (or indium), since a semiconductor atom (e.g., silicon atom) is replaced by an impurity atom, when three outer electrons of the outer layer of the boron atom form covalent bonds with surrounding semiconductor atoms, a "hole" is generated, which may attract bound electrons to "fill in" the hole, so that the boron atom becomes a negatively charged ion. Thus, such semiconductors are capable of conducting electricity because they contain a relatively high concentration of "holes" ("corresponding to" positive charges).

PN junction depletion layer: an N-type semiconductor has an excess of free electrons compared to a P-type region, and a P-type has an excess of holes compared to an N-type region. Thus, when N-doped and P-doped semiconductor fins are placed together to form a junction, electrons migrate to the P-side and holes migrate to the N-side. The departure of electrons from the N-side to the P-side leaves behind the N-side a positive donor ion and likewise leaves a negative acceptor ion on the P-side.

After transfer, the diffused electrons come into contact with holes on the P-side and are eliminated by recombination. The same is true for the N-side diffusion holes. The net result is that the diffused electrons and holes disappear, leaving charged ions adjacent to the interface in the region where there are no moving carriers (which is why the carriers are depleted, called depletion region). Uncompensated ions are positive on the N-side and negative on the P-side. This creates an electric field that provides a force against the continual exchange of charge carriers. The depletion region reaches its equilibrium size when the electric field is sufficient to prevent further transfer of holes and electrons.

Carrier: there are two types of carriers in a semiconductor, namely electrons and holes. Charged particles capable of directional movement under the action of an electric field.

Ion implantation: when an ion beam is directed at a solid material in a vacuum, the ion beam is resisted by the solid material and slowly slows down, and finally stays in the solid material, which is called ion implantation.

The embodiment of the application provides a terminal device. The terminal device includes, for example, a mobile phone, a tablet computer, a Personal Digital Assistant (PDA), a vehicle-mounted computer, and the like. The embodiment of the present application does not specially limit the specific form of the terminal device. For convenience of description, the following description will be given taking a terminal device as a mobile phone as shown in fig. 4 as an example.

As shown in fig. 4, the terminal device 01 mainly includes, but is not limited to, a display module 10. The display module 10, the middle frame 11 and the rear cover 12. The middle frame 11 is used for supporting the display module 10 on a side facing the display module 10, and a battery, a Printed Circuit Board (PCB), a Camera (Camera), an antenna, and other internal components are disposed on a side facing the rear cover 12. The rear shell 12 is fastened to the middle frame 11 for protecting the internal components.

In some embodiments of the present application, as shown in fig. 5, the display module 10 includes a display screen (DP) 101. The display 101 may be a Liquid Crystal Display (LCD). In this case, the display module 10 further includes a backlight unit (BLU) 102 for providing a light source to the LCD.

Alternatively, in other embodiments of the present application, the display screen 101 may be an Organic Light Emitting Diode (OLED) display screen, and the OLED display screen can realize self-luminescence, so that the BLU102 is not required to be disposed in the display module 10.

In addition, the above description is made by taking an example in which the terminal device 01 includes one display module 10. In some embodiments, the terminal device 01 may include one or at least two display modules 10.

In addition, as the integration degree of the terminal device 01 is higher, the terminal device 01 may further include a camera 100 as shown in fig. 6 a. The camera 100 may be a depth camera, and can obtain depth information of a subject to implement gesture recognition or face recognition.

The camera 100 can be based on 3D imaging technology of TOF, as shown in fig. 6b, and the camera 100 sends a modulated emitted light signal S1 to a subject, such as a human face. After the light signal S1 is reflected by a human face, a reflected light signal S2 is received by the camera 100. Therefore, the camera 100 can obtain the depth information (i.e. distance information) of the measured object by calculating the time difference between the emitted light signal S1 and the reflected light signal S2, thereby achieving the purpose of face recognition. In some embodiments, terminal device 01 may include at least one camera 100.

In some embodiments of the present application, the camera 100 includes a lens and an image sensor 200 as shown in fig. 7. The image sensor 200 includes a plurality of pixel units 2001 and a substrate 2002. Each pixel unit 2001 and a substrate disposed below the pixel unit 2001 constitute one pixel structure 2003.

The above-described camera 100 further includes a readout circuit 210 and a control circuit 211 coupled to the pixel circuits of the pixel unit 2001, and an image processing circuit 212. The control circuit 211 may perform photoelectric conversion with the pixel unit 2001 and transmit the converted electric signal to the readout circuit 210 at the readout time of the pixel circuit. The readout circuit 210 may perform analog-to-digital conversion and signal amplification processing on an input signal.

Next, the readout circuit 210 transmits the processed electric signal to the image processing circuit 212. The image processing circuit 212 may generate a digital image signal from the received electrical signal by using an Image Signal Processing (ISP) technique, and convert the digital image signal into depth information through a Digital Signal Processing (DSP).

Fig. 7a is a top view of a pixel structure provided in an embodiment of the present application, and fig. 7b is a cross-sectional view taken along a line a-a in fig. 7 a. As shown in fig. 7a and 7b, the pixel structure 2003 includes: a substrate 201. The material of the substrate is not limited in the embodiments of the present application, and the material of the substrate may be, for example, silicon.

A modulation gate group is arranged on the substrate, and the modulation gate group comprises: at least one first modulation gate and at least one second modulation gate. The at least one first modulation gate is sequentially disposed on the first surface 2011 of the substrate 201, the at least one second modulation gate is sequentially disposed on the first surface 2011, and the at least one second modulation gate and the at least one first modulation gate are complementarily modulated.

The number of the first modulation gate and the second modulation gate may be 1 or more, but fig. 7b illustrates a case of one modulation gate.

As shown in fig. 7b, the first modulation gate includes: a first left modulation gate PGA.

The second modulation gate includes: a first right modulation gate PGB.

Note that "PG" is an english abbreviation of photo gate (raster diode).

Wherein the at least one first modulation gate and the at least one second modulation gate are complementarily modulated, which may be: in the time period a, the first left modulation gate PGA is turned on, and the first right modulation gate PGB is turned off.

In other time periods other than the time period a, for example, in the time period B, the first right modulation gate PGB is turned on, and the first left modulation gate PGA is turned off. Based on the above, it can be considered that the first left modulation gate PGA and the first right modulation gate PGB are complementarily modulated.

The first surface 2011 may be any surface of the substrate 201. In the present embodiment, the first surface 2011 is a surface of the substrate for collecting carriers, the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface 2011, and the carrier collection region 202 is in contact with the at least one first modulation gate and the at least one second modulation gate.

In some embodiments of the present application, when the transistor is an N-type transistor, the material constituting the semiconductor substrate 201 may be a P-type semiconductor material. In addition, the gate of each transistor may include a Gate Oxide Layer (GOL) adjacent to the semiconductor substrate 201, and a Polysilicon Layer (PL) on a surface of the gate oxide layer on a side away from the semiconductor substrate 201.

The substrate 201 may include: at least two carrier storage regions and a carrier collection region 202.

The at least two carrier storage regions are respectively located on two sides of the substrate 201 in a first direction, the first direction is a direction parallel to the first surface 2011, and the carrier collection region 202 is located between the two carrier storage regions in the first direction. The first direction may be the direction of the X-axis in fig. 7 a.

The number of the carrier storage regions may be 2 or more.

As shown in fig. 7d, in one implementation of the present application, the number of carrier storage regions is 4: a first carrier storage region FDA1, a second carrier storage region FDA2, a third carrier storage region FDB1, and a fourth carrier storage region FDB 2. The first carrier storage region FDA1, the second carrier storage region FDA2, the third carrier storage region FDB1 and the fourth carrier storage region FDB2 are located at four corners of the first surface, respectively.

The modulation gate group includes: a first modulation gate PGA1, a second modulation gate PGA2, a third modulation gate PGB1, and a fourth modulation gate PGB 2. The first and second modulation gates PGA1 and 2 are symmetrical with respect to the center of the first surface, and the third and fourth modulation gates PGB1 and PGB2 are symmetrical with respect to the center of the first surface. Wherein the first modulation gate PGA1, the second modulation gate PGA2, the third modulation gate PGB1 and the fourth modulation gate PGB2 can be complementarily modulated:

in the time period a, the first modulation gate PGA1 is turned on, the second modulation gate PGA2, the third modulation gate PGB1 and the fourth modulation gate PGB2 are turned off, and the first carrier collection region FDA1 is configured to collect carriers of the first modulation gate PGA 1.

In the time period B, the second modulation gate PGA2 is turned on, the first modulation gate PGA1, the third modulation gate PGB1 and the fourth modulation gate PGB2 are turned off, and the second carrier storage region FDA2 is configured to collect carriers of the second modulation gate PGA 2.

In the time period C, the third modulation gate PGB1 is turned on, the first modulation gate PGA1, the second modulation gate PGA2 and the fourth modulation gate PGB2 are turned off, and the third carrier collection region FDB1 is configured to collect carriers of the third modulation gate PGB 1.

In the period D, the fourth modulation gate PGB2 is turned on, the first modulation gate PGA1, the second modulation gate PGA2 and the third modulation gate PGB1 are turned off, and the fourth carrier storage region FDB2 is configured to collect carriers of the fourth carrier collection region PGB 2.

Among them, the first carrier storage region FDA1 and the second carrier storage region FDA2 are located on both sides of the substrate in the first direction. The first direction is for example the same as the extension direction of the diagonal a in fig. 7 d.

The carrier collection region is located between the first carrier storage region FDA1 and the second carrier storage region FDA2 in the first direction.

The third carrier storage region FDB1 and the fourth carrier storage region FDB2 are located at both sides of the substrate in the second direction.

The carrier collection region is located between the third carrier storage region FDB1 and the fourth carrier storage region FDB2 in the second direction. The second direction is for example the same as the extension direction of the diagonal b in fig. 7 d.

In fig. 7d, the cross-sectional views of the diagonal line a and the diagonal line b can refer to the description of fig. 7b, and are not repeated here.

In another implementation of the present application, as shown in fig. 7a, there are 2 carrier storage regions. The carrier storage region may include: a first carrier storage region FDA on the left side of the substrate 201, and a second carrier storage region FDB on the right side of the substrate 201.

The first carrier storage region FDA is used to collect carriers in the PGA, and the second carrier storage region FDB is used to collect carriers in the PGB.

The term "FD" is abbreviated as floating diffusion (english).

Next, a case where 2 carrier storage regions are provided will be described as an example.

When the substrate is irradiated by the infrared light, carriers are generated inside the substrate, the carrier collection region 202 collects the carriers in the substrate 201, and the carriers in the substrate 201 are stored in the first carrier storage region FDA through the first left modulation gate PGA or in the second carrier storage region FDB through the first right modulation gate PGB under the modulation of the first left modulation gate PGA or the first right modulation gate PGB.

Referring next to fig. 7a, the carrier collection region 202 is of the same doping type as the first carrier storage region FDA and the second carrier storage region FDB, and the carrier collection region 202 is of the opposite doping type to the substrate 201.

The embodiment of the present application does not limit the specific doping types of the carrier collection region 202 and the substrate 201. For example, in one implementation of the present application, the carrier collection region 202 and the first and second carrier storage regions FDA and FDB may be doped P-type, and the substrate 201 may be doped N-type.

Free electrons in the carrier collection region 202 diffuse into the substrate 201, holes in the substrate 201 diffuse into the carrier collection region 202, the diffused electrons and holes are contacted and recombined to be eliminated, and a PN junction depletion region 203 is formed at a position where the carrier collection region 202 is adjacent to the substrate 201. Charged ions are left adjacent to the interface in the regions where there are no mobile carriers, the uncompensated ions being positive on the substrate 201 side and negative on the carrier collection region 202 side, creating an electric field that provides a force opposing the continued exchange of charge carriers. The PN junction depletion region 203 reaches its equilibrium size when the electric field is sufficient to prevent further transfer of holes and electrons.

In another implementation manner of the present application, the carrier collection region 202 and the first carrier storage region FDA and the second carrier storage region FDB are doped N-type, the substrate 201 is doped P-type, holes in the carrier collection region 202 are diffused into the substrate 201, meanwhile, free electrons in the substrate 201 are diffused into the carrier collection region 202, the diffused electrons and holes are contacted and eliminated through recombination, and a PN junction depletion region 203 is also formed at a position where the carrier collection region 202 is adjacent to the substrate 201.

Wherein the doping concentration of the carrier collection region 202 may be greater than the doping concentration of the substrate 201. Illustratively, the doping concentration of the carrier collection region 202 is 1000-10000 times the doping concentration of the substrate 201. Electrons or holes are easily transferred from the high concentration region to the low concentration region until they are uniformly distributed, and therefore, in the process of forming the PN junction depletion region, electrons or holes of the carrier collection region 202 are more easily transferred into the substrate 201, and the formed PN junction depletion region 203 is also more biased toward the substrate 201.

As shown in fig. 7b, the PN junction depletion region 203 includes a first PN junction depletion region 2031 located in the substrate 201, and a second PN junction depletion region 2032 located in the carrier collection region 202, wherein the range of the first PN junction depletion region 2031 is greater than the range of the first PN junction depletion region 2032.

As shown in fig. 7c, when the substrate 201 is irradiated by light, carriers are generated inside the substrate 201, wherein ions on two sides of the PN junction depletion region 203 are opposite in electrical property, which generates a lateral electric field, and the PN junction depletion region 203 is located more in the substrate 201, so that the electric field has a greater effect on the carriers in the substrate 201, and the carriers in the substrate 201 enter the carrier collection region 202.

Referring next to fig. 7c, the carrier collection region 202 may be in contact with the first left modulation gate PGA and the first right modulation gate PGB on the first surface 2011. Carriers in the substrate 201 may flow toward the first surface 2011 under the modulation of the first left modulation gate PGA and the first right modulation gate PGB, and then flow toward the first carrier storage region FDA through the first left modulation gate PGA or flow toward the second carrier storage region FDB through the first right modulation gate PGB.

For example, in the time period a, the first left modulation gate PGA is turned on, the first right modulation gate PGB is turned off, and carriers in the substrate flow to the first surface of the substrate under the modulation of the first left modulation gate PGA, and then are stored to the FDA.

In the time period B, the first right modulation gate PGB is turned on, the first left modulation gate PGA is turned off, and carriers in the substrate flow to the first surface of the substrate under the modulation of the first right modulation gate PGB, and are then stored in the FDB.

Assuming that the number of carriers in the first carrier storage region FDA is Sa and the number of carriers in the second carrier storage region FDB is Sb, the modulation and demodulation efficiency of the pixel structure can be obtained by substituting Sa and Sb into formula 1.

Fig. 8 is a graph of potential inside a substrate as a function of substrate depth provided by an embodiment of the present application. As shown in fig. 8, the ordinate is the potential and the abscissa is the substrate depth, where the substrate depth is the vertical distance between each point in the substrate to the first surface 2011 of the substrate.

Line 01 is a curve of the substrate internal potential with the substrate depth in the prior art, and line 02 is a curve of the substrate internal potential with the substrate depth in the embodiment of the present application.

Compared with the prior art, the carrier concentration at the bottom of the substrate is low, the potential is gentle, and the potential change in the substrate is limited to a shallow region.

In the pixel structure provided by the embodiment of the application, a PN junction depletion region is formed at the adjacent position of the carrier collection region and the substrate. The doping concentration of the carrier collecting region is greater than that of the substrate, so that electrons or holes of the carrier collecting region are easier to diffuse into the substrate in the process of forming the PN junction depletion region, and the formed PN junction depletion region is more inclined to the substrate. Substrate ions on two sides of the PN junction depletion region are opposite in electric property, and an electric field is created. When the substrate is irradiated by light, carriers are generated in the substrate, the PN junction depletion region is more inclined to the substrate, so that electric fields on two sides of the PN junction depletion region have larger action on the carriers in the substrate, and the carriers in the substrate enter the carrier collection region under the action of the electric field of the PN junction depletion region. In the prior art, the carrier concentration at the bottom of the substrate is low, and the potential change is only limited in a shallow region from one surface to the inside, so that the speed of the carrier at the bottom of the substrate is low, and a long time is required for reaching a carrier collection point of the first surface, thereby affecting the modulation and demodulation efficiency of the pixel structure. The substrate potential changes from the first surface to the bottom of the substrate more uniformly, the carrier speed of the bottom of the substrate is improved, the carriers can be collected quickly, the modulation and demodulation efficiency of the pixel structure is improved, and the distance measurement precision is improved.

In some possible embodiments, as shown in fig. 7b, the pixel structure 2003 is a structure that is symmetrical to the left and right with respect to the center line O-O, and the first left modulation gate PGA and the first right modulation gate PGB, and the FDA and the FDB are symmetrical with respect to the center line O-O of the pixel structure 2003, so that the absorption capability of the FDA and the FDB for carriers in the substrate 201 can be the same.

The structure of the carrier collection region 202 is not limited in the embodiments of the present application. In one implementation of the present application, as shown in fig. 7b, the doping concentration of the carrier collection region 202 is single, and the doping concentration does not change in the first direction.

In another implementation manner of the present application, the doping concentration of the carrier collection region 202 exhibits a doping profile of "deep-shallow-deep" in the first direction, as shown in fig. 9, the carrier collection region 202 may include: a first doped region 2021, a second doped region 2022 and a third doped region 2023, wherein the first doped region 2021 and the second doped region 2022 are respectively located at two sides of the carrier collecting region 202 in the first direction, and the third doped region 2023 is located between the first doped region 2021 and the second doped region 2022.

The doping concentration of the first doped region 2021 and the doping concentration of the second doped region 2022 are greater than the doping concentration of the third doped region 2023.

Illustratively, the doping concentration of the first doping region 2021 is 10 to 100 times that of the third doping region 2023, and the doping concentration of the second doping region 2022 is 10 to 100 times that of the third doping region 2023.

When the carrier collecting region is doped with a single concentration and the pixel structure is reset, a local potential well is formed in the center of the carrier collecting region on the surface of the substrate, so that carriers in the center of the first surface are difficult to enter the carrier collecting region, and the resetting of the pixel structure is not facilitated.

If the carrier collecting region adopts a doping mode of 'thick-shallow-thick', when the pixel structure is reset, a local potential well cannot be formed in the center of the carrier collecting region on the surface of the substrate, which is beneficial to smoothly pumping away the carriers on the first surface of the substrate in the resetting process, so that the pixel structure is easier to reset.

The third doped region 2023 with the same doping type and a lower doping concentration is disposed in the carrier collecting region 202, so that the pixel structure can be reset more easily.

Referring to fig. 10, the substrate 201 is doped P-type, and the carrier collection region 202 is doped N-type.

Fig. 10 is a graph illustrating a potential distribution of the first surface of the substrate during resetting of the pixel structure according to the embodiment of the present disclosure. As shown in fig. 10, the ordinate is the potential and the abscissa is the substrate width. The substrate width may be a vertical distance from any point of the first surface of the substrate to the first carrier storage region.

When the substrate 201 is doped P-type and the carrier collection region 202 is doped N-type, the carriers reaching the first surface are electrons.

The line 04 is a doping pattern with a single concentration for the carrier collection region, and the potential distribution curve on the first surface 1011 of the substrate is shown when the pixel structure is reset. As shown by line 04, when the carrier collection region is doped with a single concentration, the potential at the middle position of the first surface is a region that is locally 'concave' in the opposite direction, and the carriers at the middle position cannot flow to both sides under the action of the applied electric field, so that the electrons at the middle position cannot be smoothly pumped away in the resetting process.

Line 03 is the plot of the potential distribution on the first surface 1011 of the substrate as the carrier collection region is "deep-shallow-deep" doped and the pixel structure is reset. As shown by a line 03, when the carrier collection region adopts a "thick-shallow-thick" doping manner, the potential at the middle position of the first surface is a locally "convex" region in the opposite direction, and the carriers at the middle position can flow to both sides under the action of an external electric field, so that electrons on the first surface of the substrate can be smoothly pumped away in the resetting process, and the pixel structure can be reset more easily.

In some possible embodiments, as shown in fig. 9, the first doped region 2021 and the second doped region 2022 are symmetric about a center line O-O of the pixel structure 2003, and the third doped region 2023 is symmetric about the center line O-O of the pixel structure 2003, so that when the first left modulation gate PGA and the first right modulation gate PGB are complementarily modulated, carriers in the substrate have the same ability to enter the first carrier storage region FDA and the second carrier storage region FDB.

The length of the carrier collection region 202 is not limited in the embodiments of the present application.

In one implementation of the present application, as shown in fig. 7b, the length of the carrier collection region 202 is equal to the length of the substrate 201 in the direction perpendicular to the first surface 2011. The length of the carrier collection region 202 may be a distance that the carrier collection region 202 extends from the first surface into the substrate along the Y-axis.

Referring next to fig. 7b, a carrier collection region 202 extends longitudinally through the substrate 201, and PN junction depletion regions 203 are located on the substrate on either side of the carrier collection region 202.

Therefore, PN junction depletion regions can be formed on the substrates on the two sides of the carrier collection region, carriers in the substrates on the two sides of the carrier collection region can flow into the carrier collection region under the action of an electric field of the PN junction depletion regions, and the modulation and demodulation efficiency of the pixel structure is improved.

In another implementation manner, in a direction perpendicular to the first surface 2011, the length of the carrier collection region 202 is smaller than the length of the substrate 201.

As shown in fig. 11, the substrate 201 forms a U-shaped doped region, and the carrier collection region 202 is located in the U-shaped doped region 203, wherein the opening of the U-shaped doped region faces the first surface 2011 of the doping structure.

The carrier collection region 202 and the U-shaped doped region are adjoined to form a U-shaped PN junction depletion region 203, and carriers of the U-shaped doped region flow from the U-shaped doped region to the carrier collection region under the action of the U-shaped PN junction depletion region 203.

Those skilled in the art can select the appropriate length of the carrier collection region 202 as desired, and such is within the scope of the present application.

The number of the first modulation gate and the second modulation gate and the positional relationship between the carrier collection region 202 and the modulation gates are not limited in the embodiments of the present application.

The first carrier storage region FDA may be close to the at least one first modulation gate and far from the at least one second modulation gate, and the second carrier storage region FDB may be close to the at least one second modulation gate and far from the at least one first modulation gate.

The at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, and the at least one first modulation gate includes a first end closest to the first carrier storage region FDA and a second end farthest from the first carrier storage region FDB.

Similarly, the at least one second modulation gate includes a first end closest to the second carrier storage region FDB and a second end farthest from the second carrier storage region FDB.

Wherein the first doped region is located between the first end and the second end of the at least one first modulation gate in the first direction, and the second doped region is located between the first end and the second end of the at least one second modulation gate in the first direction.

In one implementation of the present application, the first modulation gate and the second modulation gate are both one, and the first modulation gate and the second modulation gate are complementarily modulated.

As shown in fig. 7a, the first modulation gate includes: a first left modulation gate PGA, the second modulation gate including: the first right modulation gate PGB, the first left modulation gate PGA and the first right modulation gate PGB are sequentially disposed on the first surface 2011 along a first direction, and the carrier collection region is located below the first left modulation gate PGA and the first right modulation gate PGB, so that carriers in the carrier collection region can enter the first left modulation gate PGA or the first right modulation gate PGB through the first surface of the substrate.

In some possible embodiments, a single doping concentration is used for the carrier collection region 202.

The first left modulation gate PGA and the first right modulation gate PGB respectively include a first end and a second end opposite to each other, the first end of the first left modulation gate PGA is close to the first carrier storage region FDA, and the second end of the first left modulation gate PGA is far away from the first carrier storage region FDA. A first end of the first right modulation gate PGB is close to the second carrier storage region FDB, and a second end of the first right modulation gate PGB is far from the second carrier storage region FDB. A second end of the first left modulation gate PGA is opposite to a second end of the first right modulation gate PGB.

The first end of the at least one first modulation gate is a first end of a first left modulation gate PGA, and the second end of the at least one first modulation gate is a second end of the first left modulation gate PGA.

The first end of the at least one second modulation gate is a first end of a first right modulation gate PGB, and the second end of the at least one second modulation gate is a second end of the first right modulation gate PGB.

The carrier collection region 202 and the at least one first modulation gate and the at least one second modulation gate are in contact with the first surface 2011, which means that the carrier collection region 202 and each of the first modulation gate and each of the second modulation gate are in contact with the first surface.

The first interface of the carrier collection region 202 may be located between the first and second ends of the first left modulation gate PGA. Wherein the first interface of the carrier collection region 202 is close to the first carrier storage region FDA.

Therefore, the carrier collection region 202 and the first left modulation gate PGA are in contact with the first surface 2011, and a distance for regulating carriers entering the first left modulation gate PGA can be reserved between the first carrier storage region FDA and the first interface of the carrier collection region, so that the carriers entering the first left modulation gate PGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate PGA.

The second interface of the carrier collection region 202 may be located between the first and second ends of the first right modulation gate PGB. Wherein the second interface of the carrier collection region 202 is close to the second carrier storage region FDB.

Therefore, the carrier collection region 202 and the first right modulation gate PGB can be in contact with the first surface 2011, and a distance for regulating and controlling carriers entering the first right modulation gate PGB can be reserved between the second carrier storage region FDB and a second interface of the carrier collection region, so that the carriers entering the first right modulation gate PGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate PGB.

In other possible embodiments of the present application, the carrier-collection region 202 exhibits a "deep-shallow-deep" doping profile in the first direction. As shown in fig. 9, the carrier collection region 202 includes: a first doped region 2021, a second doped region 2022, and a third doped region 2023.

A first interface of the first doped region 2021 may not exceed the first end of the first left modulation gate PGA, wherein the first interface of the first doped region 2021 is close to the first carrier storage region FDA.

Therefore, the first doped region 2021 and the first left modulation gate PGA can be in contact with the first surface 2011, and a distance for regulating and controlling carriers entering the first left modulation gate PGA can be left between the first carrier storage region FDA and the first interface of the first doped region 2021, so that the carriers entering the first left modulation gate PGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate PGA.

The first interface of the second doped region 2022 may be no more than the first end of the first right modulation gate PGB, and the first interface of the second doped region 2022 is close to the second carrier storage region FDB.

Therefore, the second doped region 2022 may contact the first right modulation gate PGB on the first surface, and a distance for adjusting carriers entering the first right modulation gate PGB can be left between the second carrier storage region FDB and the first interface of the second doped region 2022, so that the carriers entering the first right modulation gate PGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate PGB.

A second interface of the first doped region 2021 may not exceed the second end of the first left modulation gate PGA, wherein the second interface of the first doped region 2021 is an interface between the second doped region 2022 and the third doped region 2023.

Therefore, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 may contact the first left modulation gate PGA and the first surface, so that carriers in the third doped region 2023 may enter the first left modulation gate PGA through the first surface, and a distance for adjusting the carriers entering the first left modulation gate PGA is reserved, so that the carriers entering the first left modulation gate PGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate PGA.

A second interface of the second doped region 2022 may not exceed the second end of the first right modulation gate PGB, wherein the second interface of the second doped region 2022 is an interface between the second doped region 2022 and the third doped region 2023.

Therefore, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 may contact the first right modulation gate PGB at the first surface, so that carriers in the third doped region 2023 may enter the first right modulation gate PGB through the first surface, and a distance for adjusting the carriers entering the first right modulation gate PGB is reserved, so that the carriers entering the first right modulation gate PGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate PGB.

In another implementation of the present application, the first modulation gate and the second modulation gate are plural. Illustratively, as shown, the first modulation gate includes: a first left modulation gate TGA and a second left modulation gate PGA in series. The second modulation gate includes: a first right modulation gate TGB and a second right modulation gate PGB connected in series. The first left and right modulation gates TGA and TGB are complementarily modulated, and the second left and right modulation gates PGA and PGB are complementarily modulated. That is, when the first left modulation gate PGA is turned on, the first right modulation gate PGB is turned off, and when the first right modulation gate PGB is turned on, the first left modulation gate PGA is turned off. Meanwhile, when the first right modulation gate PGA is turned on, the second right modulation gate PGB is turned off, and when the second right modulation gate PGB is turned on, the first right modulation gate PGA is turned off.

For example, in the time period a, the first left modulation gate TGA and the second left modulation gate PGA are turned on, and the first right modulation gate TGB and the second right modulation gate PGB are turned off.

During other time periods other than the time period a, for example, during the time period B, the first right modulation gate TGB and the second right modulation gate PGB are turned on, and the first left modulation gate TGA and the second left modulation gate PGA are turned off.

Note that "TG" is an english abbreviation of turbo gate (acceleration modulation diode).

The first left modulation gate TGA, the second left modulation gate PGA, the second right modulation gate PGB, and the first right modulation gate TGB are sequentially disposed on the first surface 2011 of the substrate 201 along a first direction, and the first left modulation gate TGA, the second left modulation gate PGA, the first right modulation gate TGB, and the second right modulation gate PGB are all in contact with the carrier collection region 202 on the first surface 2011, so that carriers in the carrier collection region can enter the first left modulation gate TGA, the second left modulation gate PGA, the first right modulation gate TGB, and the second right modulation gate PGB through the first surface.

In some possible embodiments, as shown in fig. 12a, the carrier collection region 202 employs a single doping concentration.

In fig. 12a, the first left modulation gate TGA, the second left modulation gate PGA, the first right modulation gate TGB and the second right modulation gate PGB respectively include opposite first and second ends, the first end of the first left modulation gate TGA is close to the first carrier storage region FDA, the second end of the first left modulation gate TGA is far from the first carrier storage region FDA, and the second end of the first left modulation gate TGA is opposite to the first end of the second left modulation gate PGA. A first end of the first right modulation gate TGB is close to the second carrier storage region FDB, a second end of the first right modulation gate TGB is far from the second carrier storage region FDB, and the second end of the first right modulation gate TGB is opposite to the first end of the second right modulation gate PGB. A second end of the second left modulation gate PGA is close to a second end of the second right modulation gate PGB.

The first end of the at least one first modulation gate is a first end of a first left modulation gate TGA, and the second end of the at least one first modulation gate is a second end of a second left modulation gate PGA.

The first terminal of the at least one second modulation gate is a first terminal of a first right modulation gate TGB, and the second terminal of the at least one second modulation gate is a second terminal of a second right modulation gate PGB.

The first interface of the carrier collection region 202 may be located between the first end and the second end of the first left modulation gate TGA.

Therefore, the carrier collection region 202 and the first left modulation gate TGA can be in contact with the first surface 2011, and a distance for regulating carriers entering the first left modulation gate TGA can be reserved between the first carrier storage region FDA and the first interface of the carrier collection region, so that the carriers entering the first left modulation gate TGA flow to the first carrier storage region FDA.

The second interface of the carrier collection region 202 may be located between the first and second ends of the first right modulation gate TGB.

Thus, the carrier collection region 202 and the first right modulation gate TGB can be in contact with the first surface 2011, and a distance for regulating carriers entering the first right modulation gate TGB can be reserved between the second carrier storage region FDB and the second interface of the carrier collection region, so that the carriers entering the first right modulation gate TGB flow to the second carrier storage region FDB.

In some other possible embodiments of the present application, the carrier collection region 202 exhibits a "deep-shallow-deep" doping profile in the first direction. As shown in fig. 12b, the carrier collection region 202 includes: a first doped region 2021, a second doped region 2022 and a third doped region 2023 sequentially arranged along the first direction.

The first interface of the first doped region 2021 may not exceed the first end of the first left modulation gate TGA.

Therefore, the first doped region 2021 may contact the first left modulation gate TGA on the first surface, and a distance for controlling carriers entering the first left modulation gate TGA is left between the first carrier storage region FDA and the first interface of the first doped region 2021, so that the carriers entering the first left modulation gate TGA flow to the first carrier storage region FDA under the modulation of the first left modulation gate TGA.

The first interface of the second doped region 2022 may not exceed the first end of the first right modulation gate TGB.

Therefore, the second doped region 2022 can contact the first right modulation gate TGB on the first surface, and a distance for controlling carriers entering the first right modulation gate TGB can be left between the second carrier storage region FDB and the first interface of the second doped region 2022, so that the carriers entering the first right modulation gate TGB flow to the second carrier storage region FDB under the modulation of the first right modulation gate TGB.

The second interface of the first doped region 2021 may not exceed the second end of the second left modulation gate PGA.

Thus, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 may contact the second left modulation gate PGA and the first surface, so that carriers in the third doped region 2023 may enter the second left modulation gate PGA through the first surface, and at the same time, a distance for regulating carriers entering the second right modulation gate PGB is reserved, so that carriers entering the second right modulation gate PGB flow to the first carrier storage region FDA.

The second interface of the second doped region 2022 may not exceed the second end of the second right modulation gate PGB.

Therefore, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 may contact the second right modulation gate PGB at the first surface, so that carriers in the third doped region 2023 may enter the second right modulation gate PGB through the first surface, and a distance for regulating the carriers entering the second right modulation gate PGB is reserved, so that the carriers entering the second right modulation gate PGB flow to the second carrier storage region FDB.

For another example, as shown in fig. 13a, the number of first modulation gates is 3: first left modulation gate TGA1, second left modulation gate TGA2, and third left modulation gate PGA, the second modulation gate is also 3: a first right modulation gate TGB1, a second right modulation gate TGB2, and a third right modulation gate PGB.

The first left modulation gate TGA1 and the first right modulation gate TGB1 are complementarily modulated, the second left modulation gate TGA2 and the second right modulation gate TGB2 are complementarily modulated, and the third left modulation gate PGA and the third right modulation gate PGB are complementarily modulated. That is, when the first left modulation gate TGA1 is turned on, the first right modulation gate TGB1 is turned off, and when the first right modulation gate TGB1 is turned on, the first left modulation gate TGA1 is turned off. When the second left modulation gate TGA2 is turned on, the second right modulation gate TGB2 is turned off, and when the second right modulation gate TGB2 is turned on, the second left modulation gate TGA2 is turned off. Meanwhile, when the third left modulation gate PGA is turned on, the third right modulation gate PGB is turned off, and when the third right modulation gate PGB is turned on, the third left modulation gate PGA is turned off.

For example, during the time period a, the first left modulation gate TGA1, the second left modulation gate TGA2, and the third left modulation gate PGA are turned on, and the first right modulation gate TGB1, the second right modulation gate TGB2, and the third right modulation gate PGB are turned off.

During other time periods outside the time period a, for example, during the time period B, the first right modulation gate TGB1, the second right modulation gate TGB2 and the third right modulation gate PGB are turned on, and the first left modulation gate TGA1, the second left modulation gate TGA2 and the third left modulation gate PGA are turned off.

The first left modulation gate TGA1, the second left modulation gate TGA2, the third left modulation gate PGA, the third right modulation gate PGB, the second right modulation gate TGB2 and the first right modulation gate TGB1 may be sequentially disposed on the first surface 2011 of the substrate 201 along the first direction, and the first left modulation gate TGA1, the second left modulation gate TGA2, the third left modulation gate PGA, the third right modulation gate PGB, the second right modulation gate TGB2 and the first right modulation gate TGB1 are all in contact with the carrier collection region 202 on the first surface 2011.

As shown in fig. 13a, the first left modulation gate TGA1, the second left modulation gate TGA2, the third left modulation gate PGA, the third right modulation gate PGB, the second right modulation gate TGB2 and the first right modulation gate TGB1 respectively include opposite first and second ends, the first end of the first left modulation gate TGA1 is close to the first carrier storage region FDA, the second end of the first left modulation gate TGA1 is opposite to the first end of the second left modulation gate TGA2, and the second end of the second left modulation gate TGA2 is opposite to the first end of the third left modulation gate PGA. A second end of the third left modulation gate PGA is opposite to a second end of the third right modulation gate PGB. A first end of the first right modulation gate TGB1 is close to the second carrier storage region FDB, a second end of the first right modulation gate TGB1 is opposite to a first end of the second right modulation gate TGB2, and a second end of the second right modulation gate TGB2 is opposite to a first end of the third right modulation gate PGB.

The first end of the at least one first modulation gate is a first end of the first left modulation gate TGA1, and the second end of the at least one first modulation gate is a second end of the third left modulation gate PGA.

The first terminal of the at least one second modulation gate is a first terminal of a first right modulation gate TGB1, and the second terminal of the at least one second modulation gate is a second terminal of a third right modulation gate PGB.

The carrier-collection region 202 in fig. 13a may employ a single doping concentration.

A first interface of the carrier collection region 202 may be located between the first end and the second end of the first left modulation gate TGA 1.

Therefore, the carrier collection region 202 and the first left modulation gate TGA1 can be in contact with the first surface 2011, and a distance for regulating carriers entering the first left modulation gate TGA1 can be left between the first carrier storage region FDA and the first interface of the carrier collection region, so that the carriers entering the first left modulation gate TGA1 flow to the first carrier storage region FDA.

A second interface of the carrier collection region 202 may be located between the first and second ends of the first right modulation gate TGB 1.

Thus, the carrier collection region 202 and the first right modulation gate TGB1 can be brought into contact with the first surface 2011, and a distance for regulating carriers entering the first right modulation gate TGB1 can be left between the second carrier storage region FDB and the second interface of the carrier collection region, so that carriers entering the first right modulation gate TGB1 flow to the second carrier storage region FDB.

In some other possible embodiments of the present application, the carrier collection region 202 exhibits a "deep-shallow-deep" doping profile in the first direction. As shown in fig. 13b, the carrier collection region 202 includes: a first doped region 2021, a second doped region 2022 and a third doped region 2023 sequentially arranged along the first direction.

The first interface of the first doped region 2021 may not exceed the first end of the first left modulation gate TGA 1.

Therefore, the first doped region 2021 may contact the first left modulation gate TGA1 on the first surface, and a distance for controlling carriers entering the first left modulation gate TGA1 is left between the first carrier storage region FDA and the first interface of the first doped region 2021, so that the carriers entering the first left modulation gate TGA1 flow to the first carrier storage region FDA under the modulation of the first left modulation gate TGA 1.

The first interface of the second doped region 2022 may not exceed the first end of the first right modulation gate TGB 1.

Therefore, the second doped region 2022 can contact the first right modulation gate TGB1 on the first surface, and a distance for adjusting carriers entering the first right modulation gate TGB1 can be left between the second carrier storage region FDB and the first interface of the second doped region 2022, so that the carriers entering the first right modulation gate TGB1 flow to the second carrier storage region FDB under the modulation of the first right modulation gate TGB 1.

The second interface of the first doped region 2021 may not exceed the second end of the third left modulation gate PGA.

Therefore, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 may contact the third left modulation gate PGA at the first surface, so that carriers in the third doped region 2023 may enter the third left modulation gate PGA through the first surface, and a distance for regulating the carriers entering the third left modulation gate PGA is reserved, so that the carriers entering the third left modulation gate PGA flow to the first carrier storage region FDA.

The second interface of the second doped region 2022 may not exceed the second end of the third right modulation gate PGB.

Therefore, the third doped region 2023 located between the first doped region 2021 and the second doped region 2022 may contact the third right modulation gate PGB at the first surface, so that carriers in the third doped region 2023 may enter the third right modulation gate PGB through the first surface, and a distance for regulating the carriers entering the third right modulation gate PGB is reserved, so that the carriers entering the third right modulation gate PGB flow to the second carrier storage region FDB.

In addition, a first gate is arranged between the at least one first modulation gate and the first carrier storage region FDA, and a second gate is arranged between the at least one second modulation gate and the second carrier storage region FDB.

As shown in fig. 14, the first modulation gate is 2: first left modulation gate TGA and second left modulation gate third left modulation gate PGA in series. The second modulation gate is also 2: first right modulation gate TGB and second right modulation gate third right modulation gate PGB connected in series. The first gate is TXA and the second gate is TXB.

The first and second gates TXA and TXB may be symmetrical with respect to a center line O-O of the pixel structure 2003.

Thereby, the carriers in the substrate are made to have the same ability to enter the first carrier storage region FDA and the second carrier storage region FDB.

The at least one first modulation gate is coupled to the carrier collection region 202 at one end and connected to the first carrier storage region FDA through a first gate TXA at the other end, and carriers in the carrier collection region 202 may pass through the first modulation gate and the first gate TXA in sequence to reach the FDA.

The at least one second modulation gate is coupled to the carrier collection region 202 at one end and coupled to the second carrier storage region FDB through the second gate TXB at the other end, and carriers in the carrier collection region 202 may sequentially pass through the second modulation gate and the second gate TXB to reach the FDB.

The TXA and the TXB are used for receiving direct current modulation signals. In this case, the first gate TXA and the second gate TXB may be always in a conductive state during the above-described period a and period B.

Thus, the dc signal received by the first gate TXA may shield the ac signal received by the at least one first modulation gate from the influence of the ac signal on the first carrier storage region FDA.

Similarly, the dc signal received by the second gate TXB may shield the ac signal received by the at least one second modulation gate from the second carrier storage region FDB.

In addition, by adjusting the voltage value of the first gate, the steepness of the potential distribution between the first carrier storage region FDA and the first modulation gate can be increased, which is favorable for the carriers in the substrate to flow into the first carrier storage region FDA. By adjusting the voltage value of the second gate, the degree of steepness of the potential distribution between the second carrier storage region FDB and the second modulation gate can be increased, facilitating the flow of carriers in the substrate into the second carrier storage region FDB.

The embodiment of the present application provides a method for manufacturing a pixel structure, and fig. 15 is a flowchart of the method for manufacturing the pixel structure according to the embodiment of the present application. As shown in fig. 15, the method includes the steps of:

s101, as shown in fig. 15a, two carrier storage regions are formed on the substrate 201 by ion implantation.

Wherein the first surface may be any one of the surfaces of the substrate 201. The two carrier storage regions are respectively located on two sides of the substrate 201 in a first direction, which is a direction parallel to the first surface 2011.

A mask may be provided on the first surface 1011 of the substrate before ion implantation. The mask plate may be disposed in the middle of the first surface 1011 to leave regions for ion implantation on both sides of the first surface 1011, and the ion implantation may be performed in the regions to change the doping type of the regions, so as to obtain the carrier storage region.

After ion implantation is finished, the mask plate can be removed.

Wherein the doping types of the two carrier storage regions are opposite to the doping type of the substrate 201.

Illustratively, the two carrier storage regions are doped N-type and the substrate is doped P-type, or the two carrier storage regions are doped P-type and the substrate is doped N-type.

S102, as shown in fig. 15b, a carrier collection region 202 is formed on the substrate 201 by ion implantation.

Wherein the carrier collection region 202 is located between the two carrier storage regions in the first direction, the doping concentration of the carrier collection region 202 is greater than the doping concentration of the substrate 201, the doping types of the carrier collection region 202 and the two carrier storage regions are the same, and the doping type of the carrier collection region 202 and the doping type of the substrate 201 are opposite.

Before ion implantation, a mask plate may be disposed on each side of the first surface 1011 of the substrate to leave a region for ion implantation in the middle of the first surface 1011, and ion implantation may be performed in the region to change the doping type of the region, so as to obtain the carrier collection region 202.

After ion implantation is finished, the mask plate can be removed.

The depth of ion implantation can be adjusted by controlling the ion energy, and the length of the carrier collection region can be adjusted. In one implementation of the present application, a length of the carrier collection region in a direction perpendicular to the first surface is less than a length of the substrate, and in another implementation of the present application, the length of the carrier collection region is equal to the length of the substrate.

Thereby, the carrier collection region 202 of a single concentration can be formed.

As shown in fig. 16, in one implementation manner of the present application, the step S102 of forming a carrier collection region 202 on the substrate 201 by ion implantation may include the following steps:

s1021, as shown in fig. 16a, a first doped region 2021 and a second doped region 2022 are formed on the substrate 201 by ion implantation.

The first doped region 2021 and the second doped region 2022 are respectively located at two sides of the carrier collecting region 202 in the first direction.

Before the ion implantation, three masks may be disposed on the first surface 1011 of the substrate to leave an area for the ion implantation on the first surface 1011, and the ion implantation may be performed on the area to change the doping type of the area, resulting in the first doped area 2021 and the second doped area 2022.

After ion implantation is finished, the mask plate can be removed.

S1022, as shown in fig. 16b, a third doped region 2023 is formed on the substrate 201 by ion implantation.

Wherein the doping concentration of the first doped region 2021 and the second doped region 2022 are both greater than the doping concentration of the third doped region 2023, and the third doped region 2023 is located between the first doped region 2021 and the second doped region 2022.

Before ion implantation, 2 masks may be disposed on the first surface 1011 of the substrate, and an area for ion implantation may be left on the first surface 1011, and ion implantation may be performed in the area to change the doping type of the area, so as to obtain the third doped region 2023.

After ion implantation is finished, the mask plate can be removed.

Thus, a carrier collection region having a "thick-shallow-thick" distribution of doping concentration in the first direction can be obtained.

As shown in fig. 17, in another implementation manner of the present application, the step S102 of forming a carrier collection region 202 on the substrate 201 by ion implantation may include the following steps:

s1023, as shown in fig. 16a, a first doped region 2021 and a second doped region 2022 are formed on the substrate 201 by ion implantation.

The doping method of the first doping region and the second doping region can refer to the above S1021, and is not described herein again.

S1024, as shown in fig. 16b, ions of the first doped region 2021 and the second doped region 2022 are diffused to the third region to form a third doped region 2023.

The doping concentration of the first doped region 2021 and the doping concentration of the second doped region 2022 are both greater than the doping concentration of the third doped region 2023, and the third doped region 2023 is located between the first doped region 2021 and the second doped region 2022.

Therefore, compared with step S1022, it is not necessary to perform a mask and ion implantation, which is advantageous to simplify the manufacturing process.

S103, as shown in fig. 15c, at least one first modulation gate and at least one second modulation gate are disposed on the first surface 2011 of the substrate 201.

As shown in fig. 15, the first modulation gate includes: a first left modulation gate PGA, the second modulation gate including: a first right modulation gate PGB.

The first left modulation gate PGA and the first right modulation gate PGB are complementarily modulated, respectively, and the carrier collection region 202 and the first left modulation gate PGA and the first right modulation gate PGB contact the first surface 2011.

In one implementation of the present application, the carrier collection region 202 has a single doping concentration.

The disposing of at least one first modulation gate and at least one second modulation gate on the first surface 2011 of the substrate 201 includes:

the at least one first modulation gate and the at least one second modulation gate are arranged on the first surface 2011 along the first direction such that the carrier collection region 202 is located between a first end of the at least one first modulation gate and a first end of the at least one second modulation gate in the first direction.

In another implementation of the present application, the carrier collection region 202 includes: a first doped region 2021, a second doped region 2022, and a third doped region 2023.

the at least one first modulation gate and the at least one second modulation gate are arranged on the first surface 2011 along the first direction such that the first doped region 2021 is located between a first end and a second end of the at least one first modulation gate in the first direction and such that the second doped region 2022 is located between a first end and a second end of the at least one second modulation gate in the first direction.

As shown in fig. 18, in another implementation manner of the present application, the method further includes:

s104, as shown in fig. 18a, a first gate is disposed between the at least one first modulation gate and the first carrier storage region FDA, and a second gate is disposed between the at least one second modulation gate and the second carrier storage region FDB.

The first modulation grid and the second modulation grid are used for receiving alternating current modulation signals, and the first grid and the second grid are used for receiving direct current modulation signals.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A pixel structure, comprising:

a modulation gate set comprising:

the first modulation grid electrodes are respectively and sequentially arranged on the first surface of the substrate;

at least one second modulation grid electrode is respectively and sequentially arranged on the first surface, and the at least one second modulation grid electrode and the at least one first modulation grid electrode are respectively subjected to complementary modulation;

and

the substrate includes:

at least two carrier storage regions, the at least two carrier storage regions comprising: a first carrier storage region and a second carrier storage region respectively located on both sides of the substrate in a first direction, the first direction being a direction parallel to the first surface; and

and a carrier collection region located between the first carrier storage region and the second carrier storage region in the first direction and contacting the modulation gate group on the first surface, wherein a doping concentration of the carrier collection region is greater than a doping concentration of the substrate, the carrier collection region has a same doping type as the at least two carrier storage regions, and the carrier collection region has a doping type opposite to that of the substrate.
The pixel structure of claim 1, wherein the carrier collection region comprises:

a first doped region and a second doped region respectively located at both sides of the carrier collection region in the first direction; and

and the third doping area is positioned between the first doping area and the second doping area, wherein the doping concentration of the first doping area and the doping concentration of the second doping area are both greater than that of the third doping area.
The pixel structure of claim 2, wherein the first carrier storage region is proximate to the at least one first modulation gate and distal to the at least one second modulation gate, and the second carrier storage region is proximate to the at least one second modulation gate and distal to the at least one first modulation gate, wherein:

the at least one first modulation gate and the at least one second modulation gate are arranged on the first surface along the first direction, the at least one first modulation gate comprises a first end closest to the first carrier storage region and a second end farthest from the first carrier storage region, and the at least one second modulation gate comprises a first end closest to the second carrier storage region and a second end farthest from the second carrier storage region;

wherein the first doped region is located between the first and second ends of the at least one first modulation gate in the first direction, and the second doped region is located between the first and second ends of the at least one second modulation gate in the first direction.
The pixel structure of claim 2 or 3, wherein the first doped region has a doping concentration 10-100 times that of the third doped region, and wherein the second doped region has a doping concentration 10-100 times that of the third doped region.
The pixel structure of any of claims 2-4, wherein the first doped region and the second doped region are symmetrically disposed about a first axis, and the third doped region is symmetrical about the first axis, wherein the first axis is perpendicular to the first surface.
The pixel structure of claim 1, wherein the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction, the first carrier storage region is proximate to the at least one first modulation gate and distal to the at least one second modulation gate, the second carrier storage region is proximate to the at least one second modulation gate and distal to the at least one first modulation gate, wherein:

the at least one first modulation gate comprises a first end closest to the first carrier storage region and a second end farthest from the first carrier storage region, and the at least one second modulation gate comprises a first end closest to the second carrier storage region and a second end farthest from the second carrier storage region;

wherein the carrier collection region is located between the first end of the at least one first modulation gate and the first end of the at least one second modulation gate in the first direction.
The pixel structure according to any of claims 1 to 6, wherein the carrier collection region length is equal to the length of the substrate in a direction perpendicular to the first surface.
The pixel structure of any of claims 1 to 6, wherein the carrier-collection region length is less than the length of the substrate in a direction perpendicular to the first surface.
The pixel structure according to any of claims 1 to 8, wherein the carrier storage region comprises: a first carrier storage region proximate the at least one first modulation gate and a second carrier storage region proximate the at least one second modulation gate;

a first grid is arranged between the at least one first modulation grid and the first carrier storage region, and a second grid is arranged between the at least one second modulation grid and the second carrier storage region;

wherein the at least one first modulation gate and the at least one second modulation gate are configured to receive an ac modulation signal, and the first gate and the second gate are configured to receive a dc modulation signal.
The pixel structure of any of claims 1-9, wherein the doping concentration of the carrier-collecting region is 1000-10000 times the doping concentration of the substrate.
The pixel structure according to any of claims 1 to 10, wherein the carrier-collecting region is doped P-type, the substrate is doped N-type;

or the carrier collecting region is doped in an N type, and the substrate is doped in a P type.
The pixel structure of any of claims 1-11, wherein the set of modulation gates further comprises:

at least one third modulation grid electrode which is respectively arranged on the first surface of the substrate in sequence;

at least one fourth modulation grid which is respectively and sequentially arranged on the first surface, wherein the at least one first modulation grid, the at least one second modulation grid, the at least one third modulation grid and the at least one fourth modulation grid are respectively subjected to complementary modulation;

the first and second modulation gates are symmetric about a center of the first surface, and the third and fourth modulation gates are symmetric about the center of the first surface;

the at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region respectively located on two sides of the substrate in a second direction, wherein the second direction is parallel to the first surface and is perpendicular to the first direction;

the carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction.
A method of fabricating a pixel structure, the method comprising:

forming at least two carrier storage regions on a substrate by ion implantation, wherein the at least two carrier storage regions comprise: the first carrier storage region and the second carrier storage region are respectively positioned on two sides of the substrate in a first direction, and the first direction is a direction parallel to the first surface of the substrate;

forming a carrier collection region on the substrate by ion implantation; wherein the carrier collection region is located between the first carrier storage region and the second carrier storage region in the first direction, the doping concentration of the carrier collection region is greater than the doping concentration of the substrate, the doping types of the carrier collection region and the at least two carrier storage regions are the same, and the doping types of the carrier collection region and the substrate are opposite;

providing a set of modulation gates on a first surface of the substrate, wherein the set of modulation gates comprises: at least one first modulation gate and at least one second modulation gate; the at least one second modulation gate and the at least one first modulation gate are complementarily modulated, respectively, and the carrier collection region and the modulation gate group are in contact with the first surface.
The method of manufacturing a pixel structure of claim 13, wherein the first carrier storage region is proximate to the at least one first modulation gate and distal to the at least one second modulation gate, and the second carrier storage region is proximate to the at least one second modulation gate and distal to the at least one first modulation gate, wherein:

the at least one first modulation gate comprises a first end closest to the first carrier storage region and a second end farthest from the first carrier storage region, and the at least one second modulation gate comprises a first end closest to the second carrier storage region and a second end farthest from the second carrier storage region;

the disposing at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes:

the at least one first modulation gate and the at least one second modulation gate are disposed on the first surface along the first direction such that the carrier collection region is located between a first end of the at least one first modulation gate and a first end of the at least one second modulation gate in the first direction.
The method of manufacturing a pixel structure according to claim 13 or 14,

the forming a carrier collection region on a substrate by ion implantation includes:

forming a first doped region and a second doped region on the substrate by ion implantation; wherein the first doped region and the second doped region are respectively located at two sides of the carrier collection region in the first direction;

and forming a third doped region on the substrate by ion implantation, wherein the doping concentration of the first doped region and the second doped region is greater than that of the third doped region, and the third doped region is positioned between the first doped region and the second doped region.
The method of manufacturing a pixel structure according to claim 13 or 14,

the forming a carrier collection region on a substrate by ion implantation includes:

forming a first doped region and a second doped region on the substrate by ion implantation; wherein the first doped region and the second doped region are respectively located at two sides of the carrier collection region in the first direction;

and ions of the first doping area and the second doping area are diffused to a third area to form a third doping area, wherein the doping concentration of the first doping area and the doping concentration of the second doping area are both greater than that of the third doping area, and the third doping area is positioned between the first doping area and the second doping area.
The method of manufacturing a pixel structure according to claim 15 or 16, wherein the first carrier storage region is proximate to the at least one first modulation gate and distal to the at least one second modulation gate, and the second carrier storage region is proximate to the at least one second modulation gate and distal to the at least one first modulation gate, wherein:

the at least one first modulation gate comprises a first end closest to the first carrier storage region and a second end farthest from the first carrier storage region, and the at least one second modulation gate comprises a first end closest to the second carrier storage region and a second end farthest from the second carrier storage region;

the providing at least one first modulation gate and at least one second modulation gate on the first surface of the substrate includes:

disposing the at least one first modulation gate and the at least one second modulation gate on the first surface along the first direction such that the first doped region is located between a first end and a second end of the at least one first modulation gate in the first direction and such that the second doped region is located between a first end and a second end of the at least one second modulation gate in the first direction.
The method for manufacturing a pixel structure according to any one of claims 15 to 17, wherein a doping concentration of the first doping region is 10 to 100 times a doping concentration of the third doping region, and a doping concentration of the second doping region is 10 to 100 times the doping concentration of the third doping region.
The method of any of claims 15-18, wherein the first doped region and the second doped region are symmetrically disposed about a first axis, and the third doped region is symmetrical about the first axis, wherein the first axis is perpendicular to the first surface.
A method of fabricating a pixel structure according to any one of claims 13-19, wherein the length of the carrier collection region in a direction perpendicular to the first surface is less than or equal to the length of the substrate.
A method of fabricating a pixel structure according to any of claims 14-20, wherein the at least two carrier storage regions comprise: a first carrier storage region proximate the at least one first modulation gate, and a second carrier storage region proximate the at least one second modulation gate, the method further comprising:

providing a first gate between the at least one first modulation gate and the first carrier storage region;

disposing a second gate between the at least one second modulation gate and the second carrier storage region; the first modulation grid and the second modulation grid are used for receiving alternating current modulation signals, and the first grid and the second grid are used for receiving direct current modulation signals.
The method as claimed in any one of claims 13-21, wherein the doping concentration of the carrier collection region is 1000-10000 times the doping concentration of the substrate.
A method of fabricating a pixel structure according to any of claims 13 to 22, wherein the carrier-collecting region is doped P-type, the substrate is doped N-type;

or the carrier collecting region is doped in an N type, and the substrate is doped in a P type.
A method of fabricating a pixel structure according to any one of claims 13 to 23, wherein the modulation gate group further comprises:

at least one third modulation grid electrode which is respectively arranged on the first surface of the substrate in sequence;

at least one fourth modulation grid which is respectively and sequentially arranged on the first surface, wherein the at least one first modulation grid, the at least one second modulation grid, the at least one third modulation grid and the at least one fourth modulation grid are respectively subjected to complementary modulation;

the first and second modulation gates are symmetric about a center of the first surface, and the third and fourth modulation gates are symmetric about the center of the first surface;

the at least two carrier storage regions further include: a third carrier storage region and a fourth carrier storage region respectively located on two sides of the substrate in a second direction, wherein the second direction is parallel to the first surface and is perpendicular to the first direction;

the carrier collection region is located between the third carrier storage region and the fourth carrier storage region in the second direction.