CN114283755A

CN114283755A - Display control module, display control method and display device

Info

Publication number: CN114283755A
Application number: CN202111598714.3A
Authority: CN
Inventors: 韩鹏; 何惠东; 姜倩文; 石娟娟; 杜伟华; 张�浩; 陈丽莉
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2022-04-05
Anticipated expiration: 2041-12-24
Also published as: CN114283755B

Abstract

The invention provides a display control module, a display control method and a display device. The display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit; the gazing point calculation module calculates gazing direction information; the high-definition display area calculation module is used for calculating the high-definition display area of the display panel; the time sequence control module generates a grid line driving time sequence, a data line gating control signal and a data voltage supply control signal according to the high-definition display area; the data voltage supply circuit controls to supply high-definition data voltage or low-definition data voltage to the corresponding row data line; the gating circuit controls communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit so as to provide the data voltage for the corresponding column pixel circuit through the corresponding column data line. The invention can reduce the power consumption while ensuring the display effect.

Description

Display control module, display control method and display device

Technical Field

The present invention relates to the field of technologies, and in particular, to a display control module, a display control method, and a display device.

Background

In the display industry, in order to meet the requirements of people, along with continuous innovation of the technology, the display definition and the refresh rate are continuously broken through, but the high definition inevitably brings great increase of energy consumption, higher energy support is needed, the frequency and the number of components are multiplied, and higher power support is needed. However, when the human eyes watch anything, the human eyes only pay attention to the focused region, the focused region is a very small part of the whole display picture, most of the rest of the display pictures are obtained by the human eyes only by using the residual light, and the image information obtained by the residual light is only approximate image information, so that the waste of resources is caused if the image information is high-definition or not.

Disclosure of Invention

The invention mainly aims to provide a display control module, a display control method and a display device, and solves the problem that the power consumption cannot be reduced while the display effect cannot be ensured in the prior art.

In order to achieve the above object, an embodiment of the present invention provides a display control module, which is applied to a display device, where the display device includes a display panel and a gate scanning module, and the display panel includes a plurality of rows and columns of pixel circuits, a plurality of rows of gate lines, and a plurality of columns of data lines; the display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit;

the fixation point calculating module is used for calculating fixation direction information according to the obtained eyeball image;

the high-definition display area calculation module is used for calculating a high-definition display area of the display panel according to the gazing direction information;

the image low-definition processing module is used for acquiring image information to be displayed and performing low-definition processing on the image information to be displayed in other display areas except the high-definition display area of the display panel to obtain low-definition image information;

the time sequence control module is used for generating a grid line driving time sequence, a data line gating control signal and a data voltage supply control signal according to the high-definition display area, providing the grid line driving time sequence to the grid scanning module, providing the data line gating control signal to the gating circuit and providing the data control signal to the data voltage supply circuit;

the grid scanning module is used for providing corresponding grid driving signals for the plurality of rows of grid lines according to the grid scanning time sequence;

the data voltage providing circuit is used for receiving the low-definition image information and high-definition image information corresponding to a high-definition display area in the to-be-displayed image information, processing the high-definition image information to obtain high-definition data voltage, processing the low-definition image information to obtain low-definition data voltage, and controlling to provide the high-definition data voltage or the low-definition data voltage to a corresponding row data line under the control of the data providing control signal;

the gating circuit is used for controlling the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to provide data voltage for the corresponding column pixel circuit through the corresponding column data line.

Optionally, the display control module according to at least one embodiment of the present invention further includes a data decoding module;

the data decoding module is used for carrying out data decoding on the eyeball image to obtain a decoded eyeball image and carrying out data decoding on the image information to obtain decoded image information;

the fixation point calculation module is used for calculating fixation direction information according to the decoded eyeball image;

and the image information to be displayed is the decoded image information.

Optionally, the display control module according to at least one embodiment of the present invention further includes a processor and a data driving module; the data voltage supply circuit and the gate circuit are included in the data driving module;

the processor, the data decoding module, the fixation point calculating module, the high-definition region calculating module, the image low-definition processing module, the time sequence control module, the grid scanning module and the data driving module are connected through a bus;

the processor is used for controlling the data decoding module to transmit the decoded image information to the gazing point calculating module, controlling the gazing point calculating module to provide the gazing direction information to the high-definition display area calculating module, and is used for controlling the high-definition display area calculation module to provide the high-definition display area to the image low-definition processing module and the timing control module, and a data voltage supply circuit for controlling the image low-definition processing module to supply the low-definition image information to the data driving module, and the timing control module is used for controlling the timing control module to provide the grid line driving timing to the grid scanning module, controlling the timing control module to provide the data line gating control signal to the gating circuit in the data driving module, and controlling the timing control module to provide the data providing control signal to the data voltage providing circuit in the data driving module.

Optionally, the processor, the data decoding module, the gaze point calculation module, the high-definition region calculation module, the image low-definition processing module, the timing control module, the gate scanning module, and the data driving module are all included in a display driving integrated circuit;

the display driving integrated circuit is a control processing chip based on RISC-V architecture.

Optionally, the gating circuit includes a shift register, a level reading circuit, and a gating switch circuit;

the shift register is used for providing a plurality of digital control levels for the level reading circuit through a plurality of output ends according to the data line gating control signal;

the level reading circuit is used for reading the digital control level, converting the digital control level into a corresponding analog control level and providing a plurality of analog control levels to the gating switch circuit;

and the gating switch circuit is used for controlling the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit under the control of the analog control level.

Optionally, the shift register includes N sequentially cascaded flip-flops; the trigger end of the trigger is accessed to a trigger clock signal; the input end of the first trigger is connected with the data line gating control signal; n is an integer greater than 1;

the positive phase output end of the nth trigger is electrically connected with the input end of the (n + 1) th trigger; the positive phase output end of the nth trigger is used for outputting an nth digital control level; n is a positive integer, N +1 is less than or equal to N;

the level reading circuit is respectively electrically connected with the positive phase output ends of the N triggers and is used for reading the digital control level from the positive phase output ends.

Optionally, the gating switching circuit includes N switching transistors; n is an integer greater than 1; n is a positive integer, N +1 is less than or equal to N;

a control electrode of the nth switching transistor is electrically connected with an nth analog control level output end of the level reading circuit, a first electrode of the nth switching transistor is electrically connected with an nth column data line, and a second electrode of the nth switching transistor is electrically connected with a data voltage receiving end of the nth column pixel circuit;

the level reading circuit is used for providing an nth analog control level through the nth analog control level output end.

Optionally, the data voltage providing circuit includes a conversion circuit, an output buffer circuit, and an output circuit;

the conversion circuit is used for receiving the low-definition image information and high-definition image information corresponding to a high-definition display area in the image information to be displayed, processing the high-definition image information to obtain high-definition data voltage, and processing the low-definition image information to obtain low-definition data voltage;

the output buffer circuit is used for caching the high-definition data voltage and the low-definition data voltage;

the output circuit is used for controlling and providing high-definition data voltage or low-definition data voltage to the corresponding column data line under the control of the data providing control signal.

Optionally, the display control module according to at least one embodiment of the present invention further includes an eyeball image acquisition module, an image signal processing module, and an image information acquisition module;

the eyeball image acquisition module is used for acquiring eyeball images;

the image signal processing module is used for processing the eyeball image to obtain a processed eyeball image and sending the processed eyeball image to the data decoding module so that the data decoding module can decode the processed eyeball image to obtain the decoded eyeball image;

the image information acquisition module is used for acquiring the image information to be displayed from a display data source.

An embodiment of the present invention further provides a display control method, which is applied to the display control module described above, where the display control method includes:

the fixation point calculation module calculates fixation azimuth information according to the obtained eyeball image;

the high-definition display area calculation module calculates a high-definition display area of the display panel according to the gazing direction information;

the image low-definition processing module acquires image information to be displayed, and performs low-definition processing on the image information to be displayed in other display areas except the high-definition display area of the display panel to obtain low-definition image information;

the time sequence control module generates a grid line driving time sequence, a data line gating control signal and a data voltage supply control signal according to the high-definition display area, provides the grid line driving time sequence to the grid scanning module, provides the data line gating control signal to the gating circuit and provides the data control signal to the data voltage supply circuit;

the grid scanning module provides corresponding grid driving signals for at least part of grid lines in a plurality of rows of grid lines according to the grid scanning time sequence;

the data voltage providing circuit receives low-definition image information and high-definition image information corresponding to a high-definition display area in the image information to be displayed, processes the high-definition image information to obtain high-definition data voltage, processes the low-definition image information to obtain low-definition data voltage, and controls to provide the high-definition data voltage or the low-definition data voltage to a corresponding column data line under the control of the data providing control signal;

and the gating circuit controls the corresponding column data line to be communicated with the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal so as to provide data voltage for the corresponding column pixel circuit through the corresponding column data line.

Optionally, the gaze point calculation module calculates a time period between two adjacent time points of different gaze direction information as an adjustment time period according to the obtained eyeball image; the conditioning period comprises at least one conditioning phase; each adjusting stage comprises a fused image output stage and a high-definition image output stage;

the step of providing corresponding gate driving signals to at least part of the gate lines in the plurality of rows of gate lines by the gate scanning module according to the gate scanning time sequence comprises the following steps:

in the fused image output stage, the grid scanning module provides a grid driving signal for grid lines included in a display panel according to the grid scanning time sequence so as to control the grid lines included in the display panel to be opened in sequence;

in the high-definition image output stage, the grid scanning module provides corresponding grid driving signals for high-definition control grid lines according to the grid scanning time sequence so as to control the high-definition control grid lines to be opened in sequence;

the high-definition control grid line is a grid line electrically connected with the pixel circuit in the high-definition display area.

the step of controlling the data voltage supply circuit to supply the high-definition data voltage or the low-definition data voltage to the corresponding column data line under the control of the data supply control signal comprises:

in the fused image output stage, the data voltage supply circuit writes the high-definition data voltage into a high-definition control data line and writes the low-definition data voltage into a low-definition control data line when the high-definition control gate line is opened under the control of the data supply control signal, and writes the low-definition data voltage into a corresponding row of data lines when the low-definition control gate line is opened;

in the high-definition image output stage, the data voltage supply circuit writes high-definition data voltage into a high-definition control data line under the control of the data supply control signal;

the high-definition control gate lines are gate lines electrically connected with the pixel circuits in the high-definition display area, the low-definition control gate lines are gate lines, except the high-definition control gate lines, included in the display panel, the high-definition control data lines are data lines electrically connected with the pixel circuits in the high-definition display area, and the low-definition control data lines are data lines, except the high-definition control data lines, included in the display panel.

the gating circuit controls the communication between the corresponding column data line and the data voltage receiving end of the corresponding column pixel circuit according to the data line gating control signal, and the gating circuit comprises the following steps:

in the fused image output stage, the gating circuit controls the data lines included by the display panel to be communicated with the data voltage receiving ends of the corresponding column pixel circuits respectively according to the data line gating control signals;

in the high-definition image output stage, the gating circuit controls the high-definition control data line to be communicated with the data voltage receiving end of the corresponding row of pixel circuits according to the data line gating control signal;

the high-definition control data line is a data line electrically connected with the pixel circuit in the high-definition display area.

The embodiment of the invention also provides a display device which comprises the display control module.

The display control module, the display control method and the display device can control the refresh rate of the high-definition display area to be larger than that of the low-definition display area, so that the display effect is ensured and the power consumption is reduced.

Drawings

FIG. 1 is a block diagram of a display control module according to at least one embodiment of the present disclosure;

FIG. 2 is a block diagram of a display control module according to at least one embodiment of the present disclosure;

FIG. 3 is a microarchitecture diagram showing a processor in a control module, in accordance with at least one embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a high definition display area;

FIG. 5 is a block diagram illustrating at least one embodiment of a gating circuit in a control module according to the present invention;

FIG. 6 is a block diagram of at least one embodiment of the gating circuit;

FIG. 7 is a block diagram of at least one embodiment of the gating circuit;

fig. 8 is a waveform diagram of a gate driving signal output by a row of gate lines and a waveform diagram of a data line gating control signal X1 during a fused image output phase and a waveform diagram of a gate driving signal output by a row of gate lines and a waveform diagram of a data line gating control signal during a high definition image output phase, in operation of at least one embodiment of the gating circuit shown in fig. 7;

FIG. 9 is a block diagram illustrating at least one embodiment of a data voltage providing circuit in a display control module according to the present invention;

fig. 10 is a schematic workflow diagram of a display control module according to at least one embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.

The display control module is applied to a display device, the display device comprises a display panel and a grid scanning module, and the display panel comprises a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of grid lines and a plurality of columns of data lines; the display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit;

When the display control module works, the fixation point calculation module identifies and calculates an eyeball image and calculates the fixation direction of human eyes; the high-definition area calculation module calculates an area needing high-definition display according to the watching direction of human eyes; and the time sequence control module generates a control time sequence according to the high-definition display area, and the control time sequence is used for controlling grid scanning and data scanning.

In specific implementation, the high-definition display area calculation module may calculate the high-definition display area of the display panel according to the gazing direction information and by combining with the resolution of the display panel.

When the display control module works, after the gaze point calculation module calculates different gaze direction information according to the acquired eyeball image, the adjustment time period may include at least one adjustment stage, and the adjustment stage may include a fusion image output stage and a high-definition image output stage;

in a fused image output stage, the gate scanning module provides gate driving signals for gate lines included in a display panel according to the gate scanning time sequence so as to control the gate lines included in the display panel to be sequentially opened, the data voltage providing circuit writes the high-definition data voltage into a high-definition control data line and writes the low-definition data voltage into a low-definition control data line under the control of the data providing control signals when the high-definition control gate lines are opened, and writes the low-definition data voltage into corresponding column data lines when the low-definition control gate lines are opened, and the gating circuit controls the data lines included in the display panel to be respectively communicated with data voltage receiving ends of corresponding column pixel circuits according to the data line gating control signals so as to output a fused image (the fused image includes a high-definition image and a low-definition image);

in a high-definition image output stage, the grid scanning module provides corresponding grid driving signals for high-definition control grid lines according to the grid scanning time sequence so as to control the high-definition control grid lines to be opened in sequence, and the data voltage providing circuit writes high-definition data voltages into high-definition control data lines under the control of the data providing control signals; and the gating circuit controls the high-definition control data line to be communicated with the data voltage receiving end of the corresponding row of pixel circuits according to the data line gating control signal so as to provide a high-definition image only for the high-definition display area.

The embodiment of the invention can control the refresh rate of the high-definition display area to be larger than that of the low-definition display area, thereby reducing the power consumption while ensuring the display effect.

In a specific implementation, the low-definition display area may be an area included in the display area of the display panel, except for the high-definition display area.

In at least one embodiment of the present invention, the duration of the fused image output phase may be a frame time, and the duration of the high definition image output phase may be a frame time, in which the fused image is sent out, and a plurality of rows of gate lines included in the display panel are normally and sequentially opened to display the fused image; in another frame time, only sending out a high-definition image, and controlling a high-definition display area to display the high-definition image, wherein the low-definition display area still keeps displaying the original picture due to the characteristics of liquid crystal; operating in this manner, the refresh rate of high definition regions may be 2 times the refresh rate of low definition regions. For example, the refresh rate of the high definition display area may be 120Hz and the refresh rate of the low definition display area may be 60 Hz.

In at least one embodiment of the present invention, the duration of the fused image output phase may be at least one frame time, and the duration of the high definition image output phase may be at least one frame time, but not limited thereto.

In a specific implementation, the high-definition control gate lines may be gate lines electrically connected to the pixel circuits in the high-definition display region, the low-definition control gate lines may be gate lines included in the display panel except for the high-definition control gate lines, the high-definition control data lines may be data lines electrically connected to the pixel circuits in the high-definition display region, and the low-definition control data lines may be data lines included in the display panel except for the high-definition control data lines.

In at least one embodiment of the present invention, the adjusting time period may be a time period between two adjacent time points when the gaze point calculation module calculates different gaze direction information according to the obtained eyeball image, but is not limited thereto. That is, the mth adjustment period may be an mth adjustment period between the time point at which the gaze point calculation module calculates the gaze direction information according to the eyeball image for the mth time and the time point at which the gaze point calculation module calculates the gaze direction information according to the eyeball image for the (m + 1) th time, where m is a positive integer.

The display control module according to at least one embodiment of the present invention may further include a data decoding module;

and the image information to be displayed is the decoded image information.

In a specific implementation, the display control module may include a data decoding module, configured to analyze the image information and the eyeball image to obtain a decoded eyeball image and decoded image information, and the gaze point calculation module calculates gaze direction information according to the decoded eyeball image.

In at least one embodiment of the present invention, the display control module further includes a processor and a data driving module; the data voltage supply circuit and the gate circuit are included in the data driving module;

In a specific implementation, the processor, the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module may all be included in a display driving integrated circuit.

In a specific implementation, the data voltage providing circuit and the gating circuit are included in the data driving module, and the processor, the data decoding module, the gaze point calculating module, the high definition region calculating module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module may all be included in a display driving integrated circuit. The processor is used for allocating resources in the display driving integrated circuit, and the processor can adopt a 5-level pipeline architecture and can perform calculation and data processing. The processor may be configured to control resource allocation among the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module.

The display control module according to at least one embodiment of the present invention is applied to a display device, and the display device includes a display panel and a gate scanning module, where the display panel includes a plurality of rows and columns of pixel circuits, a plurality of rows and columns of gate lines, and a plurality of columns of data lines; as shown in fig. 1, the display control module includes a gazing point calculation module 11, a high-definition display area calculation module 12, an image low-definition processing module 13, a timing control module 14, a gate scanning module 15, a data voltage supply circuit, a gating circuit, a data decoding module 17, and a processor 10;

the data voltage supply circuit and the gate circuit are included in the data driving module 16;

the processor 10, the data decoding module 17, the gaze point calculating module 11, the high definition region calculating module 12, the image low definition processing module 13, the timing control module 14, the gate scanning module 15, and the data driving module 16 are connected via a bus B1;

the processor 10, the data decoding module 17, the gazing point calculating module 11, the high definition region calculating module 12, the image low definition processing module 13, the timing control module 14, the gate scanning module 15, and the data driving module 16 are all included in a display driving integrated circuit DI.

In at least one embodiment of the present invention, the display driver integrated circuit DI may be a control processing chip based on RISC-V (RISC-V is an open Instruction Set Architecture (ISA) based on the principle of Reduced Instruction Set (RISC) — compared with most instruction sets), but not limited thereto.

In at least one embodiment of the present invention, the processor 10 may be a RISC-V architecture CPU (Central processing Unit) microkernel, but not limited thereto.

As shown in fig. 2, based on at least one embodiment of the display control module shown in fig. 1, the display control module according to at least one embodiment of the present invention further includes a system clock K1, a first interface M1, a second interface M2, a third interface C1, a first memory R1, a second memory R2, and an ISP (Image Signal Processing) module 20;

the system clock K1, the first interface M1, the second interface M2 and the third interface C1, the first memory R1, the second memory R2 and the ISP module 20 may be included in the display driving integrated circuit DI;

the first Interface M1 may be an MIPI (Mobile Industry Processor Interface) (Display Serial Interface) Interface;

the first interface M1 is electrically connected to a display data source (not shown in fig. 2, the display data source is disposed outside the display driver integrated circuit DI), and is configured to receive image information to be displayed from the display data source 101 and provide the image information to be displayed to the data decoding module 17 through a bus B1;

the second interface M2 may be an MIPI CSI interface (CSI interface is a Camera serial interface), and the third interface C1 may be a Camera Link interface;

the second interface M2 and the third interface C1 may be electrically connected to a camera sensor (not shown in fig. 2, the camera sensor is disposed outside the display driver integrated circuit DI) for transmitting an eyeball image provided by the camera sensor;

the ISP module 20 is electrically connected to the second interface M2, the third node C1 and the bus B1, and configured to receive the eyeball image, perform image processing on the eyeball image, obtain a processed eyeball image, and provide the processed eyeball image to the data decoding module 17 through the bus B1; the data decoding module 17 is configured to decode the processed eyeball image to obtain a decoded eyeball image.

In at least one embodiment of the present invention, the ISP module may perform the following processing on the eyeball image: black level compensation, lens correction, bad pixel correction, color interpolation, Bayer (Bayer is an original picture inside a camera, and is generally called as a suffix) noise removal, white balance (AWB) correction, color correction, gamma (gamma) correction, color space conversion (RGB to YUV), chroma removal and edge enhancement on YUV (Y is gray, U, V represents chroma of color) color space, color and contrast enhancement, automatic exposure control, and the like; but not limited thereto.

In at least one embodiment shown in FIG. 2, the first memory R1 can be a ROM (read only memory) and the second memory R2 can be a RAM (random access memory); the first memory R1 and the second memory R2 may be electrically connected to the bus B1, respectively;

the system clock K1 is used to provide a clock signal.

In at least one embodiment of the present invention, the display data source is disposed outside the display driver ic, and the display data source may be a high definition data source, and the display data source may be configured to provide high definition image information. In a specific implementation, the display data source may be a processor, such as a motherboard of a mobile phone, but is not limited thereto.

In at least one embodiment shown in FIG. 2, the first R1 and the second R2 are included in a memory unit, the memory unit is a memory of the processor 10, and the first, the second and the third registers are memory spaces in the memory unit;

storing the low-definition image information in the first buffer;

and high-definition image information corresponding to a high-definition display area is stored in the second buffer.

Fused image information is stored in the third buffer, and the fused image information comprises the low-definition image information and the high-definition image information corresponding to a high-definition display area.

When the at least one embodiment of the present invention shown in fig. 2 works, in a fused image output stage, the third buffer sends out the fused image information, and the data driving module 16 converts the high-definition image information into a high-definition data voltage and converts the low-definition image information into a low-definition data voltage; in the high-definition image output stage, the second buffer sends the high-definition image information to the data driving module 16, and the data driving module 16 converts the high-definition image information into a high-definition data voltage.

In at least one embodiment shown in fig. 2, a data transmission module 21 may be further disposed in the display driver ic, the data transmission module 21 is configured to transmit display data to the display panel, and the internal structure of the data transmission module is the same as that of an existing data transmission module, and may include a DAC (digital-to-analog converter), a buffer, and the like. When the display data is normally supplied to the pixel circuits, that is, when the high definition display area and the low definition display area are not distinguished, and the high definition display data is supplied to all the pixel circuits included in the display panel, the corresponding display data may be supplied to each data line through the data transmission module 21.

Fig. 3 is a microarchitectural diagram of the processor.

In FIG. 3, IF is the first stage pipeline, ID is the second stage pipeline, EX is the third stage pipeline, MEM is the fourth stage pipeline, and WB is the fifth stage pipeline.

In FIG. 3, ALU is an arithmetic logic unit, RAM is random access memory, and ROM is read only memory.

In fig. 4, reference numeral 40 is a high-definition display area, the a-th row of gate lines Ga, the a + 1-th row of gate lines, the a + 2-th row of gate lines, and the a + 3-th row of gate lines are electrically connected to pixel circuits located in the high-definition display area, and the b-th column of data lines Db, the b + 1-th column of data lines Db +1, the b + 2-th column of data lines Db +2, the b + 3-th column of data lines Db +3, and the b + 4-th column of data lines Db +4 are electrically connected to pixel circuits located in the high-definition display area; a and b are both positive integers;

in the display control module according to at least one embodiment of the present invention, the gate scan module may sequentially provide the corresponding gate driving signals to only Ga, Ga +1, Ga +2, and Ga +3 for one frame time to control Ga, Ga +1, Ga +2, and Ga +3 to be sequentially turned on, and the data driving module may provide the corresponding data voltages to only Db, Db +1, Db +2, Db +3, and Db +4 for one frame time to control the corresponding data voltages to only the high definition display area a0 for a predetermined period of time.

In a specific implementation, the gating circuit may include a shift register, a level reading circuit, and a gating switch circuit, where the shift register provides a plurality of digital control levels according to a data line gating control signal, the level reading circuit reads the digital control levels and converts the digital control levels into analog control levels, and the gating switch circuit controls communication between the data lines of the corresponding column and the data voltage receiving terminals of the pixel circuits of the corresponding column under the control of the analog control levels.

As shown in fig. 5, the gate circuit may include a shift register 51, a level reading circuit 52, and a gate switching circuit 53;

the shift register 51 is configured to provide 480 digital control levels to the level reading circuit 52 through 480 output terminals according to a data line gating control signal X1;

the level reading circuit 52 is electrically connected to the 480 output terminals, respectively, and is configured to convert the digital control level into a corresponding analog control level and provide a plurality of the analog control levels to the gate switch circuit 53;

the gate switch circuit 53 is electrically connected to the multiple rows of data lines, the multiple analog control level output ends of the level reading circuit 52, and the data voltage receiving ends of the multiple rows of pixel circuits, respectively, and is configured to control the communication between the corresponding row of data lines and the data voltage receiving ends of the corresponding row of pixel circuits under the control of the analog control level.

In fig. 5, a data line denoted by S1 is a first column data line, a data line denoted by S2 is a second column data line, a data line denoted by S3 is a third column data line, a data line denoted by S478 is a fourth hundred seventy eight column data line, a data line denoted by S479 is a fourth hundred seventy nine column data line, and a data line denoted by S480 is a fourth hundred eighty column data line;

a first analog control level output terminal is marked as O1, a second analog control level output terminal is marked as O2, a third analog control level output terminal is marked as O3, a fourth hundred seventy eight analog control level output terminal is marked as O478, a fourth hundred seventy nine analog control level output terminal is marked as O479, and a fourth hundred eighty analog control level output terminal is marked as O480;

a data voltage receiving terminal of the first column of pixel circuits is denoted by F1, a data voltage receiving terminal of the second column of pixel circuits is denoted by F2, a data voltage receiving terminal of the third column of pixel circuits is denoted by F3, a data voltage receiving terminal of the fourth hundred seventy-eighteen column of pixel circuits is denoted by F478, a data voltage receiving terminal of the fourth hundred seventy-nineteen column of pixel circuits is denoted by F479, and a data voltage receiving terminal of the fourth hundred eighty column of pixel circuits is denoted by F480.

In at least one embodiment of the present invention, the shift register may include N sequentially cascaded flip-flops; the trigger end of the trigger is accessed to a trigger clock signal; the input end of the first trigger is connected with the data line gating control signal; n is an integer greater than 1;

In a specific implementation, the shift register may include a plurality of flip-flops cascaded in sequence, the plurality of flip-flops output a plurality of digital control levels according to the data line strobe control signal, and the level reading circuit reads the digital control levels from the non-inverting output terminals of the flip-flops.

Optionally, the flip-flop may be a D flip-flop, a JK flip-flop, or other types of flip-flops. In at least one embodiment of the present invention, the flip-flop is exemplified as a D flip-flop.

In a specific implementation, the gate switch circuit may include a plurality of switch transistors, and the nth switch transistor may control on/off between the nth column data line and the data voltage receiving terminal of the nth column pixel circuit.

As shown in fig. 6, based on at least one embodiment of the gating circuit shown in fig. 5,

the shift register 51 may include 480D flip-flops which are sequentially cascaded; the trigger end of the D trigger is connected with a trigger clock signal X0; the input end of the first D flip-flop D1 is connected with the data line gating control signal X1;

the non-inverting output terminal of the first D flip-flop D1 is electrically connected with the input terminal of the second D flip-flop D2; the non-inverting output terminal of the first D flip-flop D1 is used for outputting a first digital control level;

the non-inverting output terminal of the second D flip-flop D2 is electrically connected with the input terminal of the third D flip-flop D3; the non-inverting output terminal of the second D flip-flop D2 is used for outputting a second digital control level;

the non-inverting output terminal of the third D flip-flop D3 is electrically connected to the input terminal of the fourth D flip-flop (not shown in fig. 6); the non-inverting output terminal of the third D flip-flop D3 is used for outputting a third digital control level;

the positive phase output end of the fourth hundred seventy eight D flip-flop D478 is electrically connected with the input end of the fourth hundred seventy nine D flip-flop D479; a positive phase output end of the fourth hundred seventy eight D flip-flop D478 is configured to output a fourth hundred seventy eight digital control level;

the non-inverting output end of the fourth hundred seventy nine D flip-flop D479 is electrically connected with the input end of the fourth hundred eighty D flip-flop D480; the non-inverting output end of the fourth hundred seventy nine D479 flip-flop is used for outputting a fourth hundred seventy nine digital control level;

the positive phase output end of the fourth hundred eighty D flip-flop is used for outputting a fourth hundred eighty digital control level;

the level reading circuit 52 is electrically connected to the non-inverting output terminals of the 480D flip-flops, respectively, and is configured to read a digital control level from the non-inverting output terminals, convert the digital control level into a corresponding analog control level, and supply a plurality of the analog control levels to the gate switch circuit 53.

In operation of at least one embodiment of the strobe circuit shown in fig. 6, the data line strobe control signal X1 is sequentially shifted to the right in the shift register at every upward pulse of the trigger clock signal X0, for example, after passing through 480 upward pulses of the trigger control signal X0, when the potential of the data line strobe control signal is a high voltage at the first upward pulse of the trigger clock signal X0, the 480 th D flip-flop D480 outputs a digital control level corresponding to the high voltage through its non-inverting output terminal; when the potential of the data line strobe control signal is a low voltage at the second upward pulse of the trigger clock signal X0, the 479 th D flip-flop D479 outputs a digital control level corresponding to the low voltage through its non-inverting output terminal; when the potential of the data line strobe control signal is a high voltage at the third upward pulse of the trigger clock signal X0, the 478 th D flip-flop D478 outputs a digital control level corresponding to the high voltage through its non-inverting output terminal; when the potential of the data line strobe control signal is a low voltage at a fourth hundred seventy eight upward pulses of the trigger clock signal X0, the third D flip-flop D3 outputs a digital control level corresponding to the low voltage through its non-inverting output terminal; when the potential of the data line strobe control signal is a high voltage at the fourth hundred seventy-nine upward pulses of the trigger clock signal X0, the second D flip-flop D2 outputs a digital control level corresponding to the high voltage through its non-inverting output terminal; when the potential of the data line strobe control signal is a low voltage at the fourth hundred and eighty upward pulses of the trigger clock signal X0, the first D flip-flop D1 outputs a digital control level corresponding to the low voltage through its non-inverting output terminal; and so on.

the gate switching circuit 53 includes N switching transistors; the control electrode of the nth switching transistor is electrically connected with the nth analog control level output end of the level reading circuit, the first electrode of the nth switching transistor is electrically connected with the nth column data line, and the second electrode of the nth switching transistor is electrically connected with the data voltage receiving end of the nth column pixel circuit.

In fig. 6, a first switching transistor denoted by T1 and included in the gate switching circuit 53, a second switching transistor denoted by T2 and included in the gate switching circuit 53, a third switching transistor denoted by T3 and included in the gate switching circuit 53, a fourth hundred seventy-eight switching transistor denoted by T478 and included in the gate switching circuit 53, a fourth hundred seventy-nine switching transistor denoted by T479 and included in the gate switching circuit 53, and a fourth hundred eighty switching transistor denoted by T480 and included in the gate switching circuit 53;

the gate of T1 is electrically connected to the first analog control level output terminal O1, the source of T1 is electrically connected to the first column data line S1, and the drain of T1 is electrically connected to the data voltage receiving terminal F1 of the first column pixel circuit;

the gate of T2 is electrically connected to the second analog control level output terminal O2, the source of T2 is electrically connected to the second column data line S2, and the drain of T2 is electrically connected to the data voltage receiving terminal F2 of the second column of pixel circuits;

the gate of T3 is electrically connected to the third analog control level output terminal O3, the source of T3 is electrically connected to the third column data line S3, and the drain of T3 is electrically connected to the data voltage receiving terminal F3 of the third column pixel circuit;

a gate of the T478 is electrically connected to the fourth hundred seventy eight analog control level output terminal O478, a source of the T478 is electrically connected to the fourth hundred seventy eight column data line S478, and a drain of the T478 is electrically connected to the data voltage receiving terminal F478 of the fourth hundred seventy eight column pixel circuit;

a gate of the T479 is electrically connected to the fourth hundred and seventy nine analog control level output terminal O479, a source of the T479 is electrically connected to the fourth hundred and seventy nine column data line S479, and a drain of the T479 is electrically connected to a data voltage receiving terminal F479 of the fourth hundred and seventy nine column pixel circuit;

the gate of the T480 is electrically connected to the fourth hundred eighty analog control level output terminal O480, the source of the T480 is electrically connected to the fourth hundred eighty column data line S480, and the drain of the T480 is electrically connected to the data voltage receiving terminal F480 of the fourth hundred eighty column pixel circuit.

In at least one embodiment of the gate circuit shown in fig. 6, each of the switch transistors may be an n-type thin film transistor, but not limited thereto.

In operation of at least one embodiment of the gating circuit shown in fig. 6, each switching transistor may be turned on or off under control of each analog control level to control whether a data voltage is provided to the corresponding column data line.

As shown in fig. 7, a pixel circuit and a gate driving circuit G1 are added to at least one embodiment of the gate circuit shown in fig. 6;

in fig. 7, reference numeral P11 denotes a first row and first column pixel circuit, reference numeral P12 denotes a first row and second column pixel circuit, reference numeral P13 denotes a first row and third column pixel circuit, reference numerals P1-478 denotes a first row and fourth hundred seventy eight column pixel circuit, reference numerals P1-479 denotes a first row and fourth hundred seventy nine column pixel circuit, and reference numerals P1-480 denotes a first row and fourth hundred eighty column pixel circuit;

a pixel circuit of a first column of a line A is marked by PA1, a pixel circuit of a second column of the line A is marked by PA2, a pixel circuit of a third column of the line A is marked by PA3, a pixel circuit of a fourth hundred seventy eight column of the line A is marked by PA-478, a pixel circuit of a fourth hundred seventy nine column of the line A is marked by PA-479, and a pixel circuit of a fourth hundred eighty column of the line A is marked by PA-480; a is an integer greater than 1;

p11 and PA1 are both electrically connected with the data voltage receiving terminal F1 of the pixel circuit of the first column; both P12 and PA2 are electrically connected to the data voltage receiving terminal F2 of the second column of pixel circuits; both P13 and PA3 are electrically connected to the data voltage receiving terminal F3 of the pixel circuit of the third column; each of P1-478 and PA-478 is electrically connected to a data voltage receiving terminal F478 of the fourth hundred and seventy-eight column pixel circuit; p1-479 and PA-479 are both electrically connected to the data voltage receiving terminal F479 of the fourth hundred and seventy-nine column pixel circuit; the P1-480 and the PA-480 are electrically connected with a data voltage receiving end F480 of the fourth hundred eighty column of pixel circuits;

the gate drive circuit G1 is used to provide first row gate drive signals for P11, P12, P13, P1-478, P1-479, and P1-480, and to provide row a gate drive signals for PA1, PA2, PA3, PA-478, PA-479, and PA-480.

In at least one embodiment shown in fig. 7, the gate scan module is the gate driving circuit G1, but not limited thereto.

In operation of at least one embodiment of the gate circuit shown in fig. 7, during the fused image output phase, the waveform G01 of the gate driving signal output by a row of gate lines and the waveform X11 of the data line gate control signal X1 are as shown in fig. 8;

in the high definition image output phase, the waveform G02 of the gate driving signal output by a row of gate lines and the waveform X12 of the data line gating control signal X1 are as shown in fig. 8;

optionally, the data voltage providing circuit may include a conversion circuit, an output buffer circuit, and an output circuit;

In particular implementation, the data voltage supply circuit may include a conversion circuit, an output buffer circuit, and an output circuit; the conversion circuit is used for converting high-definition image information into high-definition data voltage and converting low-definition image information into low-definition data voltage, wherein the high-definition image information and the low-definition image information can be digital signals, and the high-definition data voltage and the low-definition data voltage can be analog voltage signals; the output buffer circuit is used for buffering the high-definition data voltage and the low-definition data voltage, and the output circuit is used for controlling to provide the high-definition data voltage or the low-definition data voltage to the corresponding column data line under the control of a data providing control signal.

As shown in fig. 9, at least one embodiment of the data voltage supply circuit may include a conversion circuit, an output buffer circuit 81, and an output circuit 82;

the output buffer circuit 81 is configured to buffer the high definition data voltage and the low definition data voltage;

the output circuit 82 is electrically connected to the output buffer circuit 81, the output circuit 82 is connected to a data providing control signal S0, and the output circuit 82 is configured to control to provide a high definition data voltage or a low definition data voltage to the corresponding column data line under the control of the data providing control signal S0;

the output circuit 82 is also electrically connected with 480 columns of data lines respectively;

in fig. 9, a data line denoted by reference numeral S1 is a first column data line, a data line denoted by reference numeral S2 is a second column data line, a data line denoted by reference numeral S3 is a third column data line, a data line denoted by reference numeral S478 is a fourth hundred seventy eight column data line, a data line denoted by reference numeral S479 is a fourth hundred seventy nine column data line, and a data line denoted by reference numeral S480 is a fourth hundred eighty column data line;

the conversion circuit may include an input register 91, a data latch 92, a level converter 93, and a digital-to-analog converter 94;

the input register 91 and the data latch 92 are used for temporarily storing image information and transmitting the image information to the level shifter 93; the image information comprises the low-definition image information and high-definition image information corresponding to a high-definition display area in the image information to be displayed;

the level shifter 93 is electrically connected to the data latch 92, and is configured to convert the low voltage of 3.3V output by the data latch 92 into a high voltage of about 15V, so as to convert the image information into output image information; the output image information comprises output low-definition image information and output high-definition image information corresponding to a high-definition display area;

the digital-to-analog converter 94 is electrically connected to the level shifter 93, and the digital-to-analog converter 94 is configured to convert the output low-definition image information output by the level shifter 93 to obtain a low-definition data voltage, and is configured to convert the output high-definition image information output by the level shifter 93 to obtain a high-definition data voltage.

As shown in fig. 10, when the display control module according to at least one embodiment of the present invention works, first, image information and an eyeball image are acquired; then decoding the image information and the eyeball image; calculating a fixation direction according to the decoded eyeball image, and caching the decoded image information; then, calculating a high-definition area according to the resolution and the gazing direction information of the display panel, generating a grid line driving time sequence, a data line gating control signal and a data voltage supply control signal according to the calculated high-definition area, and performing low-definition processing on image information to be displayed (the image information to be displayed is decoded) of other display areas except the high-definition display area of the display panel to obtain low-definition image information; storing low-definition image information into a first buffer, storing high-definition image information into a second buffer, and storing fused image information (the fused image information comprises the low-definition image information and the high-definition image information corresponding to a high-definition display area) into a third buffer; converting the low-definition image information and high-definition image information in the image information to be displayed to obtain low-definition data voltage and high-definition data voltage; in the fused image output stage, all row grid lines included in the display panel are sequentially opened, and all column data lines included in the display panel respectively receive corresponding data voltages; in the high-definition image output stage, the high-definition control grid line is opened, and the high-definition control data line receives high-definition data voltage.

The display control module according to at least one embodiment of the present invention may further include an eyeball image acquisition module, an image signal processing module, and an image information acquisition module;

the eyeball image acquisition module is used for acquiring eyeball images;

In a specific implementation, the eyeball image acquisition module may be a Camera sensor (Camera sensor), but is not limited thereto.

The display control method according to the embodiment of the present invention is applied to the display control module described above, and the display control method includes:

In specific implementation, the gaze point calculation module calculates a time period between two adjacent time points of different gaze direction information as an adjustment time period according to the acquired eyeball image; the conditioning period comprises at least one conditioning phase; each adjusting stage comprises a fused image output stage and a high-definition image output stage;

In at least one embodiment of the present invention, in the high definition image output stage, the high definition control gate lines are sequentially turned on, so that only the pixel circuits in the high definition region can receive the new high definition data voltage, and the refresh rate of the high definition region is increased, so that the regions of the display region of the display panel other than the high definition region still display the original image.

In at least one embodiment of the present invention, in the high definition image output stage, the data voltage providing circuit only writes the high definition data voltage into the high definition control data line, so that only the pixel circuits in the high definition area can receive the new high definition data voltage, and the area of the display panel other than the high definition area still displays the original image.

In at least one embodiment of the present invention, in the high definition image output stage, the gating circuit controls the high definition control data line to communicate with the data voltage receiving end of the corresponding column of pixel circuits, so that only the pixel circuits in the high definition area can receive the new high definition data voltage, and the area of the display panel except for the high definition area still displays the original image.

The display device provided by the embodiment of the invention comprises the display control module.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display control module is applied to a display device, the display device comprises a display panel and a grid scanning module, wherein the display panel comprises a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of grid lines and a plurality of columns of data lines; the display control module comprises a fixation point calculation module, a high-definition display area calculation module, an image low-definition processing module, a time sequence control module, a grid scanning module, a data voltage supply circuit and a gating circuit;

2. The display control module of claim 1, further comprising a data decoding module;

and the image information to be displayed is the decoded image information.

3. The display control module of claim 2, further comprising a processor and a data driver module; the data voltage supply circuit and the gate circuit are included in the data driving module;

4. The display control module of claim 3, wherein the processor, the data decoding module, the gaze point calculation module, the high definition region calculation module, the image low definition processing module, the timing control module, the gate scanning module, and the data driving module are included in a display driving integrated circuit;

5. The display control module according to any one of claims 1 to 4, wherein the gate circuit includes a shift register, a level reading circuit, and a gate switch circuit;

6. The display control module of claim 5, wherein the shift register comprises N flip-flops cascaded in sequence; the trigger end of the trigger is accessed to a trigger clock signal; the input end of the first trigger is connected with the data line gating control signal; n is an integer greater than 1;

7. The display control module of claim 5, wherein the gate switch circuit comprises N switching transistors; n is an integer greater than 1; n is a positive integer, N +1 is less than or equal to N;

8. The display control module according to any one of claims 1 to 4, wherein the data voltage supply circuit includes a conversion circuit, an output buffer circuit, and an output circuit;

9. The display control module according to any one of claims 2 to 4, further comprising an eyeball image acquisition module, an image signal processing module, and an image information acquisition module;

the eyeball image acquisition module is used for acquiring eyeball images;

10. A display control method applied to the display control module according to any one of claims 1 to 9, characterized by comprising:

11. The display control method according to claim 10, wherein the gaze point calculation module calculates a time period between two adjacent time points of different gaze direction information as an adjustment time period from the acquired eye image; the conditioning period comprises at least one conditioning phase; each adjusting stage comprises a fused image output stage and a high-definition image output stage;

12. The display control method according to claim 10, wherein the gaze point calculation module calculates a time period between two adjacent time points of different gaze direction information as an adjustment time period from the acquired eye image; the conditioning period comprises at least one conditioning phase; each adjusting stage comprises a fused image output stage and a high-definition image output stage;

13. The display control method according to claim 10, wherein the gaze point calculation module calculates a time period between two adjacent time points of different gaze direction information as an adjustment time period from the acquired eye image; the conditioning period comprises at least one conditioning phase; each adjusting stage comprises a fused image output stage and a high-definition image output stage;

14. A display apparatus comprising the display control module according to any one of claims 1 to 9.