CN114267598A - Packaging structure and packaging method of radio frequency front-end integrated circuit - Google Patents
Packaging structure and packaging method of radio frequency front-end integrated circuit Download PDFInfo
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Abstract
The invention discloses a packaging structure and a packaging method of a radio frequency front-end integrated circuit, which comprises the following steps: providing a first carrier plate, and attaching a chip on the first carrier plate to construct a first packaging layer; performing multiple times of packaging, thinning and punching and RDL wiring process treatment on the upper surface of the first packaging layer, wherein the packaging layer and the wiring layer are in an alternating structure; packaging the surface mounting device on the last wiring layer to form a first packaging body; and removing the first carrier plate, attaching a second carrier plate to the upper surface of the packaging body, performing RDL wiring on the lower surface of the first packaging body to form a second packaging body, removing the second carrier plate, attaching a device for packaging, and forming a final packaging body. The invention adopts the carrier plate to replace a multilayer substrate, reduces the production cost and the processing difficulty of products, carries out encapsulation-wiring multilayer superposition encapsulation, effectively shortens the heat dissipation path, can reduce the parasitic parameters of capacitance and inductance, improves the heat conduction efficiency, is directly connected with a metal heat dissipation surface, and improves the heat dissipation performance of the final encapsulation body.
Description
Technical Field
The present invention relates to the field of integrated circuit packaging technologies, and in particular, to a packaging structure and a packaging method for a radio frequency front end integrated circuit.
Background
With the increasing of signal transmission distance in radar and communication systems, high-power devices are widely applied to circuit modules and systems in related fields. Meanwhile, along with the requirements of system miniaturization and light weight, more and more power amplification chips and components need to be integrated in a limited-size package, so that the power and heat consumption of the chips in unit area are greatly increased, and the electric heating performance of the whole system is severely restricted.
Most of the existing thermal designs of power amplifier chips are realized by connecting the power amplifier chips with a substrate through a TSV technology, and specific heat dissipation paths are designed as follows: the front circuit of the power amplifier chip generates heat, the heat is conducted to the back metal layer of the chip through the TSV interconnection technology, then the heat is conducted to the surface of the packaging multilayer substrate from the back metal layer, and finally the heat is conducted to the circuit board of the mobile device. Therefore, heat can be conducted to the surface of the substrate through the long multilayer interconnection circuit and the through holes, and for the design of the multilayer substrate, the inductance and the resistance are too large due to the long heat conduction path, so that the heat conduction efficiency is poor, and the heat dissipation performance is also a great challenge. On the other hand, the TSV technology needs expensive materials such as a substrate, the processing cost is high, and the processing difficulty is high.
From the above, it can be seen that how to improve the heat dissipation performance is a problem to be solved at present.
Disclosure of Invention
The invention aims to provide a packaging structure and a packaging method of a radio frequency front-end integrated circuit, which solve the problems of poor packaging heat conduction efficiency and low heat dissipation performance; and simultaneously, the parasitic parameters of capacitance, inductance and the like in a radio frequency path can be reduced.
In order to solve the above technical problem, the present invention provides a first carrier, wherein a back surface of a chip is attached to an upper surface of the first carrier, and a first encapsulation layer is constructed, including: providing a first carrier plate, attaching the back surface of a chip to the upper surface of the first carrier plate, and constructing a first packaging layer; performing multiple times of packaging, thinning and punching and RDL wiring process treatment on the upper surface of the first packaging layer to form a multilayer structure in which packaging layers and wiring layers are alternately stacked; mounting a device on the surface of the topmost wiring layer, and carrying out complete encapsulation treatment to form a first packaging body; removing the first carrier plate, mounting the upper surface of the first packaging body to a second carrier plate, and performing RDL wiring on the lower surface of the first packaging body to form a second packaging body; and removing the second carrier plate, and stacking and packaging the second packaging body and other devices to form a final packaging body.
Preferably, the removing the first carrier plate comprises: and removing the first carrier plate by using a laser mode.
Preferably, the encapsulation-thinning perforation-RDL wiring process comprises;
performing RDL wiring on the upper surface of the first packaging layer to form a first wiring layer;
encapsulating the first wiring layer by using a plastic encapsulation material to form a second encapsulation layer;
punching the second packaging layer by using laser, and penetrating through the upper surface and the lower surface of the second packaging layer to form a conductive through hole connected with the first wiring layer;
and performing RDL wiring on the upper surface of the second encapsulation layer to form a second wiring layer, so that the second wiring layer is connected with the conductive through hole.
Preferably, the thickness of each of the first wiring layer and the second wiring layer is greater than 3 μm, and the material of each of the first wiring layer and the second wiring layer is electroplated copper.
Preferably, the providing a first carrier board, and the building a first encapsulation layer on the first carrier board includes:
providing the first carrier plate, and attaching the back surface of the chip to the upper surface of the first carrier plate to form an assembly body;
encapsulating the component body by using a plastic encapsulating material to form a first encapsulating layer;
and thinning the first packaging layer until the metal protruding structure of the component body is exposed.
Preferably, the thinning the first encapsulating layer until the metal bump structure of the component body is exposed includes:
and thinning the first encapsulating layer by using a plate grinding method, a laser method or a plasma etching method until the metal protruding structure in the component body is exposed.
Preferably, the surface mounting a device on the topmost wiring layer, performing a complete encapsulation process, and forming the first package further includes:
and carrying out laser perforation on the first packaging body to form a through hole penetrating through the upper surface and the lower surface of the first packaging body, and filling the through hole with metal.
Preferably, the material of the first carrier plate and the second carrier plate is glass or iron.
Preferably, a packaging structure of a radio frequency front end integrated circuit includes:
a plurality of chips and devices, a chip encapsulating layer, a wiring layer, an encapsulating-wiring layer, a complete encapsulating layer and a through hole;
the chip encapsulating layer is positioned on the upper layer of the wiring layer and encapsulates a plurality of chips;
the packaging-wiring layer is positioned on the upper layer of the chip packaging layer and is of a structure in which the packaging layer and the wiring layer are alternately superposed;
the through hole penetrates through the encapsulation-wiring layer and the chip encapsulation layer;
the complete encapsulation layer is positioned on the encapsulation-wiring layer and covers a plurality of devices.
Preferably, the plurality of chips includes: a power amplification chip, a CMOS chip or a radio frequency switch chip.
Preferably, the packaging structure of the radio frequency front end integrated circuit adopts any one of the packaging methods.
The invention provides a packaging structure and a packaging method of a radio frequency front-end integrated circuit, wherein in the packaging process, a first carrier plate is provided, a component body is constructed on the first carrier plate, multiple times of packaging, thinning, punching and RDL wiring process treatment are carried out on the component body, multiple times of packaging layers and wiring layers are alternately superposed, a device is pasted on the uppermost wiring layer, complete packaging treatment is carried out, a first packaging body is formed, the first carrier plate is removed, a second carrier plate is pasted on the upper surface of the packaging body, RDL wiring treatment is carried out on the lower surface of the packaging body, a second packaging body is formed, the second carrier plate is removed, and the second packaging body and other devices are stacked and packaged to form a final packaging body. According to the invention, the carrier plate is adopted to replace a multilayer substrate, so that the production cost and the processing difficulty are reduced, the heat conduction efficiency is improved, and the encapsulation-wiring multilayer overlapping package and the wiring layer on the lower surface are carried out, so that the chip and the device can be directly connected with the metal heat dissipation surface, the heat dissipation path is effectively shortened, the parasitic parameters of capacitance and inductance can be reduced by the design of the wiring layer, and the heat dissipation performance of the final package body is further improved.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a flowchart of a first embodiment of a packaging method for an rf front-end integrated circuit according to the present invention;
FIG. 2 is a flowchart illustrating a second embodiment of a packaging method for RF front-end ICs according to the present invention;
FIG. 3a is a block diagram of the assembly of the present invention;
FIG. 3b is a diagram of the structure of the first encapsulant layer and the first wiring layer of the present invention;
FIG. 3c is a diagram of a second encapsulant layer and a second wiring layer structure in accordance with the present invention;
FIG. 3d is a block diagram of the package formed according to the present invention;
FIG. 3e is a schematic diagram of the through hole formation of the present invention;
FIG. 3f is a block diagram of the present invention forming a final package;
FIG. 4 is a flowchart illustrating a method for packaging an RF front-end IC according to a third embodiment of the present invention;
FIG. 5 is a schematic diagram of a wire-bonded chip packaging method according to the present invention;
FIG. 6 is a schematic structural diagram of a flip chip package method according to the present invention;
FIG. 7 is a schematic diagram of a structure of the present invention applied to a hybrid packaging method;
labeled as: the chip packaging structure comprises a metal bump 1, a first carrier plate 2, a chip 3, a first encapsulating layer 4, a first wiring layer 5, a second encapsulating layer 6, a conductive through hole 7, a second wiring layer 8, a device 9, a complete encapsulating layer 10, a through hole 11, a second carrier plate 12 and a last wiring layer 13.
Detailed Description
The core of the invention is to provide a packaging structure and a packaging method of a radio frequency front end integrated circuit, which solve the problems of poor packaging heat conduction efficiency and low heat dissipation performance.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a packaging method of an rf front-end integrated circuit according to a first embodiment of the present invention; the specific operation steps are as follows:
step S101: providing a first carrier plate, attaching the back surface of a chip to the upper surface of the first carrier plate, and constructing a first packaging layer;
step S102: performing multiple times of packaging, thinning and punching and RDL wiring process treatment on the upper surface of the first packaging layer to form a multilayer structure in which packaging layers and wiring layers are alternately stacked;
step S103: mounting a device on the surface of the topmost wiring layer, and carrying out encapsulation treatment to form a first packaging body;
step S104: removing the first carrier plate, mounting the upper surface of the first packaging body to a second carrier plate, and performing RDL wiring on the lower surface of the first carrier plate to form a second packaging body;
step S105: and removing the second carrier plate, and stacking and packaging the second packaging body and other devices to form a final packaging body.
The final package structure obtained is: a plurality of chips and devices, a chip encapsulating layer, a wiring layer, an encapsulating-wiring layer, a complete encapsulating layer and a through hole;
the chip encapsulating layer is positioned on the upper layer of the wiring layer and encapsulates a plurality of chips;
the packaging-wiring layer is positioned on the upper layer of the chip packaging layer and is of a structure in which the packaging layer and the wiring layer are alternately superposed;
the through hole penetrates through the encapsulation-wiring layer and the chip encapsulation layer;
the complete encapsulation layer is positioned on the encapsulation-wiring layer and covers a plurality of devices.
In the packaging method provided in this embodiment, in the packaging process, a first carrier is provided, a chip is attached to the first carrier, a first package layer is constructed, multiple times of packaging, thinning, punching and RDL wiring processes are performed on the package layer, multiple times of package layers and wiring layers are alternately stacked, a device is attached to the uppermost wiring layer, packaging is performed, a first package body is formed, the first carrier is removed, a second carrier is attached to the upper surface of the first package body, RDL wiring is performed on the lower surface of the first package body, a second package body is formed, the second carrier is removed, and the second package body is attached to other devices for packaging, so that a final package body is formed. The invention adopts the carrier plate to replace a multilayer substrate, reduces the production cost and the processing difficulty of products, improves the heat conduction efficiency, effectively shortens the heat dissipation path, can also reduce the parasitic parameters of capacitance and inductance and increase the heat dissipation efficiency through the alternate superposition structure of a plurality of encapsulation-wiring layers, and can directly connect the metal heat dissipation surface through the last wiring layer so as to improve the heat dissipation performance of the final packaging body.
Based on the above embodiments, the present embodiment describes a method for packaging a radio frequency front end integrated circuit in detail, please refer to fig. 2 and fig. 3, where fig. 2 is a flowchart of a second embodiment of a method for packaging a radio frequency front end integrated circuit provided by the present invention, and fig. 3 is a schematic diagram of steps of a radio frequency front end integrated circuit packaging structure provided by the present invention; the specific operation steps are as follows:
step S201: providing the first carrier plate, and attaching the back surfaces of the multiple chips to the upper surface of the first carrier plate to form an assembly body;
the first carrier plate is made of iron or glass, and can be made of other materials.
The chip comprises a power amplification chip, and can also, but need not necessarily, all comprise elements such as a CMOS chip, a radio frequency switch chip, a plurality of passive devices and the like, the surface of the chip is provided with a metal bump structure, the metal bump structure is a copper column and can also be made of other materials, and the back surface of the chip is attached to the first carrier plate.
Step S202: encapsulating the component body by using the plastic encapsulating material to form a first encapsulating layer;
step S203: thinning the first packaging layer until the metal bulge structure of the component body is exposed;
the encapsulating layer can be thinned by adopting a plate grinding method or a plasma etching method to expose the end part of the copper column for subsequent electric or heat conduction.
Step S204: performing RDL wiring on the upper surface of the first packaging layer to form a first wiring layer;
the thickness of the wiring metal layer is more than 3 μm, and the wiring layer uses electroplated copper.
Step S205: encapsulating the first wiring layer by using a plastic encapsulation material to form a second encapsulation layer;
step S206: punching the second packaging layer by using laser, and penetrating through the upper surface and the lower surface of the second packaging layer to form a conductive through hole connected with the first wiring layer;
step S207: performing RDL wiring on the upper surface of the second encapsulation layer to form a second wiring layer, so that the second wiring layer is connected with the conductive through hole;
step S208: surface mounting an SMD element on the second wiring layer, and carrying out packaging treatment to form a packaging body;
step S209: performing laser perforation on the packaging body to form a through hole penetrating through the upper surface and the lower surface of the packaging body, and filling the through hole with metal;
step S210: and removing the first carrier plate, attaching the second carrier plate to the upper surface of the packaging body, performing RDL wiring on the lower surface of the first packaging layer to form a temporary packaging body, removing the second carrier plate, and attaching other devices to the final packaging body for packaging to form a final packaging body.
The other devices IPD (integrated passive device) may also be in other forms, and are not limited herein.
The first carrier on the upper surface of the device is removed, and generally, a laser method is adopted, but not limited to laser opening or photoetching opening.
In this embodiment, a first carrier is provided, a first encapsulation layer is formed on an upper surface of the first carrier, the first encapsulation layer is processed, a first wiring layer is formed on the first encapsulation layer, a second encapsulation layer is formed on the first wiring layer, the second encapsulation layer is perforated by laser to form a conductive through hole, the conductive through hole is connected with the upper and lower wiring layers, a second wiring layer is formed on the second encapsulation layer, an SMD element is mounted on the wiring layer, encapsulation processing is performed to form a package, laser perforation is performed on the package to form a through hole, the through hole is filled with metal, the first carrier is removed, the second carrier is mounted on the upper surface of the package, RDL wiring is performed below the first encapsulation layer again to form a temporary package, the second carrier is removed, mounting packaging is performed with IPD, and a final package is formed. In the embodiment provided by the invention, the chip is pasted with the carrier plate, and then the encapsulation-wiring multilayer overlapping structure encapsulation is carried out, so that the use of a multilayer encapsulation substrate is avoided, and the production cost and the processing difficulty of the product are effectively reduced; by the packaging method of the packaging-wiring layer, a heat dissipation path is effectively shortened, parasitic parameters of capacitance and inductance are reduced, heat conduction performance is improved, the last RDL wiring is directly connected with the heat dissipation metal surface of the substrate, and heat dissipation performance of the packaging body is further improved.
Referring to fig. 4, fig. 4 is a flowchart illustrating a packaging method of an rf front-end integrated circuit according to a third embodiment of the present invention; the specific operation steps are as follows:
step S401: providing a glass carrier plate, and attaching the back surface of a power amplification chip to the upper surface of the glass carrier plate to form a component body;
step S402: encapsulating the component body by using the plastic encapsulating material to form a first encapsulating layer;
step S403: thinning the first encapsulating layer by using a plasma etching method until the copper pillar protruding structure of the first assembly is exposed;
step S404: performing RDL wiring on the upper surface of the first packaging layer to form a first electroplated copper wiring layer with the thickness of more than 3 mu m;
step S405: encapsulating the first electroplated copper wiring layer by using a plastic packaging material to form a second encapsulation layer;
step S406: thinning the second packaging layer by using a grinding plate, perforating by using laser, and penetrating through the upper surface and the lower surface of the second packaging layer to form a conductive through hole connected with the first electroplated copper wiring layer;
step S407: performing RDL wiring on the upper surface of the second encapsulation layer to form a second electroplated copper wiring layer with the thickness larger than 3 mu m, and enabling the second electroplated copper wiring layer to be connected with the conductive through hole;
step S408: a CMOS chip is pasted on the surface of the second wiring layer, and encapsulation processing is carried out to form a packaging body;
step S409: performing laser perforation on two sides of the packaging body to form two through holes penetrating through the upper surface and the lower surface of the packaging body, and filling the through holes with metal;
step S410: and removing the glass carrier plate by using a laser method, attaching the iron carrier plate to the upper surface of the packaging body, performing RDL wiring on the lower surface of the first packaging layer, removing the iron carrier plate, and stacking the IPD device to form a final packaging body structure.
The packaging method provided by the invention can also be used in the lead bonding chip packaging, a carrier plate is adopted to replace a multilayer substrate, the cost is saved, the heat dissipation propagation path is directly shortened, the electric surface of the element to be packaged is upward, the element does not directly contact with the wiring layer, the electric surface is directly connected with the topmost wiring layer in a wire mode, the heat dissipation path is shortened, and the specific structural schematic diagram is shown in fig. 5.
The packaging method provided by the invention can also be implemented in the packaging of flip chips, the electrical surfaces of the flip chips are downward, and the flip chips have good heat dissipation performance, and then the first carrier plate and the second carrier plate are adopted to carry out packaging for multiple times, packaging-thinning-wiring process treatment can further improve the heat dissipation performance, reduce the requirement of multiple layers of substrates for packaging before, reduce the cost and the processing difficulty of products, and the specific structural schematic diagram is shown in fig. 6.
The packaging method provided by the invention can also be used in hybrid packaging, namely, combining various modes such as flip chip, wire bonding, SMT and the like, and can shorten a heat dissipation path through multiple packaging, thinning and wiring processes, and the first carrier plate and the second carrier plate are adopted for packaging, so that the cost and the product processing difficulty are reduced, the heat dissipation performance is improved, and the specific structural schematic diagram is shown in FIG. 7.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The present invention provides a packaging structure and a packaging method for a radio frequency front end integrated circuit. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (11)
1. A method for packaging a radio frequency front end integrated circuit, comprising:
providing a first carrier plate, attaching the back surface of a chip to the upper surface of the first carrier plate, and constructing a first packaging layer;
performing multiple times of packaging, thinning and punching and RDL wiring process treatment on the upper surface of the first packaging layer to form a multilayer structure in which packaging layers and wiring layers are alternately stacked;
mounting a device on the surface of the topmost wiring layer, and carrying out complete encapsulation treatment to form a first packaging body;
removing the first carrier plate, mounting the upper surface of the first packaging body to a second carrier plate, and performing RDL wiring on the lower surface of the first packaging body to form a second packaging body;
and removing the second carrier plate, and stacking and packaging the second packaging body and other devices to form a final packaging body.
2. The method of packaging of claim 1, wherein the removing the first carrier comprises: and removing the first carrier plate by using a laser mode.
3. The packaging method of claim 1, wherein the encapsulation-thinning punch-through-RDL routing process comprises;
performing RDL wiring on the upper surface of the first packaging layer to form a first wiring layer;
encapsulating the first wiring layer by using a plastic encapsulation material to form a second encapsulation layer;
punching the second packaging layer by using laser, and penetrating through the upper surface and the lower surface of the second packaging layer to form a conductive through hole connected with the first wiring layer;
and performing RDL wiring on the upper surface of the second encapsulation layer to form a second wiring layer, so that the second wiring layer is connected with the conductive through hole.
4. The packaging method of claim 3, wherein the first and second wiring layers are each greater than 3 μm thick, and wherein the first and second wiring layers are each of electroplated copper.
5. The packaging method of claim 1, wherein the providing the first carrier, and the building the first encapsulation layer on the first carrier comprises:
providing the first carrier plate, and attaching the back surface of the chip to the upper surface of the first carrier plate to form an assembly body;
encapsulating the component body by using a plastic encapsulating material to form a first encapsulating layer;
and thinning the first packaging layer until the metal protruding structure of the component body is exposed.
6. The packaging method according to claim 5, wherein the thinning the first encapsulant layer until the metal bump structures of the component body are exposed comprises:
and thinning the first encapsulating layer by using a plate grinding method, a laser method or a plasma etching method until the metal protruding structure in the component body is exposed.
7. The method for packaging as claimed in claim 1, wherein the surface mounting the device on the topmost wiring layer for performing a complete encapsulation process to form the first package further comprises:
and carrying out laser perforation on the first packaging body to form a through hole penetrating through the upper surface and the lower surface of the first packaging body, and filling the through hole with metal.
8. The package structure of claim 1, wherein a material of the first carrier and the second carrier is glass or iron.
9. A package structure for a radio frequency front end integrated circuit, comprising:
a plurality of chips and devices, a chip encapsulating layer, a wiring layer, an encapsulating-wiring layer, a complete encapsulating layer and a through hole;
the chip encapsulating layer is positioned on the upper layer of the wiring layer and encapsulates a plurality of chips;
the packaging-wiring layer is positioned on the upper layer of the chip packaging layer and is of a structure in which the packaging layer and the wiring layer are alternately superposed;
the through hole penetrates through the encapsulation-wiring layer and the chip encapsulation layer;
the complete encapsulation layer is positioned on the encapsulation-wiring layer and covers a plurality of devices.
10. The package structure of claim 9, wherein the number of chips comprises: a power amplification chip, a CMOS chip or a radio frequency switch chip.
11. A package structure of a radio frequency front end integrated circuit, characterized in that the package structure adopts the packaging method of any one of claims 1 to 8.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114899111A (en) * | 2022-04-22 | 2022-08-12 | 宜确半导体（苏州）有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN116169113A (en) * | 2023-04-21 | 2023-05-26 | 江苏芯德半导体科技有限公司 | QFN packaging structure capable of reducing heat conduction to PCB and preparation method thereof |
| CN116960108A (en) * | 2023-09-21 | 2023-10-27 | 江苏展芯半导体技术有限公司 | Chip packaging structure and method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120326300A1 (en) * | 2011-06-24 | 2012-12-27 | National Semiconductor Corporation | Low profile package and method |
| CN108172551A (en) * | 2016-11-29 | 2018-06-15 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN109244231A (en) * | 2018-11-09 | 2019-01-18 | 江阴长电先进封装有限公司 | A kind of encapsulating structure and its packaging method of sound surface filtering chip |
| CN110400780A (en) * | 2019-07-23 | 2019-11-01 | 杭州晶通科技有限公司 | A kind of fan-out-type stack package structure and preparation method thereof using metallic conduction post |
| CN110970397A (en) * | 2019-12-19 | 2020-04-07 | 江苏中科智芯集成科技有限公司 | Stack packaging structure and preparation method thereof |
| CN112038329A (en) * | 2020-10-12 | 2020-12-04 | 长电集成电路(绍兴)有限公司 | Wafer-level chip fan-out three-dimensional stacking packaging structure and manufacturing method thereof |
| CN112053962A (en) * | 2020-09-14 | 2020-12-08 | 山东傲天环保科技有限公司 | System-level stack package and preparation method thereof |
-
2021
- 2021-12-07 CN CN202111488795.1A patent/CN114267598B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120326300A1 (en) * | 2011-06-24 | 2012-12-27 | National Semiconductor Corporation | Low profile package and method |
| CN108172551A (en) * | 2016-11-29 | 2018-06-15 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN109244231A (en) * | 2018-11-09 | 2019-01-18 | 江阴长电先进封装有限公司 | A kind of encapsulating structure and its packaging method of sound surface filtering chip |
| CN110400780A (en) * | 2019-07-23 | 2019-11-01 | 杭州晶通科技有限公司 | A kind of fan-out-type stack package structure and preparation method thereof using metallic conduction post |
| CN110970397A (en) * | 2019-12-19 | 2020-04-07 | 江苏中科智芯集成科技有限公司 | Stack packaging structure and preparation method thereof |
| CN112053962A (en) * | 2020-09-14 | 2020-12-08 | 山东傲天环保科技有限公司 | System-level stack package and preparation method thereof |
| CN112038329A (en) * | 2020-10-12 | 2020-12-04 | 长电集成电路(绍兴)有限公司 | Wafer-level chip fan-out three-dimensional stacking packaging structure and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114899111A (en) * | 2022-04-22 | 2022-08-12 | 宜确半导体（苏州）有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN116169113A (en) * | 2023-04-21 | 2023-05-26 | 江苏芯德半导体科技有限公司 | QFN packaging structure capable of reducing heat conduction to PCB and preparation method thereof |
| CN116169113B (en) * | 2023-04-21 | 2023-08-04 | 江苏芯德半导体科技有限公司 | QFN packaging structure capable of reducing heat conduction to PCB and preparation method thereof |
| CN116960108A (en) * | 2023-09-21 | 2023-10-27 | 江苏展芯半导体技术有限公司 | Chip packaging structure and method |
| CN116960108B (en) * | 2023-09-21 | 2023-12-08 | 江苏展芯半导体技术有限公司 | Chip packaging structure and method |
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