CN114267395B - Programming pulse width adjusting circuit, adjusting method, programming circuit and flash memory - Google Patents
Programming pulse width adjusting circuit, adjusting method, programming circuit and flash memory Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductor integrated circuits, and particularly discloses a programming pulse width regulating circuit, a regulating method, a programming circuit and a flash memory, wherein the regulating circuit comprises: the input module is used for acquiring a programming enable signal en and a first bias voltage signal vbp; the conversion module is used for generating an adjusting signal according to the magnitude of the first bias voltage signal vbp; the output module is used for acquiring the programming current signal pgm_en and the adjusting signal and generating a programming signal pgm_stop according to the adjusting signal and the programming current signal pgm_en; the adjusting circuit generates an adjusting signal according to the magnitude of the first bias voltage signal vbp, and then generates a programming signal pgm_stop according to the adjusting signal reflecting the progress of the programming operation and the programming current signal pgm_en, so that the pulse width of the programming signal pgm_stop for performing the programming operation on the memory cell is adjustable.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuits, and more particularly, to a program pulse width modulation circuit, a program pulse width modulation method, a program circuit, and a flash memory.
Background
The memory cell is programmed by applying a programming voltage, but the pulse width of the programming voltage (abbreviated as programming pulse width) is fixed and not adjustable; the memory cell needs to undergo one-time programming pulse width to complete programming, and after the memory cell completes programming within a certain programming pulse width, the memory cell also needs to wait for the programming pulse width to finish programming operation, thus seriously wasting programming time.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The invention provides a programming pulse width adjusting circuit, an adjusting method, a programming circuit and a flash memory, so that the pulse width of a programming voltage is adjustable, and the programming time of a memory cell is shortened.
In a first aspect, the present application provides a program pulse width modulation circuit for modulating a programming time of a memory cell, the modulation circuit comprising:
the input module is used for acquiring a programming enable signal en and a first bias voltage signal vbp;
the conversion module is used for generating an adjusting signal according to the magnitude of the first bias voltage signal vbp;
and the output module is used for acquiring the programming current signal pgm_en and the regulating signal and generating a programming signal pgm_stop according to the regulating signal and the programming current signal pgm_en.
According to the programming pulse width regulating circuit, the regulating signal is generated according to the magnitude of the first bias voltage signal vbp, and then the programming signal pgm_stop is generated according to the regulating signal capable of reflecting the programming operation progress and the programming current signal pgm_en, so that the pulse width of the programming signal pgm_stop for performing programming operation on the memory cell is adjustable, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being excessively deeply programmed and difficult to erase.
The program pulse width adjusting circuit is characterized in that the program signal pgm_stop is the same as the program current signal pgm_en when the adjusting signal is at high level.
In the programming pulse width modulation circuit of this example, the magnitude of the programming signal pgm_stop is set to be the same as the magnitude of the programming current signal pgm_en, so that it is ensured that the memory cell can smoothly complete the programming operation.
The programming pulse width regulating circuit comprises an input module, wherein the input module comprises a first MOS tube pm1, a second MOS tube nm1, a third MOS tube nm2 and a fourth MOS tube nm3, a source electrode of the first MOS tube pm1 is connected with a power supply voltage VDD, a grid electrode of the first MOS tube pm1 is connected with a programming enabling signal en, a drain electrode of the first MOS tube pm1 is connected with a drain electrode of the second MOS tube nm1, a grid electrode of the second MOS tube nm1 is connected with a first bias voltage signal vbp, a source electrode of the second MOS tube nm1 is connected with a drain electrode and a grid electrode of the third MOS tube nm2, a source electrode of the third MOS tube nm2 is connected with a drain electrode of the fourth MOS tube nm3, a grid electrode of the fourth MOS tube nm3 is connected with the programming enabling signal en, a source electrode of the fourth MOS tube nm3 is grounded, and a drain electrode of the first MOS tube pm1 is connected with the conversion module.
In the programming pulse width modulation circuit of this example, the gate of the first MOS transistor pm1 is connected to the programming enable signal en so that the modulation circuit of the present application can be turned on or off according to the programming enable signal en.
The conversion module comprises a first inverter v1, a second inverter v2 and a third inverter v3, wherein the input end of the first inverter v1 is connected with the input module and the output end of the second inverter v2, the output end of the first inverter v1 is connected with the input end of the second inverter v2 and the input end of the third inverter v3, and the output end of the third inverter v3 is connected with the output module.
In the programming pulse width modulation circuit of this example, the three inverter structures are provided so that the modulation signal is at a high level or a low level, so that the output module can determine whether the programming signal pgm_stop needs to be output according to two conditions of the modulation signal.
The output module comprises a two-input AND gate a1, two input ends of the two-input AND gate a1 are respectively connected with the conversion module and the programming current signal pgm_en, and an output end of the two-input AND gate a1 is used for outputting the programming signal pgm_stop.
The first bias voltage signal vbp is reduced as the programming current required by the memory cell increases.
In a second aspect, the present application further provides a program pulse width adjustment method for adjusting a program time of a memory cell, the adjustment method comprising the steps of:
acquiring a programming enable signal en and a first bias voltage signal vbp;
generating an adjusting signal according to the magnitude of the first bias voltage signal vbp;
a programming current signal pgm_en and the adjustment signal are obtained and a programming signal pgm_stop is generated from the adjustment signal and the programming current signal pgm_en.
According to the programming pulse width adjusting method, the adjusting signal is generated according to the magnitude of the first bias voltage signal vbp, and then the programming signal pgm_stop is generated according to the adjusting signal capable of reflecting the programming operation progress and the programming current signal pgm_en, so that the pulse width of the programming signal pgm_stop for performing programming operation on the memory cell is adjustable, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being excessively deeply programmed and difficult to erase.
In a third aspect, the present application further provides a programming circuit for programming a memory cell, the programming circuit comprising:
a bias circuit for acquiring a program enable signal en and a feedback signal pump_out to generate a first bias voltage signal vbp and a second bias voltage signal vpn;
an oscillator circuit for generating a programming current signal pgm_en from the first bias voltage signal vbp and the second bias voltage signal vpn;
a programming pulse width adjusting circuit, configured to generate a programming signal pgm_stop according to the first bias voltage signal vbp and the programming current signal pgm_en, where the programming signal pgm_stop is used to program a memory cell and make the memory cell generate the feedback signal pump_out;
the programming pulse width modulation circuit includes:
an input module for acquiring the programming enable signal en and the first bias voltage signal vbp;
the conversion module is used for generating an adjusting signal according to the magnitude of the first bias voltage signal vbp;
and the output module is used for acquiring the programming current signal pgm_en and the regulating signal and generating the programming signal pgm_stop according to the regulating signal and the programming current signal pgm_en.
The output end of the output module is connected with the drain end of the storage unit.
According to the programming circuit, the programming pulse width regulating circuit is arranged, the programming pulse width regulating circuit generates the programming signal pgm_stop according to the first bias voltage signal vbp and the programming current signal pgm_en, programming operation is carried out on the storage unit by utilizing the programming signal pgm_stop, and when the storage unit is programmed, the programming signal pgm_stop is turned to 0 to finish the programming operation, namely the pulse width of the programming operation is adapted to the storage unit, so that the pulse width of the programming signal pgm_stop is adjustable, the programming time of the storage unit is effectively shortened, and the storage unit is prevented from being programmed too deeply and being difficult to erase.
In a fourth aspect, the present application further provides a flash memory for data storage, the flash memory comprising the programming circuit of the third aspect.
The flash memory adopts the programming circuit of the third aspect as a programming component, so that the programming voltage is not a fixed pulse width any more, but can be adjusted in real time according to the programming condition of the memory cell, and the programming voltage can be turned to 0 in time when the memory cell completes programming operation, so that the pulse width of the programming voltage is not limited by the original fixed width any more, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being excessively deep in programming and difficult to erase.
As can be seen from the foregoing, the present application provides a program pulse width adjusting circuit, an adjusting method, a program circuit and a flash memory, wherein the adjusting circuit generates an adjusting signal according to the magnitude of a first bias voltage signal vbp, and then generates a program signal pgm_stop according to the adjusting signal capable of reflecting the progress of a program operation and a program current signal pgm_en, so that the pulse width of the program signal pgm_stop for performing the program operation on a memory cell is adjustable, thereby effectively shortening the program time of the memory cell and avoiding the memory cell from being too deeply programmed and difficult to erase.
Drawings
Fig. 1 is a schematic diagram of a structure of a programming pulse width modulation circuit according to an embodiment of the present application.
Fig. 2 is a detailed schematic diagram of a programming pulse width modulation circuit according to an embodiment of the present application.
Fig. 3 is a flowchart of a method for programming pulse width modulation according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a programming circuit according to an embodiment of the present application.
FIG. 5 is a schematic diagram of a prior art programming circuit.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 5, in a programming operation, the bias circuit pgmpump_fb generates corresponding bias voltages vbn and vpb when the enable signal en=1, so that the oscillator circuit pgpump_osc generates corresponding programming currents to program the memory cell pgmpump_cell; the memory cells with different threshold voltages have different requirements for programming current, and are expressed as follows: the lower the threshold voltage of the memory cell, the larger the required programming current, and the higher the threshold voltage of the memory cell, the smaller the required programming current.
The programming circuit of FIG. 5 can adjust the output according to the programming current requirement of the memory cell: when the demand of the memory cell for the programming current is relatively large, pump_out is fed back to pgmpump_fb to adjust vbp to be smaller and vbn to be larger, so that the frequency of pgmpump_osc is increased to output a larger programming current, and otherwise, smaller programming current is output.
The pulse width of the existing programming voltage is fixed and not adjustable, and accordingly, the bias voltage generated in the programming process can reflect the programming progress.
In a first aspect, referring to fig. 1 and 2, in some embodiments of the present application, a program pulse width adjusting circuit for adjusting a program time of a memory cell in fig. 1 and 2 includes:
an input module 101 for acquiring a program enable signal en and a first bias voltage signal vbp;
a conversion module 102, configured to generate an adjustment signal according to the magnitude of the first bias voltage signal vbp;
the output module 103 is configured to obtain the program current signal pgm_en and the adjustment signal, and generate the program signal pgm_stop according to the adjustment signal and the program current signal pgm_en.
Specifically, the program enable signal en is an enable signal generated to determine whether programming of a memory cell is required, that is, when programming of a specific memory cell in the flash memory is required, the corresponding program enable signal en=1, and then the programming operation of the memory cell in the portion is started.
Specifically, the first bias voltage signal vbp is one of signals for adjusting a programming current in a programming circuit of the memory cell; in general, a programming circuit of a memory cell is provided with an oscillator circuit (osc circuit), and the magnitude of an output current of the oscillator circuit is changed by changing a first bias voltage signal vbp and a second bias voltage signal vbn input to the oscillator circuit, so that the magnitude of the programming current is changed, and the memory cell with different threshold voltages can be programmed; the input module 101 is configured to obtain the first bias voltage signal vbp generated for adjusting the oscillator circuit, and generate a corresponding adjustment signal according to the magnitude of the first bias voltage signal vbp.
More specifically, since the first bias voltage signal vbp is mainly used for changing the magnitude of the output current of the oscillator circuit, the first bias voltage signal vbp can reflect the magnitude of the programming current, and the magnitude of the programming current reflects the programming difficulty of the current state of the corresponding memory cell, that is, when the programming current is smaller, the memory cell is easier to program, that is, the programming operation is about to be finished under the current programming current, so that the adjusting signal generated according to the magnitude of the first bias voltage signal vbp can be used for judging whether the programming operation is finished or about to be finished.
More specifically, the output module 103 generates the program signal pgm_stop according to the adjustment signal representing that the program operation is in progress and the program current signal pgm_en, and the output module 103 generates the program signal pgm_stop corresponding to the program current signal pgm_en to program the memory cell, and the adjustment signal representing that the program operation is completed, and the output module 103 immediately interrupts the output of the program signal pgm_stop even though the program signal pgm_stop=0, thereby ending the program operation.
More specifically, the programming circuit of the memory cell outputs the programming current signal pgm_en according to a fixed pulse width, and when the memory cell just completes programming, the programming current signal pgm_en is still not flipped to 0.
More specifically, other operations on memory cells in a flash memory may confirm the programmed state of the memory cells by acquiring a program signal pgm_stop.
According to the programming pulse width regulating circuit, the regulating signal is generated according to the magnitude of the first bias voltage signal vbp, and then the programming signal pgm_stop is generated according to the regulating signal capable of reflecting the programming operation progress and the programming current signal pgm_en, so that the pulse width of the programming signal pgm_stop for programming the memory cell is adjustable, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being excessively deep in programming and difficult to erase.
In some preferred embodiments, the program signal pgm_stop is the same magnitude as the program current signal pgm_en when the adjustment signal is high.
Specifically, the existing programming current signal pgm_en is a programming current generated by the oscillator circuit for programming the memory cell, and the magnitude of the programming current signal pgm_en is automatically adjusted according to the programming difficulty of the memory cell.
In some preferred embodiments, the input module 101 includes a first MOS transistor pm1, a second MOS transistor nm1, a third MOS transistor nm2, and a fourth MOS transistor nm3, where the source of the first MOS transistor pm1 is connected to the power supply voltage VDD, the gate of the first MOS transistor pm1 is connected to the programming enable signal en, the drain of the first MOS transistor pm1 is connected to the drain of the second MOS transistor nm1, the gate of the second MOS transistor nm1 is connected to the first bias voltage signal vbp, the source of the second MOS transistor nm1 is connected to the drain and gate of the third MOS transistor nm2, the source of the third MOS transistor nm2 is connected to the drain of the fourth MOS transistor nm3, the gate of the fourth MOS transistor nm3 is connected to the programming enable signal en, the source of the fourth MOS transistor nm3 is grounded, and the drain of the first MOS transistor pm1 is connected to the conversion module 102.
Specifically, the gate of the first MOS transistor pm1 is connected to the programming enable signal en, so that the adjusting circuit in the embodiment of the present application can be started or closed according to the programming enable signal en, for example, when en=1, the input module 101 is turned on to start, obtain the first bias voltage signal vbp, and generate a corresponding adjusting signal in cooperation with the conversion module 102.
In some preferred embodiments, the conversion module 102 includes a first inverter v1, a second inverter v2, and a third inverter v3, the first inverter v1 input is connected to the input module 101 and the second inverter v2 output, the first inverter v1 output is connected to the second inverter v2 input and the third inverter v3 input, and the third inverter v3 output is connected to the output module 103.
Specifically, as shown in fig. 2, the level generated at B is the adjustment signal, and the three inverter structures are configured to make the adjustment signal be at a high level or a low level, so that the output module 103 can determine whether the program signal pgm_stop needs to be output according to two conditions of the adjustment signal.
More specifically, since the current level at a varies with the magnitude of the first bias voltage signal vbp, and the more stable adjustment signal needs to be generated at B to be supplied to the output module 103 for judgment, a plurality of inverters are provided to generate the adjustment signal that appears as a high level or a low level according to the magnitude of the first bias voltage signal vbp.
More specifically, when the adjustment signal is high, the output module 103 generates the programming signal pgm_stop from the programming current signal pgm_en; when the adjustment signal is low, the output module 103 inverts the program signal pgm_stop to 0, thereby ending the program operation.
More specifically, when the demand of the memory cell for the programming current is relatively large, the oscillator circuit needs to input a smaller first bias voltage signal vbp and a larger second bias voltage signal vbn to increase the frequency to generate a larger programming current, and thus the first bias voltage signal vbp in the programming operation is a relatively smaller current value than the first bias voltage signal vbp at the time of the programming operation to be completed; in the programming operation, if the memory cell does not complete the programming operation, the first bias voltage signal vbp is a relatively small current value, no discharge is generated at the a position, and the conversion module 102 keeps the B position level to be 1 according to the a position level, so that the output module 103 generates the programming signal pgm_stop according to the programming current signal pgm_en; when the memory cell completes programming, the whole programming operation is still in the original fixed pulse width, but the first bias voltage signal vbp accessed by the oscillator circuit will become larger, and the point a will be discharged to 0 because the first bias voltage signal vbp is a relatively larger current value, the conversion module 102 will flip the level at B to 0 according to the level at a, and the output module 103 will flip the programming signal pgm_stop to 0 even if the programming current signal pgm_en still exists, so as to end the programming operation on the memory cell in time and end the programming pulse width.
In some preferred embodiments, the output module 103 includes a two-input and gate a1, where two inputs of the two-input and gate a1 are respectively connected to the conversion module 102 and the programming current signal pgm_en, and an output of the two-input and gate a1 is used for outputting the programming signal pgm_stop.
Specifically, when the adjustment signal is expression 1, the two-input and gate a1 outputs the program current signal pgm_en as the program signal pgm_stop; when the adjustment signal is 0, the two-input AND gate a1 outputs 0.
In some preferred embodiments, the first bias voltage signal vbp decreases as the programming current required for the memory cell increases, whereas the first bias voltage signal vbp increases as the programming current required for the memory cell decreases.
In a second aspect, referring to fig. 3, fig. 3 is a programming pulse width adjusting method for adjusting a programming time of a memory cell according to some embodiments of the present application, the adjusting method includes the following steps:
s1, acquiring a programming enabling signal en and a first bias voltage signal vbp;
s2, generating an adjusting signal according to the magnitude of the first bias voltage signal vbp;
s3, acquiring a programming current signal pgm_en and an adjusting signal, and generating a programming signal pgm_stop according to the adjusting signal and the programming current signal pgm_en.
According to the programming pulse width adjusting method, the adjusting signal is generated according to the magnitude of the first bias voltage signal vbp, and then the programming signal pgm_stop is generated according to the adjusting signal capable of reflecting the programming operation progress and the programming current signal pgm_en, so that the pulse width of the programming signal pgm_stop for performing programming operation on the memory cell is adjustable, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being excessively deep in programming and difficult to erase.
In a third aspect, referring to fig. 4, fig. 4 is a programming circuit provided in some embodiments of the present application for programming a memory cell, the programming circuit includes:
a bias circuit 200 for acquiring a program enable signal en and a feedback signal pump_out to generate a first bias voltage signal vbp and a second bias voltage signal vpn;
an oscillator circuit 300 for generating a programming current signal pgm_en from the first bias voltage signal vbp and the second bias voltage signal vpn;
a programming pulse width adjustment circuit 100 for generating a programming signal pgm_stop for programming the memory cell and causing the memory cell to generate a feedback signal pump_out according to the first bias voltage signal vbp and the programming current signal pgm_en;
the programming pulse width modulation circuit 100 includes:
an input module 101 for acquiring a program enable signal en and a first bias voltage signal vbp;
a conversion module 102, configured to generate an adjustment signal according to the magnitude of the first bias voltage signal vbp;
the output module 103 is configured to obtain the program current signal pgm_en and the adjustment signal, and generate the program signal pgm_stop according to the adjustment signal and the program current signal pgm_en.
Specifically, when performing a programming operation on a memory cell, the programming enable signal en=1, so that the bias circuit 200 generates the first bias voltage signal vbp and the second bias voltage signal vpn, the oscillator circuit 300 changes the oscillation frequency according to the first bias voltage signal vbp and the second bias voltage signal vpn to generate a corresponding magnitude of programming current signal pgm_en, the programming pulse width adjustment circuit 100 generates the programming signal pgm_stop according to the first bias voltage signal vbp and the programming current signal pgm_en, the memory cell is programmed by using the programming signal pgm_stop, during the programming operation, the memory cell generates and outputs a feedback signal pump_out, the feedback signal pump_out can reflect the programming progress of the memory cell, the bias circuit 200 acquires the feedback signal pump_out, and adjusts the first bias voltage signal vbp and the second bias voltage signal vpn according to change the magnitude of the programming current signal pgm_en, and the programming pulse width adjustment circuit 100 programs the memory cell, such that when the feedback signal pump_out reflects the memory cell has a larger magnitude, the bias circuit 200 increases the bias current signal vpp_out by a larger magnitude than the bias voltage signal pgm_en.
According to the programming circuit, the programming pulse width adjusting circuit 100 is arranged, the programming pulse width adjusting circuit 100 generates the programming signal pgm_stop according to the first bias voltage signal vbp and the programming current signal pgm_en, programming operation is carried out on the memory cell by utilizing the programming signal pgm_stop, and when the memory cell is programmed, the programming signal pgm_stop is turned to 0 to finish the programming operation, namely the pulse width of the programming operation is adapted to the memory cell, so that the pulse width of the programming signal pgm_stop is adjustable, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being programmed too deeply to be difficult to erase.
In some preferred embodiments, the output of output module 103 is coupled to a memory cell drain.
Specifically, the output module 103 applies the program signal pgm_stop to the memory cell drain to perform a program operation on the memory cell.
In a fourth aspect, some embodiments of the present application further provide a flash memory for data storage, the flash memory including the programming circuit of the third aspect.
Specifically, the programming process of flash memory is usually to program an entire page at the same time; the programming process generally uses a voltage pulse with a fixed pulse width as programming voltage, controls electrons in a channel of a memory cell to be programmed to pass through a floating gate under the action of a strong electric field, and after the programming voltage is cancelled, a certain electric field exists in a clock in the memory cell to be programmed, so that the starting voltage of a device is changed to realize data storage; the flash memory of the embodiment of the application adopts the programming circuit of the third aspect as the programming component, so that the programming voltage is not a fixed pulse width any more, but can be adjusted in real time according to the programming condition of the memory cell, when the memory cell completes the programming operation, the programming voltage can be turned over to 0 (i.e. the programming signal pgm_stop is turned over to 0) in time, the pulse width of the programming voltage is not limited to the original fixed width any more, the programming time of the memory cell is effectively shortened, and the memory cell is prevented from being excessively deep in programming and difficult to erase.
In summary, the embodiments of the present application provide a program pulse width adjusting circuit, an adjusting method, a program circuit, and a flash memory, where the adjusting circuit generates an adjusting signal according to a magnitude of a first bias voltage signal vbp, and then generates a program signal pgm_stop according to the adjusting signal capable of reflecting a program operation progress and a program current signal pgm_en, so that a pulse width of the program signal pgm_stop for performing a program operation on a memory cell is adjustable, thereby effectively shortening a program time of the memory cell and avoiding that the memory cell is too deeply programmed and difficult to erase.
In the embodiments provided herein, it should be understood that the disclosed circuits and methods may be implemented in other ways. The above-described circuit embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, circuit or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (7)
1. A programming pulse width modulation circuit for adjusting a programming time of a memory cell, the modulation circuit comprising:
the memory device comprises an input module, a first bias voltage signal vbp and a second bias voltage signal vbp, wherein the input module is used for acquiring a programming enabling signal en and a first bias voltage signal vbp, the programming enabling signal en is an enabling signal generated by judging whether a memory cell needs to be programmed or not, the first bias voltage signal vbp is one of signals for adjusting programming current in a programming circuit of the memory cell, and the first bias voltage signal vbp is reduced along with the increase of the programming current required by the memory cell;
the conversion module is used for generating an adjusting signal according to the magnitude of the first bias voltage signal vbp;
the output module is used for acquiring a programming current signal pgm_en and the adjusting signal and generating a programming signal pgm_stop according to the adjusting signal and the programming current signal pgm_en;
the input module comprises a first MOS tube pm1, a second MOS tube nm1, a third MOS tube nm2 and a fourth MOS tube nm3, wherein a source electrode of the first MOS tube pm1 is connected with a power supply voltage VDD, a grid electrode of the first MOS tube pm1 is connected with a programming enabling signal en, a drain electrode of the first MOS tube pm1 is connected with a drain electrode of the second MOS tube nm1, a grid electrode of the second MOS tube nm1 is connected with a first bias voltage signal vbp, a source electrode of the second MOS tube nm1 is connected with a drain electrode and a grid electrode of the third MOS tube nm2, a source electrode of the third MOS tube nm2 is connected with a drain electrode of the fourth MOS tube nm3, a grid electrode of the fourth MOS tube nm3 is connected with the programming enabling signal en, a source electrode of the fourth MOS tube nm3 is grounded, and a drain electrode of the first MOS tube pm1 is connected with the conversion module.
2. The programming pulse width modulation circuit of claim 1, wherein the programming signal pgm_stop is the same magnitude as the programming current signal pgm_en when the modulation signal is high.
3. The programming pulse width modulation circuit of claim 1, wherein the conversion module comprises a first inverter v1, a second inverter v2, and a third inverter v3, wherein the first inverter v1 input is connected to the input module and the second inverter v2 output, wherein the first inverter v1 output is connected to the second inverter v2 input and the third inverter v3 input, and wherein the third inverter v3 output is connected to the output module.
4. The circuit according to claim 1, wherein the output module includes a two-input and gate a1, two input ends of the two-input and gate a1 are respectively connected to the conversion module and the programming current signal pgm_en, and an output end of the two-input and gate a1 is used for outputting the programming signal pgm_stop.
5. A programming circuit for programming a memory cell, the programming circuit comprising:
a bias circuit for acquiring a program enable signal en and a feedback signal pump_out to generate a first bias voltage signal vbp and a second bias voltage signal vpn;
an oscillator circuit for generating a programming current signal pgm_en from the first bias voltage signal vbp and the second bias voltage signal vpn;
a programming pulse width adjusting circuit, configured to generate a programming signal pgm_stop according to the first bias voltage signal vbp and the programming current signal pgm_en, where the programming signal pgm_stop is used to program a memory cell and make the memory cell generate the feedback signal pump_out;
the programming pulse width modulation circuit includes:
an input module, configured to acquire the program enable signal en and the first bias voltage signal vbp, where the program enable signal en is an enable signal generated for determining whether programming of a memory cell is required, the first bias voltage signal vbp is one of signals for adjusting a program current in a program circuit of the memory cell, and the first bias voltage signal vbp decreases as a program current required by the memory cell increases;
the conversion module is used for generating an adjusting signal according to the magnitude of the first bias voltage signal vbp;
the output module is used for acquiring the programming current signal pgm_en and the adjusting signal and generating the programming signal pgm_stop according to the adjusting signal and the programming current signal pgm_en;
the input module comprises a first MOS tube pm1, a second MOS tube nm1, a third MOS tube nm2 and a fourth MOS tube nm3, wherein a source electrode of the first MOS tube pm1 is connected with a power supply voltage VDD, a grid electrode of the first MOS tube pm1 is connected with a programming enabling signal en, a drain electrode of the first MOS tube pm1 is connected with a drain electrode of the second MOS tube nm1, a grid electrode of the second MOS tube nm1 is connected with a first bias voltage signal vbp, a source electrode of the second MOS tube nm1 is connected with a drain electrode and a grid electrode of the third MOS tube nm2, a source electrode of the third MOS tube nm2 is connected with a drain electrode of the fourth MOS tube nm3, a grid electrode of the fourth MOS tube nm3 is connected with the programming enabling signal en, a source electrode of the fourth MOS tube nm3 is grounded, and a drain electrode of the first MOS tube pm1 is connected with the conversion module.
6. The programming circuit of claim 5, wherein the output module output is coupled to the memory cell drain.
7. A flash memory for data storage, characterized in that the flash memory comprises the programming circuit of claim 5 or 6.
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| CN106468931A (en) * | 2015-08-17 | 2017-03-01 | 赵智达 | A kind of anti-fuse type FPGA bias voltage circuit |
| CN110956994B (en) * | 2019-11-27 | 2021-10-22 | 西安紫光国芯半导体有限公司 | Programming result detection circuit, detection method, flash memory and programming method |
| CN113162566B (en) * | 2021-05-17 | 2022-12-06 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
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