CN114265335A - Fault injection simulation method for battery cell management chip - Google Patents
Fault injection simulation method for battery cell management chip Download PDFInfo
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Abstract
The invention discloses a fault injection simulation method for a battery cell management chip. The method comprises the following steps: the simulator is powered on to initialize and carry out self-checking; the simulator enters a state of waiting for connection synchronization with a host to be tested and transmitting fault types; the simulator waits for the host to be tested to start testing, and the host to be tested starts to run a program to be tested; the simulator analyzes the message state after receiving a frame of complete message; and determining whether to send the message according to the message analysis result. The invention solves the problem of synchronous connection between the tested host and the simulator through SPI communication; the problem of receiving and losing frames of SPI messages of a simulator is solved by setting a frame loss prevention mechanism, and the simulation of fault injection of a battery management chip is realized on the basis; the simulation system can simulate different types of battery management chips, can also simulate a multi-node network consisting of a plurality of battery management chips, and meets the test requirements in the fields of electric/intelligent automobiles, energy storage and uninterruptible power supplies.
Description
Technical Field
The invention belongs to the technical field of software development, and particularly relates to a fault injection simulation method for a battery cell management chip.
Background
A Battery Cell management Chip (Battery Cell Chip) is one of the core components of a Battery management system, and has a key role in collecting the voltage, current, temperature and the like of a Battery Cell. When designing the software and hardware of the battery management system, in order to improve the safety level and reliability of the system, it is necessary to consider that a battery cell management chip may have a fault, and the battery management system needs a targeted software and hardware design to cope with the fault.
The electronic technology is adopted to simulate the action of injecting faults into the battery management chip, and the common method adopts an FPGA scheme. The scheme simulates the battery management chip by a hardware method, and has the defects of inflexible fault injection, large occupied hardware resources when simulating multiple nodes and low cost performance.
However, if the FPGA scheme is not adopted, and the single chip microcomputer scheme is adopted, although flexible node number increase and fault injection are easily realized, other technical difficulties are faced: due to the characteristics of the SPI communication, a connection synchronization mechanism is not provided, and a slave serving as a simulator is difficult to keep synchronous connection with a host, which causes that once the host and the slave are out of synchronization in a test (which is reflected in that data malposition occurs in RAM receiving buffers of the host and the slave), it is difficult to judge whether the host or the slave loses frames, and a correct result cannot be obtained in the test. When a pressure test scene is simulated, a tested host needs to send and receive multi-frame SPI messages in a short time, and a slave serving as a simulator adopts a single chip microcomputer as a hardware control core, so that the problem of frame loss in the process of receiving and processing the SPI messages at a high speed is difficult to solve.
Disclosure of Invention
The invention aims to provide a battery cell management chip fault injection simulation method, which solves the problem of synchronous connection between a tested host and a simulator through SPI communication; the problem of receiving and losing frames of SPI messages of a simulator is solved by setting a frame loss prevention mechanism, and the simulation of fault injection of a battery management chip is realized on the basis; the simulation system can simulate different types of battery management chips, can also simulate a multi-node network consisting of a plurality of battery management chips, and meets the test requirements in the fields of electric/intelligent automobiles, energy storage and uninterruptible power supplies.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention relates to a fault injection simulation method for a battery cell management chip, which comprises the following steps:
firstly, electrifying a simulator for initialization and performing self-checking; after self-checking is carried out, entering a step two;
step two, the simulator enters a state of waiting for connection synchronization with the host to be tested and transmitting fault types; entering a third step after connection synchronization and transmission failure are completed; the simulator is in communication connection with a host to be tested through the SPI; wherein the fault type includes one or more of an ADC fault, an SPI communication fault, and a passive or active equalization fault;
step three, the simulator waits for the host to be tested to start testing, and the host to be tested starts to run a program to be tested;
step four, the simulator analyzes the message state after receiving a frame of complete message; determining whether to send the message or not according to the message analysis result; if the message is meaningful and the self-checking of the analog machine has no fault, entering the fifth step; if the self-checking is faulty or the fault-tolerant operation of the host computer is found to be faulty according to the message, entering the seventh step;
step five, the simulator carries out a fault injection working state, and if the fault injection is finished, the simulator returns to the step three if the simulator does not need to send a message to the host to be tested; entering a sixth step if the message needs to be sent;
step six, the simulator enters a message sending state and sends a message to the host to be tested; returning to the third step after the message is successfully sent; if the self-check is failure-free, the message can not be successfully sent and the fault-tolerant operation of the host computer is found to be problematic according to the message, entering the seventh step;
and step seven, the simulator enters a shutdown alarm state.
Preferably, the second step comprises the following substeps:
stp21, the host to be tested sends a synchronous connection message to the simulator, and the simulator responds after receiving the message;
the Stp22 and the host to be tested send a message containing the injected fault type content to the simulator after receiving the response, and the simulator completes the fault injection setting after receiving the message and sends a ready response;
and after the host to be tested receives the response again, the Stp22 can start the test.
Preferably, the simulator in the second step simulates the fault of inaccurate AD sampling by adding deviation amount to the accurate sampling values of voltage, current, temperature and the like acquired from the AD peripheral of the MCU or the external AD chip;
the simulator simulates various communication delay faults caused by delay by adding delay in a program.
Preferably, the simulator in step four judges whether the fault-tolerant operation of the host computer has a problem by checking whether a place which does not conform to the communication format of the host computer and the battery cell management chip exists in the received SPI message or checking whether the content of the received SPI message conforms to a fault-tolerant policy.
Preferably, an anti-lost frame mechanism is arranged for SPI communication between the simulator and the host to be tested, the simulator starts SPI receiving interruption, and the interruption type is set to trigger interruption if an SPI peripheral receiving interruption buffer area is not empty; after the test is started, the simulator completes the receiving, analysis and sending of the SPI message according to the following procedures:
SS01, setting Counter1 to 0, and entering step SS 02;
SS02, the slave MCU waits to enter the SPI to receive the interrupt service program, and the entering step enters the step SS 03;
SS03, the tested host sends SPI message to the slave, the MCU of the slave runs into SPI receiving interrupt service program, and then step SS04 is carried out;
SS04, in SPI reception interrupt service procedure, checking SPI peripheral equipment received message byte Counter0, if Counter0 is not 0 and is less than one frame message length, then moving each received byte to RAM buffer, each time moving one byte, Counter0 subtracting 1, Counter1 adding 1; if the Counter0 is not 0 and is equal to the length of one frame of message, starting the analysis of the message and entering the step SS 05; if Counter0 is 0, go to step SS 02;
and the SS05 completes the analysis of the message according to the injection fault type, sends the AD sampling value to the host, resets the Counter1 to 0, and repeats the step SS 04.
The invention has the following beneficial effects:
the invention solves the problem of synchronous connection between the tested host and the simulator through SPI communication; the problem of receiving and losing frames of SPI messages of a simulator is solved by setting a frame loss prevention mechanism, and the simulation of fault injection of a battery management chip is realized on the basis; the simulation test system can simulate different types of battery management chips and also can simulate a multi-node network consisting of a plurality of battery management chips, thereby meeting the test requirements in the fields of electric/intelligent automobiles, energy storage and uninterrupted power supplies; the method is low in cost and is easier to realize than an FPGA scheme.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for simulating fault injection of a battery cell management chip according to the present invention;
fig. 2 is a flow chart of a frame loss prevention mechanism of a battery cell management chip fault injection simulation method.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, the present invention is a method for simulating fault injection of a battery cell management chip, including the following steps:
firstly, electrifying a simulator for initialization and performing self-checking; after self-checking is carried out, entering a step two;
step two, the simulator enters a state of waiting for connection synchronization with the host to be tested and transmitting fault types; entering a third step after connection synchronization and transmission failure are completed; the simulator is in communication connection with a host to be tested through the SPI; the fault type includes one or more of an ADC fault, an SPI communication fault, and a passive or active equalization fault;
wherein, step two includes the following substeps:
stp21, the host to be tested sends synchronous connection message to the simulator, the simulator receives the message and then responds;
stp22, after receiving the response, the host to be tested sends a message containing the content of the injected fault types to the simulator, and after receiving the message, the simulator completes the fault injection setting and sends a ready response;
stp22, after the host computer to be tested receives the response again, the test can be started;
the simulator simulates the failure of inaccurate AD sampling by adding deviation amount to accurate sampling values of voltage, current, temperature and the like acquired from an AD peripheral of the MCU or an external AD chip; the simulator simulates various communication delay faults caused by delay by adding delay in a program;
step three, the simulator waits for the host to be tested to start testing, and the host to be tested starts to run a program to be tested;
step four, the simulator analyzes the message state after receiving a frame of complete message; determining whether to send the message or not according to the message analysis result; if the message is meaningful and the self-checking of the analog machine has no fault, entering the fifth step; if the self-checking is faulty or the fault-tolerant operation of the host computer is found to be faulty according to the message, entering the seventh step;
step five, the simulator carries out a fault injection working state, and if the fault injection is finished, the simulator returns to the step three if the message does not need to be sent to the host to be tested; entering a sixth step if the message needs to be sent;
step six, the simulator enters a message sending state and sends a message to the host to be tested; returning to the third step after the message is successfully sent; if the self-check is failure-free, the message can not be successfully sent and the fault-tolerant operation of the host computer is found to be problematic according to the message, entering the seventh step;
and step seven, the simulator enters a shutdown alarm state.
Example two:
the simulator in the fourth step judges whether the fault-tolerant operation of the host computer has problems by checking whether the received SPI message has a place which does not accord with the communication format of the host computer and the battery cell management chip or checking whether the content of the received SPI message accords with a fault-tolerant strategy; the simulator judges the self running state according to the relation between the receiving frame number and the sending frame number obtained by real-time detection, and if the simulator breaks down, the simulator is stopped and gives an alarm.
Example three:
as shown in fig. 2, an anti-lost frame mechanism is provided for SPI communication between the simulator and the host to be tested, the simulator starts SPI reception interrupt, and sets the interrupt type as that interrupt is triggered if the SPI peripheral reception interrupt buffer is not empty; after the test is started, the simulator completes the receiving, analysis and sending of the SPI message according to the following procedures:
SS01, setting Counter1 to 0, and entering step SS 02;
SS02, the slave MCU waits to enter the SPI to receive the interrupt service program, and the entering step enters the step SS 03;
SS03, the tested host sends SPI message to the slave, the MCU of the slave runs into SPI receiving interrupt service program, and then step SS04 is carried out;
SS04, in SPI reception interrupt service procedure, checking SPI peripheral equipment received message byte Counter0, if Counter0 is not 0 and is less than one frame message length, then moving each received byte to RAM buffer, each time moving one byte, Counter0 subtracting 1, Counter1 adding 1; if the Counter0 is not 0 and is equal to the length of one frame of message, starting the analysis of the message and entering the step SS 05; if Counter0 is 0, go to step SS 02;
and the SS05 completes the analysis of the message according to the injection fault type, sends the AD sampling value to the host, resets the Counter1 to 0, and repeats the step SS 04.
Example four:
the simulator increases the number of slave node entities needing simulation by occupying larger RAM space, can simulate different slave node topologies, can simulate different types of battery cell management chip functions in the same topology, and can inject faults into different slave nodes and complete monitoring respectively.
Example five:
in this embodiment, the MC33771 is adopted as a simulated battery cell management chip, and there are two faults to be injected:
1. MC33771 has intermittent fault to voltage acquisition of two sections of battery cells, and shows that the deviation between the voltage acquisition value and the true value is larger than the maximum value stated in the specification, and the maximum deviation is set to be plus or minus 1 mV;
2. an SPI communication fault with unknown reasons exists between the MC33771 and the host to be tested, and the SPI communication fault is shown in that the host to be tested can not normally receive messages from the MC33771 sometimes;
performing fault injection simulation, comprising the following steps:
before the simulation starts, accessing 14 battery cores to a simulator according to a real application scene; the voltage acquisition module of the simulator is calibrated by high-precision voltage measurement equipment, so that the deviation between the voltage acquisition module and a true value is extremely small, and the influence on a test result in the fault injection process can be ignored.
Installing a tested host machine into a simulator, and connecting an SPI communication cable between the tested host machine and the simulator; the tested host and the simulator adopt independent power supply respectively;
after a host to be tested and a simulator are respectively electrified, the host sends a connection synchronous message with the length of 2 bytes to the simulator; the format of the connection synchronization message is as follows:
the first byte represents the node number to be addressed, the range is 0x 01-0 xFE, only 1 MC33771 node is provided, and the first byte is 0x 01;
the second byte is 0xFE, which represents the connection request;
after the simulator normally receives the message, if the simulator considers that the initialization is finished at the moment, the simulator sends a connection normal response 0 xFF; if not, an abnormal response 0x00 is sent.
The host to be tested receives the normal response, namely sends an injection fault type message of 2 bytes;
the message format for transmitting the fault types is as follows:
the first byte, which represents the node number to be addressed, here 0x 01;
the second byte represents the fault category to be injected, here 0x 02;
the simulator receives a message containing the injected fault type content, namely, the preparation work before the test is finished, and after all the preparation work is ready, a normal response 0xFF is sent; otherwise an abnormal response 0x00 is sent.
After receiving the normal response, the host to be tested starts to run the program to be tested;
when a complete message (6 bytes) of a frame is received, the simulator analyzes the message and determines whether to send the message according to the message analysis result;
if the voltages of the two battery cells with the faults need to be inquired at the moment, the simulator adds the deviation value to the acquired voltage value and sends the voltage value to the host to be tested, and then the AD acquisition faults can be simulated; by randomly stopping sending the acquired voltage value, the SPI communication fault can be simulated;
because the running process of the simulator at the stages of analyzing and sending the message consumes controllable time, the frame loss phenomenon can be completely eliminated by combining the frame loss prevention method as long as the time is ensured not to exceed the transmission interval time of two adjacent bytes;
in the test process, the simulator is guaranteed to obtain the message bytes from the SPI peripheral receiving interrupt buffer zone at the highest priority, the time complexity can be quantitatively analyzed, the processing logic is clear, and the occupied hardware resources are few, so that the frame loss problem which is possibly generated is completely avoided in the test requirement range, namely, in the test process, the simulator can normally receive the SPI message sent by the host, and the generated test result does not need to be considered to be influenced by the frame loss of the SPI message; if the received message has a problem, it can clearly define that the host side has a fault from the logic analysis.
It should be noted that, in the above system embodiment, each included unit is only divided according to functional logic, but is not limited to the above division as long as the corresponding function can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
In addition, it can be understood by those skilled in the art that all or part of the steps in the method for implementing the embodiments described above can be implemented by instructing the relevant hardware through a program, and the corresponding program can be stored in a computer-readable storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, or the like.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (5)
1. A battery electric core management chip fault injection simulation method comprises the following steps:
firstly, electrifying a simulator for initialization and performing self-checking; after self-checking is carried out, entering a step two;
step two, the simulator enters a state of waiting for connection synchronization with the host to be tested and transmitting fault types; entering a third step after connection synchronization and transmission failure are completed;
the simulator is in communication connection with a host to be tested through the SPI;
wherein the fault type includes one or more of an ADC fault, an SPI communication fault, and a passive or active equalization fault;
step three, the simulator waits for the host to be tested to start testing, and the host to be tested starts to run a program to be tested;
step four, the simulator analyzes the message state after receiving a frame of complete message; determining whether to send the message or not according to the message analysis result;
if the message is meaningful and the self-checking of the analog machine has no fault, entering the fifth step;
if the self-checking is faulty or the fault-tolerant operation of the host computer is found to be faulty according to the message, entering the seventh step;
step five, the simulator carries out a fault injection working state, and if the fault injection is finished, the simulator returns to the step three if the simulator does not need to send a message to the host to be tested; entering a sixth step if the message needs to be sent;
step six, the simulator enters a message sending state and sends a message to the host to be tested; returning to the third step after the message is successfully sent; if the self-check is failure-free, the message can not be successfully sent and the fault-tolerant operation of the host computer is found to be problematic according to the message, entering the seventh step;
and step seven, the simulator enters a shutdown alarm state.
2. The battery cell management chip fault injection simulation method of claim 1, wherein the second step includes the following substeps:
stp21, the host to be tested sends a synchronous connection message to the simulator, and the simulator responds after receiving the message;
the Stp22 and the host to be tested send a message containing the injected fault type content to the simulator after receiving the response, and the simulator completes the fault injection setting after receiving the message and sends a ready response;
and after the host to be tested receives the response again, the Stp22 can start the test.
3. The method for simulating fault injection of the battery electric core management chip according to claim 1, wherein in the second step, the simulator simulates the fault of inaccurate AD sampling by adding deviation amount to the accurate sampling values of voltage, current, temperature and the like acquired from an AD peripheral of the MCU or an external AD chip;
the simulator simulates various communication delay faults caused by delay by adding delay in a program.
4. The battery cell management chip fault injection simulation method according to claim 1, wherein the simulator in step four judges whether there is a problem in the fault-tolerant operation of the host by checking whether there is a place where the received SPI message does not conform to the communication format between the host and the battery cell management chip or whether the content of the received SPI message conforms to a fault-tolerant policy.
5. The battery electric core management chip fault injection simulation method according to claim 1, characterized in that an anti-frame-loss mechanism is provided for SPI communication between the simulator and a host to be tested, the simulator starts SPI reception interruption, and the interruption type is set as that the SPI peripheral reception interruption buffer is triggered to be interrupted if not empty; after the test is started, the simulator completes the receiving, analysis and sending of the SPI message according to the following procedures:
SS01, setting Counter1 to 0, and entering step SS 02;
SS02, the slave MCU waits to enter the SPI to receive the interrupt service program, and the entering step enters the step SS 03;
SS03, the tested host sends SPI message to the slave, the MCU of the slave runs into SPI receiving interrupt service program, and then step SS04 is carried out;
SS04, in SPI reception interrupt service procedure, checking SPI peripheral equipment received message byte Counter0, if Counter0 is not 0 and is less than one frame message length, then moving each received byte to RAM buffer, each time moving one byte, Counter0 subtracting 1, Counter1 adding 1; if the Counter0 is not 0 and is equal to the length of one frame of message, starting the analysis of the message and entering the step SS 05; if Counter0 is 0, go to step SS 02;
and the SS05 completes the analysis of the message according to the injection fault type, sends the AD sampling value to the host, resets the Counter1 to 0, and repeats the step SS 04.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187802A (en) * | 2012-07-12 | 2013-07-03 | 深圳市康必达中创科技有限公司 | Fault tolerance testing method for simulation system of digital transformer substation |
| CN103543640A (en) * | 2013-09-30 | 2014-01-29 | 广东电网公司电力科学研究院 | Test system for battery management system |
| CN106291427A (en) * | 2016-08-05 | 2017-01-04 | 合肥工业大学 | Battery management system BMS fault self-diagnosis function test platform and method of testing |
| CN108737187A (en) * | 2018-05-23 | 2018-11-02 | 哈尔滨工业大学 | A kind of CAN bus fault simulation system and failure simulation method |
| CN109240277A (en) * | 2018-11-13 | 2019-01-18 | 重庆长安汽车股份有限公司 | Control system diagnostic function real steering vectors automate platform and test method |
| US20200088893A1 (en) * | 2018-07-27 | 2020-03-19 | Triad National Security, Llc | Seismic detection switch |
| CN110928275A (en) * | 2019-12-12 | 2020-03-27 | 重庆长安新能源汽车科技有限公司 | Multi-controller combined HIL (high-level hierarchical level) rack message frame loss fault injection test system and method |
| CN112422951A (en) * | 2020-10-14 | 2021-02-26 | 北京三快在线科技有限公司 | Fault injection method and device, storage medium and electronic equipment |
| CN213457287U (en) * | 2020-11-16 | 2021-06-15 | 合肥华宇智航动力能源有限公司 | Battery management system test system |
| CN113253700A (en) * | 2021-04-14 | 2021-08-13 | 合肥国轩高科动力能源有限公司 | Hardware-in-loop closed-loop test method and system for battery management system |
-
2021
- 2021-09-18 CN CN202111119317.3A patent/CN114265335B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187802A (en) * | 2012-07-12 | 2013-07-03 | 深圳市康必达中创科技有限公司 | Fault tolerance testing method for simulation system of digital transformer substation |
| CN103543640A (en) * | 2013-09-30 | 2014-01-29 | 广东电网公司电力科学研究院 | Test system for battery management system |
| CN106291427A (en) * | 2016-08-05 | 2017-01-04 | 合肥工业大学 | Battery management system BMS fault self-diagnosis function test platform and method of testing |
| CN108737187A (en) * | 2018-05-23 | 2018-11-02 | 哈尔滨工业大学 | A kind of CAN bus fault simulation system and failure simulation method |
| US20200088893A1 (en) * | 2018-07-27 | 2020-03-19 | Triad National Security, Llc | Seismic detection switch |
| CN109240277A (en) * | 2018-11-13 | 2019-01-18 | 重庆长安汽车股份有限公司 | Control system diagnostic function real steering vectors automate platform and test method |
| CN110928275A (en) * | 2019-12-12 | 2020-03-27 | 重庆长安新能源汽车科技有限公司 | Multi-controller combined HIL (high-level hierarchical level) rack message frame loss fault injection test system and method |
| CN112422951A (en) * | 2020-10-14 | 2021-02-26 | 北京三快在线科技有限公司 | Fault injection method and device, storage medium and electronic equipment |
| CN213457287U (en) * | 2020-11-16 | 2021-06-15 | 合肥华宇智航动力能源有限公司 | Battery management system test system |
| CN113253700A (en) * | 2021-04-14 | 2021-08-13 | 合肥国轩高科动力能源有限公司 | Hardware-in-loop closed-loop test method and system for battery management system |
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