CN114256108A - Wafer screening method - Google Patents

Wafer screening method Download PDF

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Publication number
CN114256108A
CN114256108A CN202111547477.8A CN202111547477A CN114256108A CN 114256108 A CN114256108 A CN 114256108A CN 202111547477 A CN202111547477 A CN 202111547477A CN 114256108 A CN114256108 A CN 114256108A
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wafer
packaged
risk
chip
position information
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Chinese (zh)
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曹谢元
吴苑
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Priority to CN202111547477.8A priority Critical patent/CN114256108A/en
Publication of CN114256108A publication Critical patent/CN114256108A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67271—Sorting devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
    • B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
    • B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
    • B07C5/34—Sorting according to other particular properties
    • B07C5/344—Sorting according to other particular properties according to electric or electromagnetic properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A wafer screening method, comprising: providing a wafer to be packaged, wherein the wafer to be packaged comprises a plurality of chips; carrying out failure detection on a plurality of wafers, and acquiring a first failed wafer and an initial passing wafer from the plurality of wafers; acquiring first position information of the initial pass chip in a wafer to be packaged; carrying out risk detection on a plurality of wafers, and acquiring a first risk wafer from the plurality of wafers; acquiring second position information of the first risk chip in the wafer to be packaged; and marking the initial passing chip as a second failed chip when the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged. The method can improve the delivery yield and reduce the rejection rate.

Description

Wafer screening method
Technical Field
The invention relates to the field of semiconductor testing, in particular to a wafer screening method.
Background
Products on the wafer need to be delivered to customers after Chip combining (CP test for short) is completed, and the quality of the chips passing the Chip testing needs to be ensured.
Wafer testing aims at quickly screening out wafers with process anomalies, but does not effectively screen out wafers that may present a reliability risk. In particular, wafers screened out for process anomalies are wafer tested, and wafers that pass wafer testing in the vicinity may be at risk of reliability failures.
Therefore, the problem of how to screen out the chips with failed chip tests and possibly with failed reliability in the low-quality wafers with abnormal processes needs to be solved to improve the shipment confidence of the low-quality wafers and reduce the scrap number.
Disclosure of Invention
The invention provides a wafer screening method for improving the delivery confidence of low-quality wafers and reducing the number of scrapped wafers.
In order to solve the above technical problems, a technical solution of the present invention provides a wafer screening method, including: providing a wafer to be packaged, wherein the wafer to be packaged comprises a plurality of chips; carrying out failure detection on a plurality of wafers, and acquiring a first failed wafer and an initial passing wafer from the plurality of wafers; acquiring first position information of the initial pass chip in a wafer to be packaged; carrying out risk detection on a plurality of wafers, and acquiring a first risk wafer from the plurality of wafers; acquiring second position information of the first risk chip in the wafer to be packaged; and marking the initial passing chip as a second failed chip when the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged.
Optionally, the failure detection manner includes short circuit detection or open circuit detection.
Optionally, the method for obtaining a first failed wafer and an initial passing wafer from the plurality of wafers comprises: if the wafer is short-circuited or open-circuited, judging that the wafer is a first failure wafer; if the wafer is not short-circuited and not open-circuited, the wafer is judged to be an initial passing wafer.
Optionally, the risk detection manner includes a connectivity test, a timing correction test, a voltage correction test, an erase test, a write test, a read test, or a stress test.
Optionally, the voltage correction test method includes: providing a plurality of voltage gear values; and testing a plurality of wafers by adopting each voltage gear value until the wafers pass the test, and acquiring the corresponding voltage gear value when each wafer passes the test.
Optionally, the method for obtaining a first risk wafer among the plurality of wafers includes: obtaining a first risk wafer according to the corresponding voltage gear value when each wafer test passes: and if the corresponding voltage gear value is larger than a preset value when the wafer passes the test, judging that the wafer is a first risk wafer.
Optionally, the method for obtaining the first position information of the initially passing chip in the wafer to be packaged includes: according to the initial pass-through chip and the corresponding position of the initial pass-through chip on the wafer to be packaged, obtaining first distribution of the initial pass-through chip on the wafer, wherein the first distribution is first position information of the initial pass-through chip in the wafer to be packaged.
Optionally, the method for obtaining the second position information of the first risk chip in the wafer to be packaged includes: and acquiring second distribution of the first risk chips on the wafer according to the first risk chips and the corresponding positions of the first risk chips on the wafer to be packaged, wherein the second distribution is second position information of the first risk chips in the wafer to be packaged.
Optionally, the method further includes: and marking the initial passing wafer as a passing wafer when the second position information of the first risk wafer in the wafer to be packaged is different from the first position information of the initial passing wafer in the wafer to be packaged.
Optionally, after the obtaining the passing wafer and the second failed wafer, the method further includes: and recycling the first failed wafer and the second failed wafer.
Optionally, after the obtaining the passing wafer and the second failed wafer, the method further includes: and packaging the through wafer.
Optionally, the method further includes: when the second position information of the first risk chip in the wafer to be packaged is different from the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a transition passing chip; and acquiring third position information of the transition pass chip in the wafer to be packaged.
Optionally, according to a preset rule, a second risk chip is obtained from the plurality of chips, where the second risk chip is a chip associated with a position of the first failed chip in the wafer to be packaged; and acquiring fourth position information of the second risk chip in the wafer to be packaged.
Optionally, when the fourth position information of the second risk chip in the wafer to be packaged is the same as the third position information of the transition passing chip in the wafer to be packaged, marking the transition passing chip as a third failed chip.
Optionally, when the fourth position information of the second risk chip in the wafer to be packaged is different from the third position information of the transition passing chip in the wafer to be packaged, marking the transition passing chip as a passing chip.
Optionally, the preset rule includes: and taking the first failure wafer as a center and the wafers within the preset radius range as second risk wafers, or taking the first failure wafer as the center and taking the preset number of wafers around the first failure wafer as the second risk wafers.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the initial passing wafer is obtained through failure detection, and the first risk wafer is obtained through risk detection. Screening out a first risk wafer through risk detection, marking an initial pass wafer as a second failure wafer when second position information of the first risk wafer in the wafer to be packaged is the same as first position information of the initial pass wafer in the wafer to be packaged, and effectively screening out the failure wafer and the first risk wafer on the wafer through twice detection, so that the delivery yield can be improved, and the rejection rate is reduced.
Further, according to a preset rule, a second risk wafer is screened out from the plurality of wafers, and when fourth position information of the second risk wafer in the wafer to be packaged is the same as third position information of a transition passing wafer in the wafer to be packaged, the transition passing wafer is marked as a third failure wafer. The failure wafer, the first risk wafer and the second risk wafer on the wafer can be effectively screened out through three times of detection and screening, so that the delivery yield can be improved, and the rejection rate is reduced.
Drawings
FIG. 1 is a schematic flow chart of a wafer screening method according to an embodiment of the present invention;
FIGS. 2-7 are schematic views of a wafer screening process according to an embodiment of the present invention;
FIG. 8 is a flow chart illustrating a wafer screening method according to another embodiment of the present invention.
Detailed Description
FIG. 1 is a flow chart illustrating a wafer screening method according to an embodiment of the present invention.
Referring to fig. 1, the wafer screening method includes:
step S10: providing a wafer to be packaged, wherein the wafer to be packaged comprises a plurality of chips;
step S20: carrying out failure detection on a plurality of wafers, and acquiring a first failed wafer and an initial passing wafer from the plurality of wafers;
step S30: acquiring first position information of the initial pass chip in a wafer to be packaged;
step S40: carrying out risk detection on a plurality of wafers, and acquiring a first risk wafer from the plurality of wafers;
step S50: acquiring second position information of the first risk chip in the wafer to be packaged;
step S60: and marking the initial passing chip as a second failed chip when the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged.
An initial pass wafer is obtained by failure detection, and a first risk wafer is obtained by risk detection. Screening out a first risk wafer through risk detection, marking an initial pass wafer as a second failure wafer when second position information of the first risk wafer in the wafer to be packaged is the same as first position information of the initial pass wafer in the wafer to be packaged, and effectively screening out the failure wafer and the first risk wafer on the wafer through twice detection, so that the delivery yield can be improved, and the rejection rate is reduced.
Next, each step will be explained by analysis.
With continued reference to fig. 1, step S10 is executed: providing a wafer to be packaged, wherein the wafer to be packaged comprises a plurality of chips.
The wafer to be packaged is a bare chip with a functional device formed on the wafer after semiconductor processing is carried out on the wafer, and the bare chip becomes an independent chip after subsequent packaging and slicing.
Referring to fig. 2, fig. 2 is a schematic view of the wafer 100 to be packaged, where the wafer 100 to be packaged includes a plurality of chips 101.
With continued reference to fig. 1, step S20 is executed: failure detection is performed on a number of the wafers, and a first failed wafer and an initial pass wafer are acquired in the number of wafers 101.
The failure detection is to perform function detection on all the chips on the wafer 100 to be packaged, the chips passing the test can work normally, and the chips failing the test cannot work normally, and need to be selected and not shipped.
In this embodiment, the failure detection means includes short circuit detection or open circuit detection.
The method of acquiring a first failed wafer and an initial pass wafer among the plurality of wafers comprises: if the wafer is short-circuited or open-circuited, judging that the wafer is a first failure wafer; if the wafer is not short-circuited and not open-circuited, the wafer is judged to be an initial passing wafer.
Referring to fig. 3, fig. 3 is a schematic diagram of obtaining a first failed die 102 and an initial passed die 103 in the wafer 100 to be packaged. The location of each of the first failed die 102 and each of the initial pass-through die 103 on the wafer 100 is unique.
With continued reference to fig. 1, step S30 is executed: and acquiring first position information of the initial passing chip in the wafer to be packaged.
The method for acquiring the first position information of the initial passing chip in the wafer to be packaged comprises the following steps: according to the initial pass-through chip and the corresponding position of the initial pass-through chip on the wafer to be packaged, obtaining first distribution of the initial pass-through chip on the wafer, wherein the first distribution is first position information of the initial pass-through chip in the wafer to be packaged.
Referring to fig. 4, fig. 4 is a first distribution of the initial pass-through chips 103 at corresponding locations on the wafer 100 to be packaged.
With continued reference to fig. 1, step S40 is executed: and carrying out risk detection on a plurality of wafers, and acquiring a first risk wafer from the plurality of wafers.
The risk detection is a performance test of all chips in the wafer to be packaged, and the chips with failure risks are analyzed from the obtained performance test result.
The risk detection is performed by conventional testing of devices on the wafer, such as connectivity testing, timing correction testing, voltage correction testing, erase testing, write testing, read testing, or stress testing.
In this embodiment, the risk detection manner includes a voltage correction test. Due to the process fluctuation, the process of each wafer has slight difference, and an appropriate operating voltage is adapted to each wafer in a dynamic correction mode during testing, such as: if the initial voltage of a certain wafer is lower, the gear is pulled up to increase the voltage of the wafer; if the initial voltage of a certain chip is higher, the level is pulled down to reduce the voltage.
The voltage correction test method comprises the following steps: providing a plurality of voltage gear values; and testing a plurality of wafers by adopting each voltage gear value until the wafers pass the test, and acquiring the corresponding voltage gear value when each wafer passes the test. The voltage correction test passes the test of the wafer by adjusting the voltage gear value to be higher or adjusting the voltage gear value to be lower.
In this embodiment, the first risk wafer is a wafer around the first failed wafer. The voltage correction test is a durability failure test, and the first risk wafer durability failure is caused by that a certain oxide layer is thin, the voltage of the oxide layer is not added, namely the voltage measurement voltage is regulated abnormally, and the wafer passes the test by a method of regulating the gear value of the high voltage or regulating the gear value of the low voltage.
In this embodiment, the method for obtaining a first risk wafer among the plurality of wafers includes: obtaining a first risk wafer according to the corresponding voltage gear value when each wafer test passes: and if the corresponding voltage gear value is larger than a preset value when the wafer passes the test, judging that the wafer is a first risk wafer.
In other embodiments, the risk detection mode is other types, and then the risk judgment is performed by adopting other rules according to the actual situation.
The connectivity test comprises the following steps: the method mainly tests whether the pins after the wafer packaging have short circuit or not and whether the connectivity is intact or not.
The reading test comprises the following steps: judging whether the chip is '1' or '0' by reading the current, if the chip is '1', no electrons exist in the floating gate, and the chip is high in current; if "0" is detected, electrons exist in the floating gate, and a small current (Vwlr, Vblr, Vcgr, etc.) is detected.
The erasing test comprises the following steps: the Flash wafer is erased by an F-N tunneling mode, and electrons in the floating gate are extracted by a voltage applying mode (Vee _ Vcg, Vee _ Vwl, Vee _ Vbl and the like are involved). For example: if the erase is successful, electrons flow out of the floating gate under high voltage, and the read small current shows that the erase is successful, otherwise, the erase fails.
The writing test comprises the following steps: the Flash wafer performs write operation by the HCI method, and writes electrons into the floating gate (Vep _ Vcg, Vep _ Vwl, Vep _ Vbl, etc.) by applying a voltage. For example: if the writing is successful, electrons exist in the floating gate, and the current is small.
The pressure test comprises the following steps: in order to quickly screen for potentially failing chips. The stress test is performed by increasing the operating voltage, increasing the operating time, or increasing the number of operations, and then the function of the wafer is verified again through the erase, read, or write test.
Referring to fig. 5, fig. 5 is a schematic view based on fig. 2, and fig. 5 is a schematic view of the first risk die 104 in the wafer 100 to be packaged. The location of the first risky die 104 in the wafer 100 to be packaged is unique.
With continued reference to fig. 1, step S50 is executed: and acquiring second position information of the first risk chip in the wafer to be packaged.
The method for acquiring the second position information of the first risk chip in the wafer to be packaged comprises the following steps: and acquiring second distribution of the first risk chips on the wafer according to the first risk chips and the corresponding positions of the first risk chips on the wafer to be packaged, wherein the second distribution is second position information of the first risk chips in the wafer to be packaged.
Referring to fig. 6, fig. 6 shows a second distribution of the first risk dies 104 at corresponding positions on the wafer 100 to be packaged.
With continued reference to fig. 1, step S60 is executed: and marking the initial passing chip as a second failed chip when the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged.
Comparing second position information of a first risk chip in the wafer to be packaged with first position information of an initial pass chip in the wafer to be packaged, and marking the initial pass chip as a second failed chip if the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial pass chip in the wafer to be packaged; and if the second position information of the first risk chip in the wafer to be packaged is different from the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a passing chip.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating the distribution of the first failed die 102, the second failed die 105 and the pass-through die 106 in the wafer 100 to be packaged.
In this embodiment, after obtaining the passing wafer and the second failed wafer, the method further includes: and recycling the first failed wafer and the second failed wafer.
In this embodiment, after obtaining the passing wafer and the second failed wafer, the method further includes: and packaging the through wafer.
The failure chips and the first risk chips on the wafer can be effectively screened out through twice detection, so that the delivery yield can be improved, and the rejection rate is reduced.
FIG. 8 is a flow chart illustrating a wafer screening method according to another embodiment of the present invention.
Referring to fig. 8, fig. 8 is a schematic view based on fig. 1, the wafer screening method includes:
step S10: providing a wafer to be packaged, wherein the wafer to be packaged comprises a plurality of chips;
step S20: carrying out failure detection on a plurality of wafers, and acquiring a first failed wafer and an initial passing wafer from the plurality of wafers;
step S30: acquiring first position information of the initial pass chip in a wafer to be packaged;
step S40: carrying out risk detection on a plurality of wafers, and acquiring a first risk wafer from the plurality of wafers;
step S50: acquiring second position information of the first risk chip in the wafer to be packaged;
step S60: when the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a second failed chip;
step S70: when the second position information of the first risk chip in the wafer to be packaged is different from the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a transition passing chip;
step S80: acquiring third position information of the transition pass chip in the wafer to be packaged;
step S90: according to a preset rule, a second risk wafer is obtained from the plurality of wafers, wherein the second risk wafer is a wafer related to the position of the first failure wafer in the wafer to be packaged;
step S100: acquiring fourth position information of a second risk chip in the wafer to be packaged;
step S110: and marking the transitional passing chip as a third failed chip when the fourth position information of the second risk chip in the wafer to be packaged is the same as the third position information of the transitional passing chip in the wafer to be packaged.
The method comprises the steps of obtaining initial pass wafers through failure detection, obtaining first risk wafers through risk detection, and screening out second risk wafers from a plurality of wafers according to preset rules. When the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a second failed chip, and when the fourth position information of the second risk chip in the wafer to be packaged is the same as the third position information of the transitional passing chip in the wafer to be packaged, marking the transitional passing chip as a third failed chip. The failure wafer, the first risk wafer and the second risk wafer on the wafer can be effectively screened out through three times of detection and screening, so that the delivery yield can be improved, and the rejection rate is reduced.
Please refer to fig. 1 for detailed description of steps S10 to S60, which are not repeated herein.
Next, steps of steps S70 to S110 will be specifically described.
With continued reference to fig. 8, step S70 is executed: when the second position information of the first risk chip in the wafer to be packaged is different from the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a transition passing chip.
With continued reference to fig. 8, step S80 is executed: and acquiring third position information of the transition pass chip in the wafer to be packaged.
The method for acquiring the third position information of the transition passing chip in the wafer to be packaged comprises the following steps: and acquiring a third distribution of the transition passing chip on the wafer according to the transition passing chip and the corresponding position of the transition passing chip on the wafer to be packaged, wherein the third distribution is third position information of the transition passing chip in the wafer to be packaged.
With continued reference to fig. 8, step S90 is executed: and acquiring a second risk wafer from the plurality of wafers according to a preset rule, wherein the second risk wafer is a wafer related to the position of the first failure wafer in the wafer to be packaged.
In this embodiment, the preset rule includes: and taking the first failure wafer as a center and the wafers within the preset radius range as second risk wafers, or taking the first failure wafer as the center and taking the preset number of wafers around the first failure wafer as the second risk wafers.
In other embodiments, the preset rule is specifically determined according to actual conditions.
With continued reference to fig. 8, step S100 is executed: and acquiring fourth position information of the second risk chip in the wafer to be packaged.
The method for acquiring the fourth position information of the second risk chip in the wafer to be packaged comprises the following steps: and acquiring fourth distribution of the second risk chips on the wafer according to the second risk chips and the corresponding positions of the second risk chips on the wafer to be packaged, wherein the fourth distribution is fourth position information of the second risk chips in the wafer to be packaged.
With continued reference to fig. 8, step S110 is executed: and marking the transitional passing chip as a third failed chip when the fourth position information of the second risk chip in the wafer to be packaged is the same as the third position information of the transitional passing chip in the wafer to be packaged.
Comparing fourth position information of a second risk chip in the wafer to be packaged with third position information of a transition passing chip in the wafer to be packaged, and marking the transition passing chip as a third failure chip if the fourth position information of the second risk chip in the wafer to be packaged is the same as the third position information of the transition passing chip in the wafer to be packaged; and if the fourth position information of the second risk chip in the wafer to be packaged is different from the third position information of the transition passing chip in the wafer to be packaged, marking the transition passing chip as a passing chip.
The failure chips and the first risk chips on the wafer can be effectively screened out through three times of detection, so that the delivery yield can be improved, and the rejection rate is reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of screening a wafer, comprising:
providing a wafer to be packaged, wherein the wafer to be packaged comprises a plurality of chips;
carrying out failure detection on a plurality of wafers, and acquiring a first failed wafer and an initial passing wafer from the plurality of wafers;
acquiring first position information of the initial pass chip in a wafer to be packaged;
carrying out risk detection on a plurality of wafers, and acquiring a first risk wafer from the plurality of wafers;
acquiring second position information of the first risk chip in the wafer to be packaged;
and marking the initial passing chip as a second failed chip when the second position information of the first risk chip in the wafer to be packaged is the same as the first position information of the initial passing chip in the wafer to be packaged.
2. The wafer screening method of claim 1, wherein the failure detection means comprises a short circuit detection or an open circuit detection.
3. The wafer screening method of claim 2, wherein the method of acquiring a first failed wafer and an initial pass wafer among the plurality of wafers comprises: if the wafer is short-circuited or open-circuited, judging that the wafer is a first failure wafer; if the wafer is not short-circuited and not open-circuited, the wafer is judged to be an initial passing wafer.
4. The wafer screening method of claim 1, wherein the risk detection means comprises a connectivity test, a timing correction test, a voltage correction test, an erase test, a write test, a read test, or a stress test.
5. The wafer screening method of claim 4, wherein the voltage modification test method comprises: providing a plurality of voltage gear values; and testing a plurality of wafers by adopting each voltage gear value until the wafers pass the test, and acquiring the corresponding voltage gear value when each wafer passes the test.
6. The wafer screening method of claim 5, wherein the method of obtaining a first risk wafer among the plurality of wafers comprises: obtaining a first risk wafer according to the corresponding voltage gear value when each wafer test passes: and if the corresponding voltage gear value is larger than a preset value when the wafer passes the test, judging that the wafer is a first risk wafer.
7. The wafer screening method of claim 1, wherein the method of obtaining the first location information of the initially passed wafer in the wafer to be packaged comprises: according to the initial pass-through chip and the corresponding position of the initial pass-through chip on the wafer to be packaged, obtaining first distribution of the initial pass-through chip on the wafer, wherein the first distribution is first position information of the initial pass-through chip in the wafer to be packaged.
8. The wafer screening method of claim 1, wherein the step of obtaining the second position information of the first risk wafer in the wafer to be packaged comprises: and acquiring second distribution of the first risk chips on the wafer according to the first risk chips and the corresponding positions of the first risk chips on the wafer to be packaged, wherein the second distribution is second position information of the first risk chips in the wafer to be packaged.
9. The wafer screening method of claim 1, further comprising: and marking the initial passing wafer as a passing wafer when the second position information of the first risk wafer in the wafer to be packaged is different from the first position information of the initial passing wafer in the wafer to be packaged.
10. The wafer screening method of claim 9, further comprising, after acquiring the pass wafer and the second fail wafer: and recycling the first failed wafer and the second failed wafer.
11. The wafer screening method of claim 9, further comprising, after acquiring the pass wafer and the second fail wafer: and packaging the through wafer.
12. The wafer screening method of claim 1, further comprising: when the second position information of the first risk chip in the wafer to be packaged is different from the first position information of the initial passing chip in the wafer to be packaged, marking the initial passing chip as a transition passing chip; and acquiring third position information of the transition pass chip in the wafer to be packaged.
13. The wafer screening method of claim 12, wherein a second risk wafer is obtained among the plurality of wafers according to a predetermined rule, the second risk wafer being a wafer associated with a position of a first failed wafer in the wafer to be packaged; and acquiring fourth position information of the second risk chip in the wafer to be packaged.
14. The wafer screening method of claim 13, wherein when the fourth position information of the second risk wafer in the wafer to be packaged is the same as the third position information of the transit passing wafer in the wafer to be packaged, the transit passing wafer is marked as a third failed wafer.
15. The wafer screening method of claim 14, wherein when fourth position information of the second risk die in the wafer to be packaged is different from third position information of a transit passing die in the wafer to be packaged, the transit passing die is marked as a passing die.
16. The wafer screening method of claim 13, wherein the predetermined rule comprises: and taking the first failure wafer as a center and the wafers within the preset radius range as second risk wafers, or taking the first failure wafer as the center and taking the preset number of wafers around the first failure wafer as the second risk wafers.
CN202111547477.8A 2021-12-16 2021-12-16 Wafer screening method Pending CN114256108A (en)

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CN202111547477.8A CN114256108A (en) 2021-12-16 2021-12-16 Wafer screening method

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