CN114253483A - Write cache management method and device based on command, computer equipment and storage medium - Google Patents
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- 230000001960 triggered effect Effects 0.000 claims abstract description 6
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- 238000004590 computer program Methods 0.000 claims description 13
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a write cache management method, a write cache management device, computer equipment and a storage medium based on commands, wherein the method comprises the following steps: acquiring a write cache management request based on a command; according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the linked list; when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value, the command of the cache is triggered to be written into the NAND; if the cached commands form a sequential stream, rearranging the logic address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND. The command level write cache management mode provided by the invention can effectively reduce the requirement on RAM resources and meet the requirement of DRAM-less SSD.
Description
Technical Field
The present invention relates to the field of storage system technologies, and in particular, to a write cache management method and apparatus based on a command, a computer device, and a storage medium.
Background
With the development of Solid State Disk technology, SSD (Solid State Disk) has been widely used in various occasions, and has gradually replaced traditional HDD (Hard Disk Drive) in PC market, providing better experience for users from the aspects of reliability and performance.
At present, one of the functions of the SSD write cache is to collect sufficient sequential write data, and to reorder and write the data into the NAND according to the optimal read concurrency requirement, so as to ensure the optimal read performance. However, the conventional write cache is usually managed according to the size of a mapping unit (usually 4KB), and in order to cache enough data, a large number of write cache management units are needed, and the requirement on RAM space is large.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, an apparatus, a computer device and a storage medium for command-based write cache management.
A command-based write cache management method, the method comprising:
acquiring a write cache management request based on a command;
according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the linked list;
when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value, the command of the cache is triggered to be written into the NAND;
if the cached commands form a sequential stream, rearranging the logic address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing;
otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
In one embodiment, the method further comprises:
in the command-based write cache management, a management unit of a write cache is a command with an indefinite length, and the command with the indefinite length is used for managing an effective mapping unit bitmap;
when the write command is overwritten, the corresponding mapping unit bitmap in the overwritten command is cleared.
In one embodiment, the method further comprises:
and finishing the check of the read-write command hit by the ASIC logic in the solid state hard disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
In one embodiment, the step of performing read-write hit processing according to the read-write hit result of the ASIC includes:
and if the hit is detected, traversing the command linked list of the command cache, and clearing the corresponding bit of the effective logical address bitmap in the hit command.
An apparatus for command-based write cache management, the apparatus comprising:
the acquisition module is used for acquiring a write cache management request based on a command;
the composition module is used for composing the write cache command into a write cache command linked list according to the command-based write cache management request in a linked list form;
the trigger module is used for triggering the cached command to be written into the NAND when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value;
the arranging module is used for rearranging the logic address interval corresponding to the sequential flow according to the optimal reading concurrency requirement before writing if the cached commands form the sequential flow;
and the extraction and writing module is used for traversing the command linked list if the command linked list is not the same, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
In one embodiment, the apparatus further comprises an element management module configured to:
in the command-based write cache management, a management unit of a write cache is a command with an indefinite length, and the command with the indefinite length is used for managing an effective mapping unit bitmap;
when the write command is overwritten, the corresponding mapping unit bitmap in the overwritten command is cleared.
In one embodiment, the apparatus further comprises a hit check module configured to:
and finishing the check of the read-write command hit by the ASIC logic in the solid state hard disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
In one embodiment, the hit check module is further configured to:
and if the hit is detected, traversing the command linked list of the command cache, and clearing the corresponding bit of the effective logical address bitmap in the hit command.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.
The command-based write cache management method, the command-based write cache management device, the computer equipment and the storage medium acquire a command-based write cache management request; according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the linked list; when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value, the command of the cache is triggered to be written into the NAND; if the cached commands form a sequential stream, rearranging the logic address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND. The command level write cache management mode provided by the invention can effectively reduce the requirement on RAM resources and meet the requirement of DRAM-less SSD.
Drawings
FIG. 1 is a diagram of write cache management based on a mapping unit;
FIG. 2 is a schematic illustration of command-based write cache management;
FIG. 3 is a flow diagram that illustrates a method for command-based write cache management, according to an embodiment;
FIG. 4 is a flow diagram illustrating a command-based write cache management method in accordance with another embodiment;
FIG. 5 is a flow diagram illustrating a command-based write cache management method in accordance with yet another embodiment;
FIG. 6 is a block diagram of an apparatus for command-based write cache management in one embodiment;
FIG. 7 is a block diagram of an apparatus for command-based write cache management in another embodiment;
FIG. 8 is a block diagram showing a structure of a command-based write cache management apparatus according to still another embodiment;
FIG. 9 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
At present, one of the functions of the SSD write cache is to collect sufficient sequential write data, and to reorder and write the data into the NAND according to the optimal read concurrency requirement, so as to ensure the optimal read performance. However, the conventional write cache is usually managed according to the size of a mapping unit (usually 4KB), and in order to cache enough data, a large number of write cache management units are needed, and the requirement on RAM space is large.
Based on the above, the invention provides a write cache management method based on commands, which aims to reduce the demand on RAM resources so as to meet the requirement of DRAM-less SSD.
In one embodiment, as shown in fig. 3, there is provided a command-based write cache management method, the method comprising:
step 302, obtaining a write cache management request based on a command;
step 304, according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the form of the linked list;
step 306, when the total number of valid logic units or the total number of cache commands in the write cache exceeds a threshold, triggering the cached commands to write into the NAND;
step 308, if the cached commands form a sequential stream, rearranging the logical address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing;
and step 310, otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND.
In this embodiment, a command-level write cache management method is provided to reduce the RAM resource requirement to meet the DRAM-less SSD requirement, and the specific implementation steps are as follows:
the mapping unit based cache management is described with reference to fig. 1, and fig. 2 is the command based write cache management proposed in the present embodiment. Firstly, a write cache management request based on a command is obtained; and according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the form of the linked list. In particular, the write commands are organized in a linked list, requiring less additional management information.
Then, when the total number of valid logical units in the write cache exceeds a threshold or the total number of cached commands exceeds a threshold, the cached commands are triggered to be written into the NAND. If the cached commands form a sequential stream, rearranging the logic address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command, and writing the effective data information into the NAND.
In the embodiment, the cache management request is managed by acquiring a write cache based on a command; according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the linked list; when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value, the command of the cache is triggered to be written into the NAND; if the cached commands form a sequential stream, rearranging the logic address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing; otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND. The command level write cache management mode provided by the scheme can effectively reduce the requirement on RAM resources and meet the requirement of DRAM-less SSD.
In one embodiment, as shown in fig. 4, there is provided a command-based write cache management method, further comprising:
step 402, in the command-based write cache management, the management unit of the write cache is a command with an indefinite length, and the command with the indefinite length is used for managing an effective mapping unit bitmap;
in step 404, when the write command is overwritten, the corresponding mapping unit bitmap in the overwritten command is cleared.
In one embodiment, as shown in fig. 5, there is provided a command-based write cache management method, further comprising:
step 502, the ASIC logic in the solid state hard disk controller completes the check of the read-write command hit, and the read-write hit processing is performed according to the read-write hit result of the ASIC;
step 504, if the hit is detected, the command linked list of the command cache is traversed, and the corresponding bit of the effective logical address bitmap in the hit command is cleared.
In this embodiment, a command-based write cache management method is provided, in which read/write hit checking is performed by a custom ASIC logic in an SSD controller instead, so as to speed up read/write command processing.
In particular, the management structure commonly used for read-write hit checking described with reference to fig. 1: if the software maintains the query structure and performs the hit check, it will increase the processing delay of the read/write command. In this embodiment, as shown in fig. 2, in the write cache management scheme based on commands, the process of hit checking is processed by the customized ASIC logic of the SSD controller, and the software only needs to perform corresponding processing according to the checking result provided by the controller. And if the hit is detected, traversing the command linked list of the command cache, and clearing the bit corresponding to the effective logical address bitmap in the hit command.
In the embodiment, the check in the read-write command of the command level is completed through the ASIC logic customized in the SSD controller, and the software performs read-write hit processing according to the read-write hit result of the ASIC, so that the processing of the read-write command is accelerated.
It should be understood that although the various steps in the flow charts of fig. 1-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in FIG. 6, there is provided a command-based write cache management apparatus 600, comprising:
an obtaining module 601, configured to obtain a write cache management request based on a command;
a composition module 602, configured to compose a write cache command linked list from write cache commands according to a linked list form according to the command-based write cache management request;
a trigger module 603, configured to trigger the cached command to be written into the NAND when the total number of valid logic units or the total number of cache commands in the write cache exceeds a threshold;
an arranging module 604, configured to rearrange, before writing, a logical address interval corresponding to a sequential stream according to an optimal read concurrency requirement if the cached commands form the sequential stream;
and an extract write module 605, configured to traverse the command linked list if the command linked list is not the valid logical unit bitmap in the command, extract valid data information according to the valid logical unit bitmap in the command, and write the valid data information into the NAND.
In one embodiment, as shown in fig. 7, there is provided a command-based write cache management apparatus 600, further comprising a unit management module 606 for:
in the command-based write cache management, a management unit of a write cache is a command with an indefinite length, and the command with the indefinite length is used for managing an effective mapping unit bitmap;
when the write command is overwritten, the corresponding mapping unit bitmap in the overwritten command is cleared.
In one embodiment, as shown in fig. 8, there is provided a command-based write cache management apparatus 600, further comprising a hit check module 607 for:
and finishing the check of the read-write command hit by the ASIC logic in the solid state hard disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
In one embodiment, the hit check module 607 is further configured to:
and if the hit is detected, traversing the command linked list of the command cache, and clearing the corresponding bit of the effective logical address bitmap in the hit command.
For specific limitations of the command-based write cache management apparatus, reference may be made to the above limitations of the command-based write cache management method, which is not described herein again.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 9. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a command-based write cache management method.
Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A command-based write cache management method, the method comprising:
acquiring a write cache management request based on a command;
according to the write cache management request based on the command, forming a write cache command linked list by the write cache command according to the linked list;
when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value, the command of the cache is triggered to be written into the NAND;
if the cached commands form a sequential stream, rearranging the logic address intervals corresponding to the sequential stream according to the optimal read concurrency requirement before writing;
otherwise, traversing the command linked list, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
2. The command-based write cache management method of claim 1, further comprising:
in the command-based write cache management, a management unit of a write cache is a command with an indefinite length, and the command with the indefinite length is used for managing an effective mapping unit bitmap;
when the write command is overwritten, the corresponding mapping unit bitmap in the overwritten command is cleared.
3. The command-based write cache management method of claim 1, further comprising:
and finishing the check of the read-write command hit by the ASIC logic in the solid state hard disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
4. The command-based write cache management method according to claim 3, wherein the step of performing read-write hit processing according to the read-write hit result of the ASIC comprises:
and if the hit is detected, traversing the command linked list of the command cache, and clearing the corresponding bit of the effective logical address bitmap in the hit command.
5. An apparatus for command-based write cache management, the apparatus comprising:
the acquisition module is used for acquiring a write cache management request based on a command;
the composition module is used for composing the write cache command into a write cache command linked list according to the command-based write cache management request in a linked list form;
the trigger module is used for triggering the cached command to be written into the NAND when the total number of the effective logic units or the total number of the cache commands in the write cache exceeds a threshold value;
the arranging module is used for rearranging the logic address interval corresponding to the sequential flow according to the optimal reading concurrency requirement before writing if the cached commands form the sequential flow;
and the extraction and writing module is used for traversing the command linked list if the command linked list is not the same, extracting effective data information according to the effective logic unit bitmap in the command and writing the effective data information into the NAND.
6. The command-based write cache management apparatus of claim 5, wherein the apparatus further comprises an element management module to:
in the command-based write cache management, a management unit of a write cache is a command with an indefinite length, and the command with the indefinite length is used for managing an effective mapping unit bitmap;
when the write command is overwritten, the corresponding mapping unit bitmap in the overwritten command is cleared.
7. The command-based write cache management apparatus of claim 5, further comprising a hit check module to:
and finishing the check of the read-write command hit by the ASIC logic in the solid state hard disk controller, and performing read-write hit processing according to the read-write hit result of the ASIC.
8. The command-based write cache management apparatus of claim 7, wherein the hit check module is further configured to:
and if the hit is detected, traversing the command linked list of the command cache, and clearing the corresponding bit of the effective logical address bitmap in the hit command.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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| CN116701246A (en) * | 2023-05-23 | 2023-09-05 | 合芯科技有限公司 | Method, device, equipment and storage medium for improving cache bandwidth |
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| CN105302501A (en) * | 2015-11-27 | 2016-02-03 | 浙江宇视科技有限公司 | Control method and device for disk sectors |
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| CN115905038A (en) * | 2022-12-01 | 2023-04-04 | 格兰菲智能科技有限公司 | Cache data reading method and device, computer equipment and storage medium |
| CN115905038B (en) * | 2022-12-01 | 2023-12-22 | 格兰菲智能科技有限公司 | Cache data reading method, device, computer equipment and storage medium |
| CN116701246A (en) * | 2023-05-23 | 2023-09-05 | 合芯科技有限公司 | Method, device, equipment and storage medium for improving cache bandwidth |
| CN116701246B (en) * | 2023-05-23 | 2024-05-07 | 合芯科技有限公司 | Method, device, equipment and storage medium for improving cache bandwidth |
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Effective date of registration: 20231201 Address after: Room 4-B703, No. 328 Xinghu Street, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Pilot Free Trade Zone, Suzhou City, Jiangsu Province, 215000 Patentee after: Suzhou Yilian Information System Co.,Ltd. Address before: D24 / f-02, dongjiaotou workshop, Shekou Houhai Avenue, Shekou street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN UNIONMEMORY INFORMATION SYSTEM Co.,Ltd. |