CN111831589A

CN111831589A - Method and device for improving IO command processing parallelism

Info

Publication number: CN111831589A
Application number: CN202010887341.0A
Authority: CN
Inventors: 路向峰
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2020-10-27
Anticipated expiration: 2036-07-01
Also published as: CN111831589B; CN107562654B; CN107562654A

Abstract

A method and apparatus for improving IO command processing parallelism are provided. The disclosed method for processing IO request includes: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the physical block or the large block containing the first physical address is in an erased state, replaying the first read request; and if the current writing position lags behind the first physical address, suspending the processing of the first read request until the current writing position leads the first physical address.

Description

Method and device for improving IO command processing parallelism

Technical Field

The present invention relates to a solid-state storage device, and more particularly, to a method, an apparatus, and a device for improving I O command processing parallelism when an IO request is processed by a solid-state storage device.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host and the storage device 102 by, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105 and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, P CIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in a variety of ways including software, hardware, firmware, or a combination thereof. The control unit 104 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller. Control unit 104 loads firmware from firmware memory 110 at runtime. Firmware memory 110 may be NOR flash, ROM, EEPROM, or may be part of NVM chip 105.

In the solid-state storage device, mapping information from logical addresses to physical addresses is maintained using FTL (Flash Translation Layer). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

The FTL table includes a plurality of FTL table entries (or table entries). In one embodiment, each FTL table entry records a correspondence relationship between a logical page address and a physical page. In another example, each FTL table entry records the correspondence between consecutive logical page addresses and consecutive physical pages. In another embodiment, each FTL table entry records the corresponding relationship between the logical block address and the physical block address. In still another embodiment, the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses.

Fig. 2 is a schematic diagram of a prior art control component accessing an FTL table. The control section 204 includes a plurality of CPUs (CPU210, CPU 212, and CPU 214) and a flash interface through which the CPU of the control section accesses the NVM chip in the solid-state storage device. The FTL table is stored in a memory external to control component 204 and includes a plurality of entries (entry 220, entry 222, and entry 224). Each of the plurality of CPUs can independently access the FTL table. To achieve data consistency, a lock is provided for each F TL entry, since FTL entries may be accessed by multiple CPUs simultaneously. Referring to fig. 2, to update the FTL entry 224, the CPU210 checks the lock 234 of the FTL entry 224, and in case the lock 234 indicates that the FTL entry 224 is not locked, the CPU210 obtains the lock 234 (e.g., sets the lock 234 to the locked state) and acquires the FTL entry 224 (time t 1). Next, the CPU210 operates on the retrieved FTL entry 224 and updates the FTL entry 224 at time t4 and releases the lock 234 (e.g., sets the lock 234 to an unlocked state). During times t1-t4, the other CPUs (CPU 212 and CPU 214) retrieve the presence of lock 234 and temporarily relinquish access to the FTL entry 224. In FIG. 2, at time t2, CPU 212 attempts to access FTL entry 224, but finds that lock 234 cannot be obtained, and then relinquishes access to FT L entry 224. Similarly, the CPU214 may also relinquish access to the FTL entry 224 at time t3 because the lock 234 is not available. After time t4, however, CPU210 releases lock 234 and the CPU 212 and the CPU214 that preempted lock 234 will access FTL entry 234. In another example, during the time period t1-t4, one task of the CPU210 acquires the lock 234, while another task in the CPU210 temporarily relinquishes access to the FTL entry 224 because the lock 234 was not acquired.

The lock of the FTL entry may be stored in the same location of the corresponding FTL entry, or the locks of a plurality of FTL entries may be collectively stored in another storage space.

Disclosure of Invention

In the solid-state storage device, a plurality of IO requests are processed simultaneously, and almost every IO request needs to access the FTL table. And the locking mechanism enables the access to the FTL table entry to be serialized, reduces the parallel processing capacity of solid-state storage, and increases the processing delay of the IO request.

In the present invention, there is provided a first method for processing an IO request according to the first aspect of the present invention, including: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the current write location is behind the first physical address, processing of the first read request is suspended until the current write location is ahead of the first physical address.

According to the first method for processing an IO request of the first aspect of the present invention, there is provided a second method for processing an IO request of the first aspect of the present invention, further comprising: data is read from a first physical address in response to the first read request.

A third method for processing an IO request according to the first aspect of the present invention includes: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; if the physical block or chunk containing the first physical address is in a written state, and if the current write position leads the first physical address, reading data from the first physical address in response to the first read request.

According to a third method for processing an IO request in the first aspect of the present invention, there is provided a fourth method for processing an IO request in the first aspect of the present invention, further comprising: if the physical block or chunk containing the first physical address is in an erased state, the first read request is replayed.

According to the third or fourth method for processing an IO request of the first aspect of the present invention, there is provided a fifth method for processing an IO request of the first aspect of the present invention, further comprising: if the current write location is behind the first physical address, processing of the first read request is suspended until the current write location is ahead of the first physical address.

According to a fourth method for processing an IO request of the first aspect of the present invention, there is provided the sixth method for processing an IO request of the first aspect of the present invention, wherein the replaying the first read request includes: accessing a first FTL table entry corresponding to the first read request, and acquiring a second physical address recorded by the first FTL table entry; if the physical block or chunk containing the second physical address is in a written state, and if the current write position is ahead of the second physical address, reading data from the second physical address in response to the first read request.

According to one of the third to sixth methods of handling IO requests of the first aspect of the present invention, there is provided the seventh method of handling IO requests of the first aspect of the present invention, wherein the current write location is a current write location of a physical block or a large block containing the first physical address.

A first method of handling IO requests according to a second aspect of the invention comprises: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; reading data from a first physical address; if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is in an erased state, if the current writing position is behind the first physical address, the processing of the first read request is suspended until the current writing position is ahead of the first physical address.

According to the first method for processing an IO request of the second aspect of the present invention, there is provided a second method for processing an IO request of the second aspect of the present invention, further comprising: after the current write position leads the first physical address, reading data from the first physical address in response to the first read request.

A third method for processing an IO request according to the second aspect of the present invention includes: responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry; reading data from a first physical address; if the result of reading data from the first physical address indicates that the physical page in which the first physical address is located is in an erased state and the physical block or chunk containing the first physical address is in a written state, processing of the first read request is suspended until the current write location leads the first physical address.

According to a third method for processing an IO request of the second aspect of the present invention, there is provided a fourth method for processing an IO request of the second aspect of the present invention, further comprising: after the current write position leads the first physical address, reading data from the first physical address in response to the first read request.

According to a third method for processing an IO request of the second aspect of the present invention, there is provided a fifth method for processing an IO request of the second aspect of the present invention, further comprising: if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is in an erased state and the physical block or large block containing the first physical address is in an erased state, acquiring a second physical address recorded by a first FTL table entry corresponding to the first read request; and reading data from the second physical address.

According to a fifth method for processing an IO request of the second aspect of the present invention, there is provided the sixth method for processing an IO request of the second aspect of the present invention, further comprising: after the second physical address recorded by the first FTL table entry is obtained, if the current writing position lags behind the second physical address, the processing of the first reading request is suspended until the current writing position is ahead of the second physical address.

According to a sixth method for processing an IO request of the second aspect of the present invention, there is provided the seventh method for processing an IO request of the second aspect of the present invention, further comprising: after the current writing position is ahead of the second physical address, reading data from the second physical address to respond to the first read request.

A first method for processing an IO request according to a third aspect of the present invention includes: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; allocating a first physical address to the write request, updating a first FTL table entry by using the first physical address, unlocking the first FTL table entry, writing data into the first physical address, and updating the current write position; responding to the received read request, accessing a first FTL table entry corresponding to the read request, and acquiring a first physical address recorded by the first FTL table entry; if the current write location is behind the first physical address, processing of the first read request is suspended until the current write location is ahead of the first physical address.

According to the first method for processing an IO request in the third aspect of the present invention, there is provided a second method for processing an IO request in the third aspect of the present invention, further comprising: in response to receiving a second write request, if the first FTL entry is locked, processing of the second write request is aborted until the lock of the first FTL entry is released.

According to the second method for processing an IO request in the third aspect of the present invention, there is provided a third method for processing an IO request in the third aspect of the present invention, further comprising: and after the lock of the first FTL table entry is released, acquiring the first FTL table entry and locking the first FTL table entry.

According to the first to third methods for processing an IO request in the third aspect of the present invention, there is provided a fourth method for processing an IO request in the third aspect of the present invention, further comprising: responding to the received read request, accessing a first FTL table entry corresponding to the read request, and acquiring a first physical address recorded by the first FTL table entry; and if the physical block containing the first physical address is in an erasing state, replaying the read request.

According to the first to fourth methods for processing an IO request in the third aspect of the present invention, there is provided a fifth method for processing an IO request in the third aspect of the present invention, further comprising: after the current write position leads the first physical address, reading data from the first physical address in response to the read request.

According to one of the methods of processing an IO request of the third aspect of the present invention, there is provided the method of processing an IO request of the sixth aspect of the present invention, wherein the allocating the first physical address to the write request includes using the current write location as the first physical address, and incrementing the current write location.

A first IO request processing apparatus according to a fourth aspect of the present invention includes: the FTL entry accessing module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; and the current writing position processing module is used for suspending the processing of the first read request until the current writing position leads the first physical address if the current writing position lags the first physical address.

A second IO request processing apparatus according to a fourth aspect of the present invention includes: the FTL entry accessing module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; and the current write position processing module is used for reading data from the first physical address to respond to the first read request if the physical block or the large block containing the first physical address is in a written state and if the current write position is ahead of the first physical address.

A first IO request processing apparatus according to a fifth aspect of the present invention includes: the FTL entry accessing module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; the current writing position processing module is used for reading data from the first physical address; if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is in an erased state, if the current writing position is behind the first physical address, the processing of the first read request is suspended until the current writing position is ahead of the first physical address.

An apparatus for processing an IO request according to a fifth aspect of the present invention includes: the FTL entry accessing module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; the current writing position processing module is used for reading data from the first physical address; if the result of reading data from the first physical address indicates that the physical page in which the first physical address is located is in an erased state and the physical block or chunk containing the first physical address is in a written state, processing of the first read request is suspended until the current write location leads the first physical address.

A first IO request processing apparatus according to a sixth aspect of the present invention includes: the write request processing module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; an FTL entry updating module, configured to allocate a first physical address to the write request, update a first FTL entry with the first physical address, unlock the first FTL entry, write data to the first physical address, and update a current write position; the read request processing module is used for responding to the received read request, accessing a first FTL table entry corresponding to the read request and acquiring a first physical address recorded by the first FTL table entry; and the current writing position processing module is used for suspending the processing of the first read request until the current writing position leads the first physical address if the current writing position lags the first physical address.

According to a seventh aspect of the present invention there is provided a computer program comprising computer program code which, when loaded into a computer system and executed thereon, causes the computer system to perform a method of handling IO requests as provided in accordance with the first to third aspects of the present invention.

According to an eighth aspect of the present invention, there is provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to perform a method of handling IO requests as provided in accordance with the first to third aspects of the present invention.

Drawings

The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a prior art storage device;

FIG. 2 is a schematic diagram of a control component of a prior art storage device accessing an FTL table;

fig. 3A is a schematic diagram of a control component of a storage device accessing an FTL table according to an embodiment of the present invention;

fig. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present invention;

fig. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present invention; and

FIG. 4A is a flow diagram of accessing an FTL table for handling write commands according to an embodiment of the present invention;

FIG. 4B is a flow diagram of accessing an FTL table for handling write commands according to an embodiment of the present invention;

fig. 5A is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present invention;

FIG. 5B is a sequence diagram for processing the IO request of FIG. 5A in accordance with the present invention;

FIG. 6 is a schematic diagram of the organization of physical blocks of an NVM into a block stripe in accordance with an embodiment of the present invention;

fig. 7 is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present invention;

FIG. 8A is a flow diagram of accessing an FTL table for handling write commands according to yet another embodiment of the present invention;

FIG. 8B is a flow diagram of accessing an FTL table for handling read commands according to yet another embodiment of the present invention;

FIG. 9A is a flow diagram of accessing an FTL table for processing IO commands in accordance with an embodiment of the present invention;

FIG. 9B is a flowchart of accessing an FTL table for processing IO commands in accordance with a further embodiment of the present invention;

FIG. 9C is a flow diagram of accessing an FTL table for processing IO commands in accordance with yet another embodiment of the present invention;

fig. 10A is a schematic diagram of a control component of a storage device accessing an FTL table according to yet another embodiment of the present invention;

FIG. 10B is a sequence diagram for processing the IO request of FIG. 10A in accordance with the present invention;

FIG. 11A is a flow diagram of processing a write command according to an embodiment of the invention;

FIG. 11B is a flow diagram of processing a read command according to an embodiment of the invention;

FIG. 11C is a flow diagram of processing an IO command in accordance with yet another embodiment of the present invention;

FIG. 12A is a flow diagram of processing an IO command according to another embodiment of the invention; and

FIG. 12B is a flow diagram of processing an IO command according to another embodiment of the invention.

Detailed Description

In the NVMe (Non-Volatile Memory express) protocol, different IO command types are defined. For some IO commands, no requirements are made on the sequentiality between the IO commands. For example, if a read command for logical address x is submitted and a write command for logical address x is also submitted, although the execution result of the write command may affect the execution result of the read command, if the sequentiality between the two IO commands is not required, the NVMe protocol allows the solid-state storage device to execute the two IO commands in any order.

Aiming at the characteristic of the NVMe protocol, in the embodiment of the invention, the processing mode of the IO request is improved, so that the IO command processing capacity of the solid-state storage device is improved, and the processing delay of the IO command is reduced. Those skilled in the art will appreciate that while embodiments in accordance with the present invention are described in the context of the NVMe protocol, embodiments in accordance with the present invention may be implemented in other protocols that do not require an execution order between IO commands.

Referring to fig. 3A, a schematic diagram illustrating a control component of a storage device accessing an FTL table according to an embodiment of the present invention is shown. The control unit 304 of the solid state disk includes a plurality of CPUs (CPU 310, CPU 312, and CPU 314), each of which is capable of accessing the FTL table external to the control unit 304. The FTL table is stored in, for example, a DRAM (dynamic Random Access Memory). The CPU of the control unit also accesses the NVM chip through a flash interface (not shown). By way of example, the CPU310 processes a write command from the host, accesses the FTL entry 324 (indicated by W-t1 of FIG. 3A) at time t1 in accordance with the logical address indicated by the write command to assign a physical address to the write command. To avoid multiple write commands writing the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 3A, the CPU310 accesses the lock 334 corresponding to the FTL entry 324. In the example of FIG. 3, the lock 334 indicates that the FTL entry 324 is not locked, and the CPU310 modifies the lock 334 to indicate a lock on the FTL entry 324. In an embodiment according to the present invention, when a write command is processed, a lock of an FTL entry to be modified by the write command is acquired. When the lock cannot be acquired, processing of the write command is temporarily suspended and release of the lock is awaited. In the example of FIG. 3A, after time t1, the CPU310 obtains a lock for the FTL entry 324. At this time, when other CPUs access the FTL entry 324 for processing the write command, since the lock 334 is found to indicate that the FTL entry 324 is locked, the processing of the write command accessing the FTL entry 324 is terminated.

Still referring to fig. 3A, the CPU314 processes a read command from the host and accesses the FTL entry 324 at time t2 according to the logical address of the read command. Although FTL entry 324 is already locked, in the embodiment according to the present invention, CPU314 ignores the lock of FTL entry 324, still obtains FTL entry 324, and obtains the physical address to be accessed according to FTL entry 324. Further, the CPU314 or other CPUs read data by the physical address and provide the read data to the host as a response to the read command. Because the read command is processed without checking whether the FTL entry 324 is locked, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces read command processing time since there is no need to wait for the lock of FTL entry 324 to be released when processing read commands.

In the example of FIG. 3A, to process a write command, the CPU310 assigns a new physical address to the write command and updates the FTL entry 324 with the new physical address, and at time t3, the CPU310 completes the update of the FTL entry 324 (indicated in FIG. 3 by W-t 3). And also writes data to the new physical address in response to the write command. The data may be written to the new physical address by CPU310 or other CPU. Thus, at time t2, which is before time t3, the CPU314 obtains the old physical address from the FTL entry 324, and after time t3, the new physical address (updated by the CPU310 in processing write commands) is obtained from the FTL entry 324 in response to a read command. Therefore, when processing the read command, if the CPU314 accesses the FTL entry 324 before the time t3, a different physical address is obtained by accessing the FTL entry 324 after the time t3, and different data is read. Such results conform to protocols such as NVMe protocol that do not require the order of processing of IO commands.

In one example, the lock 334 and the FTL entry 324 are stored separately from each other. To process a read command, the CPU314 accesses the FTL entry 324 without accessing the lock 334. In another example, the lock 334 is stored in the same storage location as the FTL entry 324. While processing read commands, the CPU314 will obtain the contents of the lock 334 while accessing the FTL entry 324, but the CPU314 need not process the contents of the lock 334, but instead only care about the physical address provided by the FTL entry 324.

With continued reference to fig. 3A, the granularity of the lock is for each FTL entry. In response to the IO command, CPU 312 accesses FTL entry 328. For read commands, the CPU 312 ignores the lock 338 corresponding to the FTL entry 328; for write commands, CPU 312 checks lock 338 corresponding to FTL entry 328, and continues processing write commands only if lock 338 indicates that FTL entry 328 is not locked, and suspends processing write commands or defers updating FTL entry 328 if lock 338 indicates that FTL entry 328 is locked.

Fig. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present invention. Read or write commands from the host access different lengths of data and different numbers of FTL entries. In an embodiment consistent with the invention, the granularity of locking is per FTL entry. By way of example, the CPU310 processes a write command from the host, the write command accessing 3 logical addresses, and the CPU310 accesses the FTL entry 320, the FTL entry 322, and the FTL entry 324 (indicated by W1-t1, W2-t1, and W3-t1 of FIG. 3B) at time t1 to allocate a physical address for the write command. CPU310 also requests locks corresponding to the entries when accessing FTL entries, by accessing lock 330, lock 332, and lock 334 to request locks corresponding to FTL entries 320, FTL entries 322, and FTL entries 324. When the corresponding lock is acquired, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry with the new physical address, and when the corresponding lock cannot be acquired, the CPU310 stops the operation on the corresponding FTL entry and waits for the corresponding lock to be released. For example, the CPU310 obtains the lock of the FTL entry 320 and the FTL entry 322, but does not obtain the lock of the FTL entry 324, the CPU310 continues to update the FTL entry 320 and the FTL entry 322 by subsequent processing, and suspends the operation on the FTL entry 324 until the lock 334 of the FTL entry 324 is released and obtained by the CPU310, and the CPU310 continues to update the FTL entry 324. In response to the FTL entry being updated, data is also written to the new physical address in response to the write command. And when the new physical addresses of the three FTL table entries corresponding to the write command are all written with data, completing the write command processing.

Still referring to FIG. 3B, the CPU314 processes the read command from the host, and accesses the FTL entry 324 (denoted as R-t2 in FIG. 3B) at time t2 according to the logical address of the read command. Although FTL entry 324 has been locked by CP U310 when processing write commands, in an embodiment according to the present invention, CPU314 ignores the lock of FTL entry 324, still obtains FTL entry 324, and obtains the physical address to be accessed according to FTL entry 324. Further, the CPU314 or other CPUs read data by the physical address and provide the read data to the host as a response to the read command. Because the read command is processed without checking whether the FTL entry 324 is locked, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces read command processing time since there is no need to wait for the lock of FTL entry 324 to be released when processing read commands.

Fig. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present invention. In the illustrated embodiment, FIG. 3C is an illustration of how multiple IO commands may be processed in parallel on the same CPU. By way of example, the CPU310 processes a write command from the host, and the CPU310 accesses the FTL entry 324 (indicated by W1-t2 of FIG. 3C) at time t1 to assign a physical address for the write command based on the logical address indicated by the write command. The CPU310 also requests a lock corresponding to the entry when accessing the FTL entry, and requests a lock corresponding to the FTL entry 324 by accessing the lock 334. Upon acquiring the corresponding lock, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry 324 with the new physical address at time t3 (the updating of the FTL entry 324 is indicated by W3-t3 of fig. 3C). Between times t1 and t3, CPU310 also accesses FT L entry 324 at time t2 in response to the host's read command. Although at time t2, the lock 334 indicates that the FTL entry 324 is locked, for a read command, the CPU310 still accesses and uses the FTL entry 324 to read data using the physical address provided by the FTL entry 324 even though there is a lock on the FTL entry 324. In further embodiments, the CPU310 caches the FTL entry 324 retrieved at time t1, and retrieves the contents of the FTL entry 324 from the CPU310 cache at time t 2. And for processing read commands, whether or not the FTL entry 324 cached by the CPU310 is updated, reading data using the physical address provided by the cached FTL entry 324. At time t2, the CPU314 accesses the FTL entry 324 (shown in FIG. 3C as R3-t 2) in response to the logical address of another read command. Because of the read command, although the lock 334 indicates that the FTL entry 324 is locked, the CPU314 still accesses and uses the FTL entry 324 and reads data with the physical address provided by the FTL entry 324.

Fig. 4A is a flow diagram of accessing an FTL table for processing a write command according to an embodiment of the present invention. In an embodiment consistent with the invention, in response to receiving a write command (410) to access a logical address of a first FTL entry, it is checked (420) whether the first FTL entry is locked. If the first FTL table entry is locked, stopping the subsequent processing of the first FTL table entry and waiting for the lock of the first FTL table entry to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, to process the write command, the first FTL entry is locked (430) so that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is assigned to the write command, the first FTL entry is updated with the first physical address, the updated FTL entry is written into the FTL table, and the first FTL entry is unlocked (440). Assigning a new physical address for a write command may utilize a variety of means known in the art. And writing data corresponding to the write command to the first physical address (450).

In another example, when the first FTL entry corresponding to the logical address of the write command is accessed in response to receiving the second write command, and the first FTL entry is found to be locked, the processing of the second write command is completed without allocating a physical address for the second write command and without writing data corresponding to the second write command to the nonvolatile memory.

Fig. 4B is a flow diagram of accessing an FTL table for processing a write command according to an embodiment of the present invention. In response to receiving the read command, the logical address of the read command corresponds to the first FTL entry (432). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 430 of fig. 4A), the locked first FTL entry is obtained from the FTL table and used when processing the read command (434). And reading the data (436) in response to the read command based on the first physical address.

In another example, when a first FTL entry is obtained for processing a read command, if the first FTL entry is locked, it indicates that there is a write command in execution accessing the first FTL table, and the data to be written by the write command is in the cache. And searching data to be written by the write command accessing the first FTL table from the cache as read data of the read command. The speed of obtaining data from the cache is far faster than the speed of obtaining data from the nonvolatile memory chip, so that the processing time of the read command is further reduced by using the cached data to be written as a response to the read command.

Fig. 5A is a schematic diagram of a control section of a storage device accessing an FTL table according to yet another embodiment of the present invention.

The control section 504 of the solid state disk includes a plurality of CPUs (CPU 510, CPU 512, CPU 514), each of which is capable of accessing the FTL table external to the control section 304. The CPU of the control unit also accesses the NVM chip 505 through the flash interface. NVM chip 505 includes a plurality of memory cells, such as memory cell 550, memory cell 552, memory cell 560, and memory cell 562. By way of example, the CPU 510 processes a write command from the garbage collection task and accesses the FTL entry 524 (indicated by W g-t1 of FIG. 5A) at time t1 in accordance with the logical address indicated by the write command to assign a physical address to the write command. To avoid multiple write commands writing the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 5A, CPU 510 accesses lock 534 corresponding to FT L entry 524. In the example of FIG. 5A, CPU 510 modifies lock 534 to indicate a lock on FTL entry 524.

Still referring to FIG. 5A, the CPU 514 processes the read command from the host, accessing the FTL entry 524 (indicated by R-t2 in FIG. 5A) at time t2 based on the logical address of the read command. Although FTL table 5324 is locked, in the embodiment according to the present invention, CPU 514 ignores the lock of FTL table entry 524 when processing the read command, still obtains FTL table entry 524, and obtains the physical address to be accessed according to FTL table entry 524. The CPU 514 accesses the physical address of the NVM chip 505 through the flash interface according to the acquired physical address and acquires data to be read.

In the example of FIG. 5A, to process a write command from a garbage collection task, CPU 510 assigns a new physical address to the write command and updates FTL entry 524 with the new physical address, and at time t3, CPU 510 completes the update to FTL entry 524 (indicated in FIG. 5A by Wg-t 3). And also writes data to the new physical address in response to the write command.

In some cases, the physical address accessed when the CPU 514 processes the read command is a physical block in the NVM chip 505 that is in an erased state. The physical block in the erased state has no valid data and should not be read. FIG. 5B is a sequence diagram illustrating the reason that the CPU 514 reads an erase block in the NVM chip 505 for processing the IO request according to the embodiment of FIG. 5A of the present invention. In fig. 5B, the time axis shows the direction of the passage of time. In response to Garbage Collection (GC) write command 560, CPU 510 accesses FTL entry 524 (indicated by Wg-t1 of FIG. 5A) at time t1 according to the logical address indicated by write command 560, FTL entry 524 is locked, and the physical address of FTL table 524 indicates memory location 550 of NVM chip 505. In processing the GC write command (560), FTL entry 524 is next updated by CPU 510, and the updated physical address of FTL entry 524 indicates storage unit 560.

After FTL entry 524 is locked, a user read command is received (570), CPU 514 processes the user read command (570) and obtains FTL entry 524. Since the lock 534 of the FTL entry 524 is ignored when the CPU 514 acquires the FTL entry 524, and the timing of acquiring the FTL entry 524 is before the FTL entry 524 is updated by the CPU 510, the physical address acquired from the FTL entry 524 indicates the storage unit 550.

With continued reference to fig. 5B, the GC write command 560 is followed by a GC erase command 562, and the affected old physical address (memory location 550) of the GC write command 560 is erased in response to the GC erase command 562. So that the memory cells 550 of the NVM chip are in an erased state. And CPU 514 obtains old FTL entry 524 for processing user read command 570 and issues the read command to storage unit 550 through the flash interface. The two operations, i.e., the CPU 514 issuing a read command to the memory unit 550 and the CPU 510 issuing an erase command to the memory unit 550, may occur in any order, so that when the CPU 514 issues a read command, the memory unit 550 may be in an erased state, and thus the read command may not be correctly processed.

In an embodiment in accordance with the invention (see fig. 5A), to address the above-described problem, the control component 504 also maintains a block status table 540. In the block state table 540, it is recorded whether each physical block of the NVM chip 550 is in an erased state or in an already written state. In one example, when a physical block is erased, block status table 540 is updated to identify that the physical block is in an erased state. When the physical block is written for the first time, block status table 540 is updated to identify that the physical block is in a written state. Before the CPU 514 issues a read command to the NVM chip 505 through the flash interface, the physical block where the physical address is located is obtained by using the physical address obtained from the FTL entry 524, and the state of the physical block is looked up in the block state table 540. If the physical block is in a written state, the CPU 514 issues a read command to the NVM chip 505 through the flash interface; if the physical block is in the erased state, the CPU 514 instructs to replay the read command. By way of example, replaying a read command means that the control section 504 treats the read command as a newly received read command and reprocesses it. Because of the time required for re-processing, when FTL entry 524 is re-acquired, its contents have been updated with a high probability, and newly acquired FTL entry 524 will provide an updated physical address in which valid data is stored. In a few cases, for example, when FTL entry 524 is obtained again, the update of FTL entry 524 is still not completed, and the obtained FTL entry is still the old physical address in the erased state. In this case, in one example, the read command is replayed again to retrieve the FTL entry 524; in yet another example, CPU 514 further identifies lock 534 corresponding to FTL entry 524. If the lock 534 indicates that the FTL entry 524 is locked, the CPU 514 waits for the release of the lock 534 to obtain the updated FTL entry 524, and then accesses the NVM chip 505 with the physical address provided by the updated FTL entry 524; if lock 534 indicates that FTL entry 524 is not locked, NVM chip 505 is immediately accessed with the physical address provided by FTL entry 524.

FIG. 6 is a schematic diagram of the organization of physical blocks of an NVM into a block stripe in accordance with an embodiment of the present invention. In the solid-state storage device shown in FIG. 6, a block stripe is constructed on every 16 logical units (LUN0, LUN1, … … LUN15), and physical blocks of the same physical address within each logical unit constitute a "block stripe".

In FIG. 6, block B0 with address 0 in LUN0-LUN15 constitutes block stripe 0, where physical blocks B0 of LUN0-LU N14 are used to store user data, and physical block B0 of LUN15 is used to store parity data calculated from user data within the block stripe. The physical blocks of the NVM include a plurality of pages, the physical pages in a block stripe having the same address constitute a page stripe, and check data is calculated for each page stripe. For example, each physical page in physical block B0 of LUN15 stores check data calculated from all user data of the page stripe in which the physical page resides.

Similarly, in FIG. 6, physical block B2, address 2, of LUN0-LUN15 is block stripe 2. Alternatively, the physical block used to store the check data may be located in any LUN in the block stripe. In the example of fig. 6, when the data of 1 physical page of a block stripe is damaged by the parity data in the block stripe, the data of the damaged page can be recovered from the other pages of the page stripe where the physical page is located.

Those skilled in the art will appreciate that the block strips may be constructed in a variety of other data organization manners. Multiple physical blocks are included in a block stripe, and data protection is provided in the block stripe through redundancy or RAID techniques. So that in case one or several physical blocks in a block stripe are corrupted, the data of the corrupted physical blocks can be reconstructed by the other blocks of the block stripe. Erasing is performed in units of block stripes. When an erase operation is performed, all physical blocks belonging to a stripe of blocks are erased together.

Fig. 7 is a schematic diagram of a control section of a storage device accessing an FTL table according to still another embodiment of the present invention. In contrast to fig. 5A, in the embodiment of fig. 7, control unit 504 further includes CPU516, and block stripes 750, 752, 754, 756, and block stripe status table 740 for recording the status of each block stripe on NVM 705. In block stripe state table 740, a plurality of entries (entry 760, entry 762, entry 764, and entry 766) are included, each recording whether a corresponding block stripe of NVM705 is in an erased state or in an already written state. In one example, when a block stripe is erased, the block stripe state table 740 is updated to identify that the block stripe is in an erased state. When the block stripe is written for the first time, block stripe status table 740 is updated to identify that the physical block is in a written state.

In the FIG. 7 embodiment, to process a read command, CPU 514 accesses FTL entry 524 and provides the physical supply provided by FTL entry 524 to CPU 516. CPU516 issues a read command to NVM705 through the flash interface. Before the CPU516 issues a read command to the NVM705 through the flash interface, the physical address obtained from the FTL entry 524 is used to obtain the block stripe where the physical address is located, and the state of the block stripe is looked up in the block stripe state table 740. If the block is in the written state, CPU516 issues a read command to NVM705 via the flash interface; if the physical block is in the erased state, the CPU516 instructs to replay the read command. In rare cases, for example, when FTL entry 524 is retrieved, the update of FTL entry 524 is still not completed, and the retrieved FTL entry provides the old physical address in the erased state. In this case, in one example, the read command is replayed again to retrieve the FTL entry 524; in yet another example, CPU516 further identifies lock 534 corresponding to FTL entry 524. If lock 534 indicates that FTL entry 524 is locked, CPU 614 waits for release of lock 534 to obtain updated FTL entry 524, and then provides the physical address provided by updated FTL entry 524 to CPU 516; if lock 534 indicates that FTL entry 524 is not locked, the physical address provided by FTL entry 524 is immediately provided to CPU 516.

Fig. 8A is a flow diagram of accessing an FTL table for processing a write command according to still another embodiment of the present invention. In the embodiment according to fig. 8, in response to receiving a write command to access a logical address of a first FTL entry (802), it is checked whether the first FTL entry is locked (804). If the first FTL table entry is locked, stopping the subsequent processing of the first FTL table entry and waiting for the lock of the first FTL table entry to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, to process the write command, the first FTL entry is locked (806) so that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is allocated for the write command, the first FTL entry is updated with the first physical address, the updated FTL entry is written into the FTL table, and the first FTL entry is unlocked (808). Assigning a new physical address for a write command may utilize a variety of means known in the art. And writing data corresponding to the write command to the first physical address (809).

Fig. 8B is a flow diagram of accessing an FTL table for processing a write command according to still another embodiment of the present invention. In response to receiving the read command, the logical address of the read command also corresponds to the first FTL entry (810). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 806 of fig. 8A), the first physical address provided by the first FTL entry is obtained from the FTL table and used when processing the read command (820). Next, the corresponding physical block or block stripe is obtained according to the first physical address, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A, 540) or the block stripe state table (see fig. 7, 740). If the retrieved status indicates that the physical block or block stripe in which the first physical address is located is in an erased state (830), the read command is replayed, in other words, the read command is reprocessed, via step 810. If the retrieved status indicates that the physical block or block stripe in which the first physical address is located is in a written state 830, data is read from the first physical address in response to the read command 840.

Fig. 9A is a flow diagram of accessing an FTL table for processing an IO command according to an embodiment of the present invention. In the embodiment of FIG. 9A, in response to receiving a read command, the logical address of the read command corresponds to the first FTL entry (910). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command, the first physical address provided by the first FTL entry is obtained 920 from the FTL table and used when processing the read command. Next, a read command is sent to the NV M according to the first physical address to read data from the first physical address (920). Whether a physical page corresponding to the first address is in an erased state is indicated in the result of reading the data 930. In one example, the NVM chip provides such an indication in the results of reading the data to identify whether the physical page being read is in an erased state. In another example, the flash interface of the control unit determines whether the read data is from a physical page in an erased state based on the data read from the NVM chip.

With continued reference to FIG. 9A, if the result of reading the data indicates that the physical page corresponding to the first physical address is in the erased state, the step 910 is returned to replay the read command. If the read data result indicates that the physical page corresponding to the first physical address is not in the erased state, the read data is valid, and the read command processing is completed with the read data as a response to the read command (940).

In the embodiment of fig. 9A, after the first physical address is obtained, it is not checked whether the physical block or block stripe where the first physical address is located is in an erased state. The probability that the physical block or block stripe where the first physical address is located is in an erased state is low and in most cases the operation of checking whether it is in an erased state will introduce additional delay. In the embodiment of fig. 9A, after the first physical address is obtained, the data is read out directly from the first physical address without checking whether the physical block or block stripe where the first physical address is located is in the erased state, and it is determined whether the read physical page is in the erased state depending on the indication provided by the result of reading the data. Therefore, the additional processing is carried out only when the read physical page is in an erasing state, and the average processing delay of the read command is reduced.

Fig. 9B is a flow diagram of accessing FTL table for processing IO commands according to still another embodiment of the present invention. The embodiment of fig. 9B is similar to the embodiment of fig. 9A, except that when data is read from the first physical address, and it is determined whether the physical page corresponding to the first address is in an erased state in the result of reading the data (980), if the result of reading the data indicates that the physical page corresponding to the first physical address is in an erased state, the corresponding physical block or block stripe is obtained according to the first physical address, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A, 540) or the block stripe state table (see fig. 7, 740) (990). If the physical block or block stripe in which the first physical address is located is in a written state (990), then the result of reading data from the first physical address indicates that the physical page is in an erased state regardless of whether the first FTL entry is locked, but that the data stored at the first physical address is corrupted, indicating a failed read command processing as a response to the read command (995). If the physical block or block stripe where the first physical address is located is in an erased state (990), return to step 950 to replay the read command. If the data is read from the first physical address and the result of reading the data indicates that the physical page corresponding to the first physical address is not in an erased state (980), the read data is used as a response to the read command and the read command processing is completed (985).

Still referring to fig. 9B, in another example, when data is read from the first physical address for the first time through step 980 and it is determined that the physical page corresponding to the first address is in an erased state in the result of reading the data (980), the read command is directly replayed as indicated by a dotted line in fig. 9B. When the same read command is replayed and step 980 is passed for the second time, if it is determined again that the physical page corresponding to the first address is in the erased state in the result of reading the data (980), the process proceeds to step 990, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A and 540) or the block stripe state table (see fig. 7 and 740).

In the embodiment of fig. 9B, when the read physical page is a physical page in an erased state, a different processing strategy is adopted to obtain better error processing efficiency.

Fig. 9C is a flow diagram of accessing an FTL table for processing an IO command according to still another embodiment of the present invention. The embodiment of FIG. 9B is similar to the embodiment of FIG. 9C, except that when data is read from the first physical address, and it is determined (980) whether the physical page corresponding to the first address is in an erased state, it is queried (992) whether the first FTL entry is locked. If the first FTL entry is not locked (992), the result of reading data from the first physical address indicates that the physical page is in an erased state regardless of whether the first FTL entry is locked, but that the data stored at the first physical address is corrupted, indicating a read command processing failure as a response to the read command (995). If the first FTL entry is locked (992), the data reading result from the first physical address indicates that the physical page is in the erase state and is related to the first FTL entry being locked, waits for the lock of the first FTL entry to be released, acquires the first FTL entry again and obtains the updated second physical address provided by the first FTL (994). And issuing an access command to the NVM at the second physical address, reading data (996) from the second physical address of the NVM in response to the read command.

Still referring to fig. 9C, in another example, when the data is read from the first physical address for the first time after step 980 is passed, and it is determined that the physical page corresponding to the first address is in the erased state in the result of reading the data (980), the process returns to step 950 to directly replay the read command, as indicated by the dotted line in fig. 9C. If the same read command passes through step 980 for the second time due to being replayed, if it is determined again that the physical page corresponding to the first address is in the erased state in the result of reading the data (980), the process proceeds to step 992, and it is queried whether the first FTL entry is locked, and the subsequent processing is performed.

In the embodiment of fig. 9C, when the read physical page is a physical page in an erased state, a different processing strategy is adopted to obtain better error processing efficiency.

Fig. 10A is a schematic diagram of a control section of a storage device accessing an FTL table according to yet another embodiment of the present invention. In fig. 10A, the control unit 1004 of the solid state disk includes a plurality of CPUs (CPU 1010, CPU 1012, CPU 1014) each capable of accessing the FTL table external to the control unit 1004. The CPU of the control section also accesses the NVM chip 1005 through the flash interface. NVM chip 1005 includes multiple memory cells, such as memory cell 1050, memory cell 1052, memory cell 1060, and memory cell 1062. By way of example, CPU1010 processes commands from a write. The write command may come from the host or from a garbage collection operation or other request to write data. The FTL entry 1024 (indicated by W-t1 of FIG. 10A) is accessed at time t1 according to the logical address indicated by the write command to assign a physical address for the write command. To avoid multiple write commands writing the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 10A, CPU1010 accesses lock 1034, which corresponds to FT L entry 1024. In the example of FIG. 10A, CPU1010 modifies lock 1034 to indicate a lock on F TL entry 1024.

In the example of FIG. 10A, to process a write command, CPU1010 assigns a new physical address to the write command and updates FTL entry 524 with the new physical address, and at time t2, CPU1010 completes the update of FTL entry 1024 (indicated in FIG. 10A by Wg-t 2). And also responds to the write command by writing data to the new physical address through the flash interface (indicated by W-t5 in fig. 10A).

Still referring to FIG. 10A, the CPU1014 processes a read command from the host, accessing the FTL entry 1024 (indicated by R-t3 in FIG. 10A) at time t3 based on the logical address of the read command. And acquiring the physical address to be accessed according to the FTL table entry 1024. CPU1014 accesses NVM chip 1005 (indicated by R-t4 in FIG. 10A) via the flash interface according to the retrieved physical address.

In the example of FIG. 10A, the CPU1014 obtaining the FTL entry 1024 (indicated by R-t3 in FIG. 10A) occurs after the CPU1010 updates the FTL entry 1024 (indicated by Wg-t2 in FIG. 10A), and thus the CPU1014 obtains the updated FTL entry 1024. However, accessing the N VM chip by the CPU1014 through the flash interface (indicated by R-t4 in FIG. 10A) occurs before the CPU1010 writes data to a new physical address (indicated by W-t5 in FIG. 10A) through the flash interface. Thus, it is possible that when the CPU1014 accesses the NVM chip 1005 via the flash interface with the physical address provided by the FTL entry 1024, the memory location accessed by the physical address has not been written with data yet and may be in an erased state. The physical block in the erased state has no valid data and should not be read.

FIG. 10B is a sequence diagram illustrating the reason that CPU1014 reads an erased memory location in NVM chip 1005 according to the embodiment of FIG. 10A of the present invention. In fig. 10B, the time axis shows the direction of the passage of time. In response to the write command 1060, CPU1010 accesses FTL entry 1024 (indicated by W-t1 of fig. 10A) at time t1 according to the logical address indicated by the write command 1060, FTL entry 1024 is locked, and the physical address of FTL table 1024 indicates the memory unit 1050 of NVM chip 1005. In processing the write command (1060), next, FTL entry 1024 is updated by CPU1010, and the updated physical address of FTL entry 1024 indicates storage unit 1060. And optionally the lock of FTL entry 1024 is released.

Next, upon receiving a user read command (1070), the CPU1014 processes the user read command (1070) and obtains the FTL entry 1024. Since the timing for the CPU1014 to acquire the FTL entry 1024 is after the FTL entry 1024 is updated by the C PU1010, the physical address acquired from the FTL entry 1024 indicates the storage unit 1060.

With continued reference to FIG. 10B, at time t4, CPU1014 issues a read command to NVM chip 1005 to read the physical address 1060 of NVM chip 1005 (see also R-t4 of FIG. 10A); and at time t5 after time t4, the CPU1010 issues a write command to the physical address 1060 of the NVM chip 1005 (see also W-t5 of FIG. 10A). The NVM chip 1005 has received a read command to physical address 1060 prior to receiving a write command to physical address 1060.

However, before the physical address 1060 of the NVM chip 1005 is written, it is in an erased state and results in a read command that cannot be properly processed by the flash interface. In the prior art, the minimum unit of erase of an NVM storage medium such as flash memory is a block, and the minimum unit of read/write is a page, the block including a plurality of pages. Thus, in NVM die 1005, there may be states where partial pages in a block have been written with data while other pages are still in an erased state.

In an embodiment according to the present invention (see fig. 10A), to solve the above problem, the control section 1004 further maintains a write position table 1042. The write position table 1042 records the position to be currently written in the block or block stripe currently being written. The location to be currently written may be a page (indicated by a page address or page number) in the physical block, or may be a location to be written in a page stripe in a block stripe. And in response to a write command, the control unit 1004 sequentially allocates physical addresses to be written to the write command in an embodiment in accordance with the present invention. For example, the current write position is page 100 of block 100 of the N VM chip 1005, and when a physical address is allocated for a write command, the physical address of page 100 of block 100 is allocated to the write command, and the allocated physical address is recorded in an entry of the FTL table, and the current write position is incremented (to page 101 of block 100). And responds to the write command again, a physical address of a new current write location (page 101 of the 100 th block) is allocated for the write command. Alternatively, the control unit 1004 only writes data to one or a small number of physical blocks at a time, and thus only one or a small number of entries need to be provided in the write position table 1042 without occupying a large amount of storage space. In another example, the current write location indicates a Logical Unit (LUN) of a page stripe to be currently written, e.g., a page corresponding to the 3 rd logical unit of the 100 th page stripe of the 100 th block stripe. When allocating a physical address for a write command, the physical address of a page corresponding to the 3 rd logical unit of the 100 th page stripe of the 100 th block stripe is allocated to the write command, and the allocated physical address is recorded in an entry of the ftl table, and the current write position is incremented (to a page corresponding to the 4 th logical unit of the 100 th page stripe of the 100 th block stripe). And when the write command is responded again, a new physical address of the current write location (the page corresponding to the 4 th logical unit of the 100 th page stripe of the 100 th block stripe) is allocated for the write command. Alternatively, the control unit 1004 only writes data to one or a small number of block stripes at a time, and thus only one or a small number of entries need to be provided in the write position table 1042 without taking up a large amount of storage space.

The control unit 1004 also maintains a block status table 1040. In the block state table 1040, it is recorded whether each physical block of the NVM chip 1005 is in an erased state or in an already written state. In one example, when a physical block is erased, block status table 1040 is updated to identify that the physical block is in an erased state. When the physical block is first written, block status table 1040 is updated to identify that the physical block is in a written state. Before the CPU1014 issues a read command to the NVM chip 1005 via the flash memory interface, the physical block where the physical address is located is obtained by using the physical address obtained from the FTL entry 1024, and the state of the physical block is queried in the block state table 1040. If the physical block is in a written state, CPU1014 issues a read command to NVM chip 1005 via the flash interface; if the physical block is in the erased state, the CPU1014 instructs to replay the read command.

FIG. 11A is a flow diagram of processing a write command according to an embodiment of the invention. In the embodiment according to FIG. 11A, in response to receiving a write command to access a logical address of a first FTL entry (1102), it is checked whether the first FTL entry is locked (1104). If the first FTL table entry is locked, stopping the subsequent processing of the first FTL table entry and waiting for the lock of the first FTL table entry to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, to process the write command, the first FTL entry is locked (1106) so that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is assigned to the write command, the first FTL entry is updated with the first physical address, the updated FTL entry is written into the FTL entry, and a lock on the first FTL entry is released (1108). Assigning a new physical address for a write command may utilize a variety of means known in the art. And writing data corresponding to the write command to the first physical address (1109).

FIG. 11B is a flow diagram of processing a read command according to an embodiment of the invention. In response to receiving the read command, the logical address of the read command also corresponds to the first FTL entry (1110). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 1106 of fig. 11A), the first physical address provided by the first FTL entry is obtained from the FTL table and used when processing the read command (1120). Next, the corresponding physical block or block stripe is obtained according to the first physical address, and whether the current writing position of the physical block or block stripe is ahead of the first physical address is compared (1130). The current write location of the physical block or block stripe is retrieved from the write location table (see fig. 10, write location table 1042) and compared to the first physical address retrieved from the first FTL entry. If the current write location is ahead of the first physical address, indicating that the first physical address has been written with data, a read command is issued to the first physical address and the data is read (1140). If the current writing position does not lead or lag the first physical address, indicating that the first physical address has not been written with data, the correct data cannot be read from the first physical address, and thus the processing of the read command is suspended, and the current writing position is waited for to lead the first physical address. After the current write location leads the first physical address, data is read from the first physical address (1140).

FIG. 11C is a flow diagram of processing an IO command in accordance with yet another embodiment of the present invention. In response to receiving the read command, the logical address of the read command also corresponds to the first FTL entry (1150). For read commands, it is not checked whether the first FT L entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 1106 of fig. 11A), the first physical address provided by the first FTL entry is obtained from the FTL table and used when processing the read command (1160). Next, the corresponding physical block or block stripe is obtained according to the first physical address, and the state of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A, 540) or the block stripe state table (see fig. 7, 740). If the retrieved status indicates that the physical block or block stripe in which the first physical address is located is in an erased state (1170), then the read command is replayed, in other words, reprocessed, via step 1150. If the obtained status indicates that the physical block or block stripe where the first physical address is located is in a written state (1170), the corresponding physical block or block stripe is obtained according to the first physical address, and whether the current writing position of the physical block or block stripe is ahead of the first physical address is compared (1180). The current write location of the physical block or block stripe is retrieved from the write location table (see fig. 10, write location table 1042) and compared to the first physical address retrieved from the first FTL entry. If the current write location is ahead of the first physical address, indicating that the first physical address has been written with data, a read command is issued to the first physical address and the data is read 1190. If the current writing position does not lead or lag the first physical address, indicating that the first physical address has not been written with data, the correct data cannot be read from the first physical address, and thus the processing of the read command is suspended, and the current writing position is waited for to lead the first physical address. After the current write position leads the first physical address, data is read from the first physical address (1190).

FIG. 12A is a flow diagram of processing an IO command according to another embodiment of the invention. In the embodiment of fig. 12A, in response to receiving a read command, the logical address of the read command corresponds to the first FTL entry (1210). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command, the first physical address provided by the first FTL entry is obtained from the FTL table and used when processing the read command (1220). Next, a read command is sent to the NVM in accordance with the first physical address to read data from the first physical address (1225). Whether the physical page corresponding to the first address is in an erased state is indicated in the result of reading the data 1230. If the read data result indicates that the physical page corresponding to the first physical address is in an erased state, it is further determined whether the current write position is ahead of the first physical address (1245). As an example, the corresponding physical block or block stripe is obtained according to the first physical address, and the current writing location of the physical block or block stripe is obtained from the writing location table (see fig. 10, writing location table 1042). If the current write location leads the first physical address, indicating that the first physical address has been written with data, a read command is issued to the first physical address and the data is read (1248). If the current writing position does not lead or lag the first physical address, indicating that the first physical address has not been written with data, the correct data cannot be read from the first physical address, and thus the processing of the read command is suspended, and the current writing position is waited for to lead the first physical address. After the current write position leads the first physical address, data is read from the first physical address (1248). If the result of reading the data indicates that the physical page corresponding to the first physical address is not in the erased state (1230), the read data is valid, and the read command processing is completed with the read data as a response to the read command (1240).

In the embodiment of fig. 12A, after the first physical address is obtained, it is not first checked whether the physical block or block stripe where the first physical address is located is in an erased state. Since the probability that the physical block or block stripe where the first physical address is located is in the erased state is low, in most cases, the operation of checking whether it is in the erased state will introduce additional delay. In the embodiment of fig. 12A, after the first physical address is obtained, data is read out directly from the first physical address without first checking whether the physical block or block stripe where the first physical address is located is in an erased state, and it is determined whether the read physical page is in an erased state depending on an indication provided by the result of reading the data. Therefore, the additional processing is carried out only when the read physical page is in an erasing state, and the average processing delay of the read command is reduced.

FIG. 12B is a flow diagram of processing an IO command according to another embodiment of the invention. The embodiment of fig. 12B is similar to the embodiment of fig. 9A, except that when the data is read from the first physical address, and it is determined whether the physical page corresponding to the first address is in the erased state in the result of reading the data (1230), if the result of reading the data indicates that the physical page corresponding to the first physical address is in the erased state, the corresponding physical block or block stripe is obtained according to the first physical address, and the state 1250 of the corresponding physical block or block stripe is obtained from the block state table (see fig. 5A, 540) or the block stripe state table (see fig. 7, 740). If the physical block or block stripe where the first physical address is located is in a written state (1250), a further determination is made as to whether the current write location is ahead of the first physical address (1260). If the current write location leads the first physical address, indicating that the first physical address has been written with data, a read command is issued to the first physical address and the data is read 1270. If the current writing position does not lead or lag the first physical address, indicating that the first physical address has not been written with data, the correct data cannot be read from the first physical address, and thus the processing of the read command is suspended, and the current writing position is waited for to lead the first physical address. After the current write location leads the first physical address, data is read from the first physical address (1270). If the physical block or block stripe where the first physical address is located is in an erased state (1250), the first FTL entry is accessed again and the updated second physical address is obtained from the first FTL entry (1255). And then, judging the relationship (1260) between the second physical address and the current writing position and carrying out subsequent processing.

Embodiments of the present invention also provide a program comprising program code which, when loaded into and executed on a CPU, causes the CPU to perform one of the methods according to embodiments of the present invention provided above.

Embodiments of the present invention also provide a program comprising program code, which, when loaded into and executed on a storage device, causes the processor of the storage device to perform one of the methods according to embodiments of the present invention provided above.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the invention, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the invention.

Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method of processing an IO request, comprising:

responding to the received first read request, accessing a first FTL table entry corresponding to the first read request, and acquiring a first physical address recorded by the first FTL table entry;

if the physical block or the large block containing the first physical address is in an erased state, replaying the first read request; and

if the current write location is behind the first physical address, processing of the first read request is suspended until the current write location is ahead of the first physical address.

2. The method of handling IO requests according to claim 1, wherein

Said replaying said first read request comprises: accessing a first FTL table entry corresponding to the first read request, and acquiring a second physical address recorded by the first FTL table entry; if the physical block or chunk containing the second physical address is in a written state, and if the current write position is ahead of the second physical address, reading data from the second physical address in response to the first read request.

3. A method of processing an IO request, comprising:

responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; allocating a first physical address to the write request, updating a first FTL table entry by using the first physical address, unlocking the first FTL table entry, writing data into the first physical address, and updating the current write position;

responding to the received read request, accessing a first FTL table entry corresponding to the read request, and acquiring a first physical address recorded by the first FTL table entry; if the current writing position is behind the first physical address, suspending the processing of the first reading request until the current writing position is ahead of the first physical address;

in response to receiving a second write request, if the first FTL entry is locked, processing of the second write request is aborted until the lock of the first FTL entry is released.

4. The method of handling IO requests according to claim 3, further comprising: responding to the received read request, accessing a first FTL table entry corresponding to the read request, and acquiring a first physical address recorded by the first FTL table entry; and if the physical block containing the first physical address is in an erasing state, replaying the read request.

5. A method of handling IO requests according to claim 3 or 4, wherein allocating a first physical address to the write request includes using a current write location as the first physical address and incrementing the current write location.

6. An apparatus to process IO requests, comprising:

the FTL entry accessing module is configured to, in response to receiving the first read request, access a first FTL entry corresponding to the first read request to obtain a first physical address recorded in the first FTL entry; and

and the current write position processing module is used for reading data from the first physical address to respond to the first read request if the physical block or the large block containing the first physical address is in a written state and if the current write position is ahead of the first physical address.

7. An apparatus to process IO requests, comprising:

the current writing position processing module is used for reading data from the first physical address; if the result of reading data from the first physical address indicates that the physical page where the first physical address is located is in an erased state, if the current writing position is behind the first physical address, the processing of the first read request is suspended until the current writing position is ahead of the first physical address.

8. An apparatus to process IO requests, comprising:

the current writing position processing module is used for reading data from the first physical address; if the result of reading data from the first physical address indicates that the physical page in which the first physical address is located is in an erased state and the physical block or chunk containing the first physical address is in a written state, processing of the first read request is suspended until the current write location leads the first physical address.

9. An apparatus to process IO requests, comprising:

the write request processing module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; allocating a first physical address to the write request, updating a first FTL table entry by using the first physical address, unlocking the first FTL table entry, writing data into the first physical address, and updating the current write position; and

the read request processing module is used for responding to the received read request, accessing a first FTL table entry corresponding to the read request and acquiring a first physical address recorded by the first FTL table entry; if the current write location is behind the first physical address, processing of the first read request is suspended until the current write location is ahead of the first physical address.

10. An information processing apparatus comprising a memory, a processor and a program stored on the memory and executable on the processor, characterized in that the processor implements the method according to one of claims 1 to 5 when executing the program.