CN114245614A - Through hole electrical performance optimization design method and device, PCB and equipment - Google Patents
Through hole electrical performance optimization design method and device, PCB and equipment Download PDFInfo
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- CN114245614A CN114245614A CN202111553966.4A CN202111553966A CN114245614A CN 114245614 A CN114245614 A CN 114245614A CN 202111553966 A CN202111553966 A CN 202111553966A CN 114245614 A CN114245614 A CN 114245614A
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- 238000013461 design Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000005457 optimization Methods 0.000 title abstract description 10
- 238000007747 plating Methods 0.000 claims abstract description 121
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 115
- 229910052802 copper Inorganic materials 0.000 claims abstract description 115
- 239000010949 copper Substances 0.000 claims abstract description 115
- 239000011148 porous material Substances 0.000 claims abstract description 37
- 238000005553 drilling Methods 0.000 claims abstract description 24
- 238000004891 communication Methods 0.000 claims description 5
- 150000003071 polychlorinated biphenyls Chemical class 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 7
- 238000003780 insertion Methods 0.000 description 14
- 230000037431 insertion Effects 0.000 description 14
- 238000004088 simulation Methods 0.000 description 9
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
Abstract
The invention provides a through hole electrical performance optimization design method, which comprises the following steps: under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the through hole is used for improving the electrical performance of the through hole in the PCB; the invention also provides a through hole electrical performance optimization design device, a PCB and equipment, wherein the copper plating ratio is 1-pore forming aperture/drilling aperture, the three electrical performance indexes of IL, RL and TDR of a through hole (through hole) are greatly improved, the design difficulty of a single plate is not increased, the processing difficulty of the single plate is not increased, and the electrical performance of the through hole in the PCB is effectively improved.
Description
Technical Field
The invention relates to the field of PCB system design, in particular to a method and a device for optimally designing the electrical performance of a through hole, a PCB and equipment.
Background
In the design of high-speed and high-density single boards, the design of high-speed signals is the most important. Among them, the treatment of the high-speed through-hole is important. Signal integrity engineers are constantly striving to design high-speed vias for better electrical performance. As shown in fig. 1, the high speed via is composed. The high-speed through hole comprises a drilling hole, a pore-forming hole, a bonding pad and an anti-bonding pad. And copper plating is carried out between the drilling and the pore-forming to endow the through hole with electrical properties.
In high speed single board via designs, existing via designs typically employ 8mil (via hole size) -10mil (via hole size) -18mil (pad diameter) -28mil (anti-pad diameter) as the carrier for signal interconnects. For such a via, its copper plating ratio is generally 1 to 8/10 ═ 0.2.
However, in the conventional high speed via design, when the copper plating ratio is 0.2, the electrical performance of the via, such as IL (Insertion Loss), RL (return Loss ), and TDR (Time Domain impedance) does not reach a better performance, which is not favorable for further optimization of the electrical performance of the via in a PCB (Printed circuit board or Printed circuit board).
Disclosure of Invention
The invention aims to solve the problems in the prior art, innovatively provides a method, a device, a PCB and equipment for optimally designing the electrical performance of a through hole, effectively solves the problem of low electrical performance of the through hole caused by the prior art, and effectively improves the electrical performance of the through hole of the PCB.
The invention provides a method for optimally designing the electrical performance of a through hole, which comprises the following steps:
under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the through hole is used for improving the electrical performance of the through hole in the PCB; wherein the copper plating ratio is 1-pore forming pore diameter/pore drilling pore diameter.
Optionally, increasing the copper plating ratio of the through hole is specifically:
keeping the bore diameter of the drilled hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole; or keeping the pore diameter of the formed hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the pore diameter of the drilled hole.
Further, after the copper plating ratio of the through hole is increased, the copper plating ratio of the through hole ranges from 0.3 to 0.4.
Further, after the increase, the copper plating ratio of the through-hole was 0.4.
The invention provides a through hole electrical performance optimization design device in a second aspect, which comprises:
the adjusting module is used for increasing the copper plating ratio of the through hole under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, and is used for improving the electrical performance of the through hole in the PCB; wherein the copper plating ratio is 1-pore forming pore diameter/pore drilling pore diameter.
Optionally, increasing the copper plating ratio of the through hole is specifically:
keeping the bore diameter of the drilled hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole; or keeping the pore diameter of the formed hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the pore diameter of the drilled hole.
Further, after the copper plating ratio of the through hole is increased, the copper plating ratio of the through hole ranges from 0.3 to 0.4.
The third aspect of the present invention provides a PCB formed on the basis of the method for optimizing and designing electrical properties of a through hole according to the first aspect of the present invention.
Optionally, the copper plating ratio of the through-hole ranges from 0.3 to 0.4.
A fourth aspect of the invention provides a communication device comprising a plurality of PCBs according to the third aspect of the invention.
The technical scheme adopted by the invention comprises the following technical effects:
1. according to the technical scheme, under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the electrical performance of the through hole in the PCB is effectively improved.
2. The technical scheme of the invention keeps the bore diameter of the drilled hole unchanged, increases the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole, provides a new through hole copper plating mode, greatly improves the three electrical performance indexes of IL, RL and TDR of the through hole (through hole), and increases a realization thought for the area which is difficult to improve the TDR impedance of the through hole without increasing the design difficulty of a single plate or increasing the processing difficulty of the single plate by the new copper plating mode.
3. After the technical scheme is added, the copper plating ratio of the through hole ranges from 0.3 to 0.4, preferably, the copper plating ratio of the through hole is 0.4, and the electrical performance of the through hole in the PCB is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without any creative effort.
FIG. 1 is a schematic diagram of a through hole (via) in the prior art;
FIG. 2 is a graph showing simulated curves for IL or RL with a 6mil via hole size and a copper plating ratio of 0.2 in a first embodiment of the present invention;
FIG. 3 is a graph showing simulated curves for IL or RL with a copper plating ratio of 0.2 for a via opening size of 8mil in a first embodiment of the present invention;
FIG. 4 is a graph showing simulated curves for IL or RL with a 6mil via opening size and a copper plating ratio of 0.4 in a first embodiment of the present invention;
FIG. 5 is a schematic diagram showing a simulated TDR curve at a copper plating ratio of 0.2 for a 6mil via hole diameter in example one of the embodiments of the present invention;
FIG. 6 is a graph showing a simulated TDR at a copper plating ratio of 0.2 for a hole forming aperture of 8 mils in the first example of the embodiment of the present invention;
FIG. 7 is a graph showing a simulated TDR at a copper plating ratio of 0.4 for a 6mil via opening size in accordance with one embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
Example one
The invention provides a through hole electrical performance optimization design method, which comprises the following steps:
under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the through hole is used for improving the electrical performance of the through hole in the PCB; wherein the copper plating ratio is 1-pore forming pore diameter/pore drilling pore diameter.
Wherein, the copper plating ratio for increasing the through hole is as follows:
keeping the bore diameter of the drilled hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole; or keeping the pore diameter of the formed hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the pore diameter of the drilled hole. After the copper plating ratio of the through hole is increased, the copper plating ratio of the through hole ranges from 0.3 to 0.4. Preferably, the copper plating ratio of the through-hole after the increase is 0.4.
For example, in high speed single board designs, vias of 8mil (via hole size) -10mil (via hole size) -18mil (pad diameter) -28mil (anti-pad diameter) are commonly used as carriers for signal interconnects. For such vias, the copper Plating Ratio (Plating Ratio) is typically 1-8/10-0.2; after the through holes are subjected to secondary plating (the thickness of a copper plating layer is increased between Hole forming and Hole drilling), a new copper plating ratio is obtained, namely, the Hole Diameter (Drill Hole Diameter) of the Hole drilling is ensured to be unchanged by 10 mils, the copper plating ratio is changed to be 0.3-0.4, namely, the corresponding Hole forming Hole Diameter (Finish Hole Diameter) is changed to be 10 x (1-0.3) to 7 mils, or 10 x (1-0.4) to 6 mils, the Diameter of the bonding pad is constant, and the Diameter of the anti-bonding pad is unchanged; or the hole diameter of the formed hole can be kept unchanged, and the hole diameter of the drilled hole is adjusted to ensure that the copper plating ratio is 0.3-0.4, wherein the invention is not limited in the process.
No matter the through hole is 8mil (pore-forming aperture) -10mil (drilling aperture) or the through hole is 6mil (pore-forming aperture) -8mil (drilling aperture), the relationship that the difference between the pore-forming aperture and the drilling aperture is 2mil is basically unchanged, the copper plating ratio is increased to be within the range of 0.3-0.4 from 0.2, and the pore-forming aperture of 6mil-7mil can also be obtained by the drilling aperture of 10 mil. The simulation can be used for obviously improving the electrical performance.
Further, the following description will be given taking an example in which the copper plating ratio is 0.4. The copper plating ratio is 0.2 (the hole drilling diameter is 7.5mil) for the hole forming diameter of 6mil respectively; the aperture of the hole is 8mil, the copper plating ratio is 0.2 (the aperture of the drilled hole is 10 mil); and the present example was compared for simulation using a copper plating ratio of 0.4 (6mil via hole diameter, 10mil via hole diameter).
As shown in FIG. 2, FIG. 2 is a simulation plot of 6mil via hole diameter, copper plating ratio of 0.2 (via hole diameter of 7.5mil), frequency (Freq) in GHZ on the abscissa, insertion loss IL or return loss RL on the ordinate, insertion loss IL on the upper side, return loss RL on the lower side, and dB in all units. The relevant parameters are shown in the following table.
| name | X (frequency, GHZ) | Y(dB) |
| m1 (Return loss RL) | 8.0000 | -13.5722 |
| m2 (insertion loss IL) | 8.0000 | -0.2860 |
| m3 (Return loss RL) | 16.0000 | -8.4302 |
| m4 (insertion loss IL) | 16.0000 | -0.8835 |
As shown in FIG. 3, FIG. 3 is a simulation plot for a 8mil via hole diameter and copper plating ratio of 0.2 (via hole diameter of 10mil), with frequency (Freq) on the abscissa, in GHZ, insertion loss IL or return loss RL on the ordinate, insertion loss IL on the upper side, return loss RL on the lower side, in dB. The relevant parameters are shown in the following table.
| name | X (frequency, GHZ) | Y(dB) |
| m1 (Return loss RL) | 8.0000 | -14.2426 |
| m2 (insertion loss IL) | 8.0000 | -0.2563 |
| m3 (Return loss RL) | 16.0000 | -9.1102 |
| m4 (insertion loss IL) | 16.0000 | -0.7784 |
As shown in FIG. 4, FIG. 4 is a simulated curve for a 6mil via hole diameter, copper plating ratio of 0.4 (10 mil via hole diameter), frequency (Freq) in GHZ on the abscissa, insertion loss IL or return loss RL on the ordinate, insertion loss IL on the upper side and return loss RL on the lower side, all in dB. The relevant parameters are shown in the following table.
| name | X (frequency, GHZ) | Y(dB) |
| m1 (Return loss RL) | 8.0000 | -17.7566 |
| m2 (insertion loss IL) | 8.0000 | -0.1394 |
| m3 (Return loss RL) | 16.0000 | -9.9847 |
| m4 (insertion loss IL) | 16.0000 | -0.6131 |
As shown in FIG. 5, FIG. 5 is a simulation plot of a 6mil via hole diameter with a copper plating ratio of 0.2 (via hole diameter of 7.5mil), with time (time) on the abscissa in ns and time domain impedance TDR on the ordinate in Ohm. The relevant parameters are shown in the following table.
| name | X(time，ns) | Y(Ohm) |
| m1 (frequency 8GHZ) | 0.0300 | 74.0676 |
| m2 (frequency 16GHZ) | 0.0600 | 74.3792 |
As shown in FIG. 6, FIG. 6 is a simulation plot of copper plating ratio at 0.2 (10 mil via hole diameter) for a hole having a hole diameter of 8mil, with time (time) in ps on the abscissa and time domain impedance TDR in Ohm on the ordinate. The relevant parameters are shown in the following table.
| name | X(time，ps) | Y(Ohm) |
| m1 (frequency 8GHZ) | 30 | 74.1567 |
| m2 (frequency 16GHZ) | 60 | 75.0189 |
As shown in FIG. 7, FIG. 7 is a simulated curve at a 6mil via hole diameter and a copper plating ratio of 0.4 (via hole diameter of 10 mils), with time (time) on the abscissa and time domain impedance TDR on the ordinate in ohms. The relevant parameters are shown in the following table.
By combining the above tables, the following table can be obtained.
According to the simulation result table, compared with the conventional design, the IL insertion loss index is improved by 0.12-0.27 dB; the RL return loss index is improved by 0.87-4.2 dB; TDR has a lift of about 5 ohm.
According to the technical scheme, under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the electrical performance of the through hole in the PCB is effectively improved.
The technical scheme of the invention keeps the bore diameter of the drilled hole unchanged, increases the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole, provides a new through hole copper plating mode, greatly improves the three electrical performance indexes of IL, RL and TDR of the through hole (through hole), and increases a realization thought for the area which is difficult to improve the TDR impedance of the through hole without increasing the design difficulty of a single plate or increasing the processing difficulty of the single plate by the new copper plating mode.
After the technical scheme is added, the copper plating ratio of the through hole ranges from 0.3 to 0.4, preferably, the copper plating ratio of the through hole is 0.4, and the electrical performance of the through hole in the PCB is further improved.
Example two
The technical scheme of the invention also provides a through hole electrical performance optimization design device, which comprises:
the adjusting module is used for increasing the copper plating ratio of the through hole under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, and is used for improving the electrical performance of the through hole in the PCB; wherein the copper plating ratio is 1-pore forming pore diameter/pore drilling pore diameter.
Wherein, the copper plating ratio for increasing the through hole is as follows:
keeping the bore diameter of the drilled hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole; or keeping the pore diameter of the formed hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the pore diameter of the drilled hole. After the copper plating ratio of the through hole is increased, the copper plating ratio of the through hole ranges from 0.3 to 0.4. Preferably, the copper plating ratio of the through-hole after the increase is 0.4.
For example, in high speed single board designs, vias of 8mil (via hole size) -10mil (via hole size) -18mil (pad diameter) -28mil (anti-pad diameter) are commonly used as carriers for signal interconnects. For such vias, the copper Plating Ratio (Plating Ratio) is typically 1-8/10-0.2; after the through holes are subjected to additional plating (between the formed holes and the drilled holes), a new copper plating ratio is obtained, namely, the Hole Diameter (Drill Hole Diameter) of the drilled holes is ensured to be unchanged by 10 mils, the copper plating ratio is changed to 0.3-0.4, namely, the corresponding Hole forming Hole Diameter (Finish Hole Diameter) is changed to 10 (1-0.3) to 7 mils, or 10 (1-0.4) to 6 mils, the Diameter of the bonding pad and the Diameter of the anti-bonding pad are unchanged; or the hole diameter of the formed hole can be kept unchanged, and the hole diameter of the drilled hole is adjusted to ensure that the copper plating ratio is 0.3-0.4, wherein the invention is not limited in the process.
No matter the through hole is 8mil (pore-forming aperture) -10mil (drilling aperture) or the through hole is 6mil (pore-forming aperture) -8mil (drilling aperture), the relationship that the difference between the pore-forming aperture and the drilling aperture is 2mil is basically unchanged, the copper plating ratio is increased to be within the range of 0.3-0.4 from 0.2, and the pore-forming aperture of 6mil-7mil can also be obtained by the drilling aperture of 10 mil. The simulation can be used for obviously improving the electrical performance.
According to the technical scheme, under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the electrical performance of the through hole in the PCB is effectively improved.
The technical scheme of the invention keeps the bore diameter of the drilled hole unchanged, increases the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole, provides a new through hole copper plating mode, greatly improves the three electrical performance indexes of IL, RL and TDR of the through hole (through hole), and increases a realization thought for the area which is difficult to improve the TDR impedance of the through hole without increasing the design difficulty of a single plate or increasing the processing difficulty of the single plate by the new copper plating mode.
After the technical scheme is added, the copper plating ratio of the through hole ranges from 0.3 to 0.4, preferably, the copper plating ratio of the through hole is 0.4, and the electrical performance of the through hole in the PCB is further improved.
EXAMPLE III
The technical scheme of the invention also provides a PCB which is formed on the basis of adopting the through hole electrical performance optimization design method in the first embodiment.
The copper plating ratio of the through holes in the PCB board ranges from 0.3 to 0.4. Preferably, the copper plating ratio of the through-hole is 0.4.
For example, in high speed PCB board designs, vias of 8mil (via hole diameter) -10mil (via hole diameter) -18mil (pad diameter) -28mil (anti-pad diameter) are commonly used as carriers for signal interconnects. For such vias, the copper Plating Ratio (Plating Ratio) is typically 1-8/10-0.2; after the through holes are subjected to additional plating (between the formed holes and the drilled holes), a new copper plating ratio is obtained, namely, the Hole Diameter (Drill Hole Diameter) of the drilled holes is ensured to be unchanged by 10 mils, the copper plating ratio is changed to 0.3-0.4, namely, the corresponding Hole forming Hole Diameter (Finish Hole Diameter) is changed to 10 (1-0.3) to 7 mils, or 10 (1-0.4) to 6 mils, the Diameter of the bonding pad and the Diameter of the anti-bonding pad are unchanged; or the hole diameter of the formed hole can be kept unchanged, and the hole diameter of the drilled hole is adjusted to ensure that the copper plating ratio is 0.3-0.4, wherein the invention is not limited in the process.
No matter the through hole is 8mil (pore-forming aperture) -10mil (drilling aperture) or the through hole is 6mil (pore-forming aperture) -8mil (drilling aperture), the relationship that the difference between the pore-forming aperture and the drilling aperture is 2mil is basically unchanged, the copper plating ratio is increased to be within the range of 0.3-0.4 from 0.2, and the pore-forming aperture of 6mil-7mil can also be obtained by the drilling aperture of 10 mil. The simulation can be used for obviously improving the electrical performance.
According to the technical scheme, under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the electrical performance of the through hole in the PCB is effectively improved.
The technical scheme of the invention keeps the bore diameter of the drilled hole unchanged, increases the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole, provides a new through hole copper plating mode, greatly improves the three electrical performance indexes of IL, RL and TDR of the through hole (through hole), and increases a realization thought for the area which is difficult to improve the TDR impedance of the through hole without increasing the design difficulty of a single plate or increasing the processing difficulty of the single plate by the new copper plating mode.
After the technical scheme is added, the copper plating ratio of the through hole ranges from 0.3 to 0.4, preferably, the copper plating ratio of the through hole is 0.4, and the electrical performance of the through hole in the PCB is further improved.
Example four
The technical scheme of the invention also provides communication equipment which comprises the PCB in the third embodiment.
According to the communication equipment in the technical scheme, by applying the PCB in the third embodiment, the copper plating ratio of the through hole can be increased under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, and the electrical performance of the through hole in the PCB is effectively improved.
According to the communication equipment in the technical scheme, the hole diameter of the drilled hole is kept unchanged, the copper plating ratio of the through hole is increased by adjusting the size of the hole-forming hole diameter, a novel through hole copper plating mode is provided, the three electrical performance indexes of IL, RL and TDR of the through hole (through hole) are greatly improved, the novel copper plating mode does not increase the design difficulty of the single board, does not increase the processing difficulty of the single board, even expands the thought and direction of TDR impedance optimization of the through hole, and increases a realization thought for the area which is difficult to improve the TDR impedance of the through hole.
According to the technical scheme, by applying the PCB in the third embodiment, the copper plating ratio of the through holes in the PCB ranges from 0.3 to 0.4, preferably, the copper plating ratio of the through holes is 0.4, and the electrical performance of the through holes in the PCB is further improved.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (10)
1. A method for optimally designing the electrical performance of a through hole is characterized by comprising the following steps:
under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, the copper plating ratio of the through hole is increased, and the through hole is used for improving the electrical performance of the through hole in the PCB; wherein the copper plating ratio is 1-pore forming pore diameter/pore drilling pore diameter.
2. The method for optimizing the electrical performance of a through hole according to claim 1, wherein the step of increasing the copper plating ratio of the through hole comprises the following steps:
keeping the bore diameter of the drilled hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole; or keeping the pore diameter of the formed hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the pore diameter of the drilled hole.
3. The method as claimed in claim 2, wherein the copper plating ratio of the through hole is in the range of 0.3-0.4.
4. The method as claimed in claim 3, wherein the copper plating ratio of the through hole is 0.4 after the step of increasing.
5. A through hole electrical performance optimal design device is characterized by comprising:
the adjusting module is used for increasing the copper plating ratio of the through hole under the condition that the diameter of the bonding pad and the diameter of the anti-bonding pad are not changed, and is used for improving the electrical performance of the through hole in the PCB; wherein the copper plating ratio is 1-pore forming pore diameter/pore drilling pore diameter.
6. The device for optimizing the electrical performance of the through hole according to claim 5, wherein the increase of the copper plating ratio of the through hole is specifically:
keeping the bore diameter of the drilled hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the bore diameter of the drilled hole; or keeping the pore diameter of the formed hole unchanged, and increasing the copper plating ratio of the through hole by adjusting the size of the pore diameter of the drilled hole.
7. The device of claim 6, wherein the copper plating ratio of the through hole ranges from 0.3 to 0.4 after the increase.
8. A PCB formed by the method for optimizing the electrical performance of the through hole according to any one of claims 1 to 4.
9. The PCB of claim 8, wherein the through-hole has a copper plating ratio ranging from 0.3 to 0.4.
10. A communication device comprising a plurality of PCBs as claimed in claim 8 or 9.
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| CN109548295A (en) * | 2018-12-27 | 2019-03-29 | 郑州云海信息技术有限公司 | A kind of sizing method and system for anti-pad and via hole back drill technology |
| CN109618500A (en) * | 2018-12-27 | 2019-04-12 | 广州兴森快捷电路科技有限公司 | Reparation detection method for semiconductor test board |
| CN112566376A (en) * | 2020-11-27 | 2021-03-26 | 惠州市特创电子科技股份有限公司 | Deep etching hole control process of circuit board and circuit board |
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