CN114245046B - Circulating ADC for CMOS image sensor and circulating method thereof - Google Patents
Circulating ADC for CMOS image sensor and circulating method thereof Download PDFInfo
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- CN114245046B CN114245046B CN202111256487.6A CN202111256487A CN114245046B CN 114245046 B CN114245046 B CN 114245046B CN 202111256487 A CN202111256487 A CN 202111256487A CN 114245046 B CN114245046 B CN 114245046B
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- 239000003990 capacitor Substances 0.000 claims abstract description 352
- 238000005070 sampling Methods 0.000 claims abstract description 22
- 125000004122 cyclic group Chemical group 0.000 claims description 14
- 230000008859 change Effects 0.000 claims description 3
- 238000007667 floating Methods 0.000 claims description 3
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- 238000006243 chemical reaction Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000012935 Averaging Methods 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/667—Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
The embodiment of the application discloses a circulating ADC for a CMOS image sensor and a circulating method thereof, wherein the ADC comprises: the transconductance amplifier, the chopper, the capacitors with the same capacitance values and the control switches; the chopper and the control switch are switched to enable the ADC to have a first working mode, a second working mode, a third working mode and a fourth working mode which are sequentially and circularly executed; the capacitors in the first group of capacitors in the first working mode and the second working mode are respectively connected in series to the input end and the output end, the polarities of the capacitors in the first group of capacitors in the first working mode and the second working mode are opposite, and different capacitors in the second group of capacitors in the second working mode are respectively subjected to voltage sampling; the first group of capacitors and the second group of capacitors in the first working mode are subjected to position exchange to obtain a third working mode; the first set of capacitors and the second set of capacitors in the second mode of operation are position interchanged to obtain a fourth mode of operation. The embodiment solves the problems of capacitor mismatch and offset voltage of the transconductance amplifier.
Description
Technical Field
Embodiments of the present disclosure relate to ADC design, and more particularly, to a circulating ADC for CMOS image sensor and a circulating method thereof.
Background
CMOS (Complementary Metal Oxide Semiconductor complementary metal oxide semiconductor) image sensors typically employ a column-wise parallel readout architecture, with the voltage values of the pixels being read column-wise, with each column sharing an ADC (analog-to-digital converter, or analog-to-digital converter). The CYCLIC (CYCLIC) ADC has the characteristics of low input capacitance, small area, simple structure, etc., so that it is very suitable for CMOS image sensors. However, the capacitor mismatch and offset voltage of the amplifier of the current cyclic ADC limit the conversion accuracy of CYCLIC ADC.
Disclosure of Invention
The embodiment of the application provides a circulating ADC for a CMOS image sensor and a circulating method thereof, which can solve the problems of capacitance mismatch and offset voltage of a transconductance amplifier.
Embodiments of the present application provide a cyclic ADC for CMOS image sensors, which may include: the transconductance amplifier, the chopper, the capacitors with the same capacitance values and the control switches;
the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor; the input terminal comprises: a forward input and a reverse input, the output comprising: a forward output and a reverse output;
the control switch is arranged to control the access mode of the transconductance amplifier and the capacitor in each working mode;
wherein the chopper and the plurality of control switches are switched such that the cyclic analog-to-digital converter ADC has a plurality of said modes of operation; the plurality of operation modes include: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the plurality of capacitors having the same capacitance value include: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are connected in series to the input end and the output end respectively; the at least two capacitors are connected with the input end and the DAC output end, and the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the first working mode is opposite to the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; to eliminate offset voltages by charge combination on the second set of capacitors.
In an exemplary embodiment of the present application, the plurality of operation modes may further include: an initial sampling mode;
in the initial sampling mode, the first group of capacitors are used as sampling capacitors for signal acquisition to acquire initial acquisition voltage; and the chopper and the transconductance amplifier, and the chopper and the capacitor are in an off state, and the capacitors in the second group of capacitors are in a floating state.
In an exemplary embodiment of the present application, the chopper may include a first chopper and a second chopper;
wherein the first chopper and the second chopper are both used for connecting the first group of capacitors or the second group of capacitors with the forward input end and the reverse input end;
the DAC output terminal comprises: a first DAC output and a second DAC output;
the first set of capacitances may include: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the second set of capacitances includes: a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor;
the first capacitor, the second capacitor, the fifth capacitor and the sixth capacitor are used for being connected with an input end or an output end of the first side of the transconductance amplifier;
the third capacitor, the fourth capacitor, the seventh capacitor and the eighth capacitor are used for being connected with an input end or an output end of the second side of the transconductance amplifier.
In an exemplary embodiment of the present application, the first operation mode may include:
the first capacitor is connected in series between the first DAC output end and the reverse input end;
the second capacitor is connected in series between the reverse input end and the forward output end;
the first end of the fifth capacitor is connected with the positive output end, and the second end is applied with a common mode level;
the sixth capacitor is suspended;
the third capacitor is connected in series between the second DAC output end and the positive input end;
the fourth capacitor is connected in series between the positive input end and the negative output end;
the first end of the seventh capacitor is connected with the reverse output end, and the second end is applied with the common mode level;
the eighth capacitor is suspended.
In an exemplary embodiment of the present application, the second operation mode may include:
the second capacitor is connected in series between the first DAC output end and the positive input end;
the first capacitor is connected in series between the positive input end and the negative output end;
the first end of the sixth capacitor is connected with the reverse output end, and the second end is applied with a common mode level;
the fifth capacitor is suspended;
the fourth capacitor is connected in series between the second DAC output end and the reverse input end;
the third capacitor is connected in series between the reverse input end and the forward output end;
the first end of the eighth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the eighth capacitor;
the seventh capacitor is suspended.
In an exemplary embodiment of the present application, the third operation mode may include:
the fifth capacitor is connected in series between the first DAC output end and the reverse input end;
the sixth capacitor is connected in series between the reverse input end and the forward output end;
the first end of the first capacitor is connected with the positive output end, and the second end is applied with a common mode level;
the second capacitor is suspended;
the seventh capacitor is connected in series between the second DAC output end and the positive input end;
the eighth capacitor is connected in series between the positive input end and the negative output end;
the first end of the third capacitor is connected with the reverse output end, and the second end of the third capacitor is applied with the common mode level;
the fourth capacitor is suspended.
In an exemplary embodiment of the present application, the fourth operation mode may include:
the sixth capacitor is connected in series between the first DAC output end and the positive input end;
the fifth capacitor is connected in series between the positive input end and the negative output end;
the first end of the second capacitor is connected with the reverse output end, and the second end is applied with a common mode level;
the first capacitor is suspended;
the eighth capacitor is connected in series between the second DAC output end and the reverse input end;
the seventh capacitor is connected in series between the reverse input end and the forward output end;
the first end of the fourth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the fourth capacitor;
the third capacitor is suspended.
In an exemplary embodiment of the present application, the initial sampling pattern may include:
the first capacitor and the second capacitor are connected in parallel;
the first ends of the first capacitor and the second capacitor are connected with a forward input signal Vip, and the second ends are applied with a common mode level;
the third capacitor and the fourth capacitor are connected in parallel;
the first ends of the third capacitor and the fourth capacitor are connected with an inverted input signal Vin, and the second ends are applied with the common mode level.
The embodiment of the application also provides a circulating ADC circulating method for the CMOS image sensor, which can be applied to the circulating ADC for the CMOS image sensor; the method may include:
sequentially and circularly executing a plurality of preset working modes; and in the multiple working modes, different capacitors in the circulating ADC sample output voltages of the transconductance amplifier, and when the modes change, the connection mode of the capacitors and the polarity of the connected ends are changed, so that charges on the capacitors are combined to eliminate offset voltages.
In an exemplary embodiment of the present application, the plurality of operation modes may include: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the capacitance may include: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected in series to the input end and the output end of the transconductance amplifier in the circulating ADC; the at least two capacitors are connected with the input end and the DAC output end, and the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the first working mode is opposite to the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; to eliminate offset voltages by charge combination on the second set of capacitors.
Compared with the related art, the embodiment of the application can comprise the following steps: the transconductance amplifier, the chopper, the capacitors with the same capacitance values and the control switches; the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor; the input terminal comprises: a forward input and a reverse input, the output comprising: a forward output and a reverse output; the control switch is arranged to control the access mode of the transconductance amplifier and the capacitor in each working mode; the chopper and the switch states of the control switches enable the circulating analog-to-digital converter ADC to have multiple working modes; the plurality of modes of operation include: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the plurality of capacitors having the same capacitance value include: a first set of capacitors and a second set of capacitors; in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are connected in series to the input end and the output end respectively; the at least two capacitors are connected with the input end and the DAC output end, and the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the first working mode is opposite to the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the second working mode; in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors; the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; to eliminate offset voltages by charge combination on the second set of capacitors. By the scheme of the embodiment, the problems of capacitance mismatch and offset voltage of the transconductance amplifier are solved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a block diagram of a cyclic ADC according to an embodiment of the present application;
FIG. 2 is a schematic circuit diagram of a first operation mode according to an embodiment of the present application;
FIG. 3 is a circuit schematic of a second mode of operation according to an embodiment of the present application;
FIG. 4 is a circuit schematic of a third mode of operation according to an embodiment of the present application;
FIG. 5 is a fourth operational mode circuit schematic of an embodiment of the present application;
FIG. 6 is a schematic diagram of an initial sampling mode circuit according to an embodiment of the present application;
FIG. 7 is a block diagram of a CMOS image sensor system according to an embodiment of the present application;
fig. 8 is a flowchart of a cyclic ADC cyclic method according to an embodiment of the application.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Embodiments of the present application provide a cyclic ADC for a CMOS image sensor, as shown in fig. 1, may include: a transconductance amplifier A, a chopper, a plurality of capacitors C with the same capacitance value and a plurality of control switches B;
the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor C; the input terminal comprises: a forward input and a reverse input, the output comprising: a forward output and a reverse output;
the control switch B is arranged to control the access mode of the transconductance amplifier and the capacitor C in each working mode;
wherein the chopper and the plurality of control switches are switched such that the cyclic analog-to-digital converter ADC has a plurality of said modes of operation; as shown in fig. 2, 3, 4, 5, the plurality of said modes of operation include: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the plurality of capacitors having the same capacitance value include: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are connected in series to the input end and the output end respectively; the at least two capacitors are connected with the input end and the DAC output end, and the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the first working mode is opposite to the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; to eliminate offset voltages by charge combination on the second set of capacitors.
In an exemplary embodiment of the present application, all capacitances take the same magnitude of capacitance value.
In an exemplary embodiment of the present application, the embodiment of the present application may employ a 1.5bit per cycle structure. As shown in fig. 6, the input signal is first sampled and quantized to a 1.5bit digital output, and then may be cyclically operated in the order of the first operation mode (fig. 2), the second operation mode (fig. 3), the third operation mode (fig. 4), and the fourth operation mode (fig. 5). Here, the first operation mode (fig. 2) and the second operation mode (fig. 3) may be defined, or the third operation mode (fig. 4) and the fourth operation mode (fig. 5) may be defined as one conversion period, each conversion period may generate a digital output of 1.5 bits, and 14 conversion periods and one sampling period may be used (fig. 6) to obtain an overall 16-bit analog-to-digital conversion result. In one conversion period, the elimination of the capacitance mismatch and the elimination of the offset voltage of the transconductance amplifier are realized through the position of the exchange capacitance and the positive and negative polarities of the transconductance amplifier, wherein the former can be called as a capacitance mismatch averaging technology, and the latter can be called as a chopping extinction modulation technology.
In an exemplary embodiment of the present application, the chopper may include a first chopper1 and a second chopper2;
wherein the first chopper1 and the second chopper2 are each configured to connect the first set of capacitors or the second set of capacitors to the forward input terminal and the reverse input terminal.
In an exemplary embodiment of the present application, four switches may be provided in the chopper (chopper) depending on whether lateral conduction or cross conduction is selected at different operating phases.
In an exemplary embodiment of the present application, the first set of capacitances may include: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the second set of capacitances includes: a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8;
the first capacitor C1, the second capacitor C2, the fifth capacitor C5 and the sixth capacitor C6 are used for connecting an input end or an output end of the first side of the transconductance amplifier a;
the third capacitor C3, the fourth capacitor C4, the seventh capacitor C7 and the eighth capacitor C8 are connected to an input terminal or an output terminal of the second side of the transconductance amplifier a.
In an exemplary embodiment of the present application, as shown in fig. 6, the plurality of operation modes may further include: an initial sampling mode;
in the initial sampling mode, the first group of capacitors are used as sampling capacitors for signal acquisition to acquire initial acquisition voltage; and the chopper and the transconductance amplifier, and the chopper and the capacitor are in an off state, and the capacitors in the second group of capacitors are in a floating state.
In an exemplary embodiment of the present application, the DAC output may include: a first DAC output and a second DAC output.
In an exemplary embodiment of the present application, the initial sampling mode may include:
the first capacitor C1 and the second capacitor C2 are connected in parallel;
the first ends of the first capacitor C1 and the second capacitor C2 are connected to the positive input signal Vip as shown in fig. 6, and the second ends are applied with a common mode level VCM;
the third capacitor C3 and the fourth capacitor C4 are connected in parallel;
the third capacitor C3 and the fourth capacitor C4 have a first terminal connected to the inverted input signal Vin as shown in fig. 6 and a second terminal to which the common mode level VCM is applied.
In an exemplary embodiment of the present application, as shown in fig. 2, the first operation mode may include:
the first capacitor C1 is connected in series between the output end of the first DAC (digital-to-analog converter) and the reverse input end;
the second capacitor C2 is connected in series between the reverse input end and the forward output end;
the first end of the fifth capacitor C5 is connected with the positive output end, and the common mode level is applied to the second end of the fifth capacitor C5;
the sixth capacitor C6 is suspended;
the third capacitor C3 is connected in series between the second DAC output end and the positive input end;
the fourth capacitor C4 is connected in series between the positive input end and the negative output end;
the first end of the seventh capacitor C7 is connected with the reverse output end, and the common mode level is applied to the second end;
the eighth capacitor C8 is suspended.
Wherein VDACp (may include VDACp1, VDACp 2) and VDACn (may include VDACn1, VDACn 2) may access VRP, VRN, or VCM depending on the value of the comparator in the analog-to-digital converter; VRP represents a reference voltage high level; VRN represents a reference voltage low level; VCM represents the common mode level.
In an exemplary embodiment of the present application, as shown in fig. 3, the second operation mode may include:
the second capacitor C2 is connected in series between the first DAC output end and the positive input end;
the first capacitor C1 is connected in series between the positive input end and the negative output end;
the first end of the sixth capacitor C6 is connected with the reverse output end, and the common mode level is applied to the second end;
the fifth capacitor C5 is suspended;
the fourth capacitor C4 is connected in series between the second DAC output end and the reverse input end;
the third capacitor C3 is connected in series between the reverse input end and the forward output end;
the first end of the eighth capacitor C8 is connected with the positive output end, and the common mode level is applied to the second end of the eighth capacitor C8;
the seventh capacitor C7 is suspended.
In an exemplary embodiment of the present application, as shown in fig. 4, the third operation mode may include:
the fifth capacitor C5 is connected in series between the first DAC output end and the reverse input end;
the sixth capacitor C6 is connected in series between the reverse input end and the forward output end;
the first end of the first capacitor C1 is connected with the positive output end, and the common mode level is applied to the second end;
the second capacitor C2 is suspended;
the seventh capacitor C7 is connected in series between the second DAC output end and the positive input end;
the eighth capacitor C8 is connected in series between the positive input end and the negative output end;
the first end of the third capacitor C3 is connected with the reverse output end, and the common mode level is applied to the second end;
the fourth capacitor C4 is suspended.
In an exemplary embodiment of the present application, as shown in fig. 5, the fourth operation mode may include:
the sixth capacitor C6 is connected in series between the first DAC output end and the positive input end;
the fifth capacitor C5 is connected in series between the positive input end and the negative output end;
the first end of the second capacitor C2 is connected with the reverse output end, and the common mode level is applied to the second end;
the first capacitor C1 is suspended;
the eighth capacitor C8 is connected in series between the second DAC output end and the reverse input end;
the seventh capacitor C7 is connected in series between the reverse input end and the forward output end;
the first end of the fourth capacitor C4 is connected with the positive output end, and the common mode level is applied to the second end of the fourth capacitor C4;
the third capacitor C3 is suspended.
In the exemplary embodiment of the present application, fig. 2 and 3 may be taken as an example for illustration in one conversion process, in order to simplify the single-ended analysis, by exchanging the positions of C1 and C2 and the polarities of the transconductance amplifier, two residual voltages are sampled by C5 and C6, respectively, and in the next conversion process, the charges on C5 and C6 are combined together, so that the capacitance mismatch of C1 and C2 and the offset voltage of the transconductance amplifier are eliminated.
In an exemplary embodiment of the present application, the above-described cyclic ADC may be applied to a CMOS image sensor as shown in fig. 7. The Pixel Array is a detector part of the embodiment of the application, and the analog-to-digital converter ADC is responsible for converting a signal of the PD into a digital signal and sequentially outputs the digital signal through an algorism & Timing Control module and a FIFO (first in first out) module and then through an LVDS Driver (low voltage differential signaling) port. Global Timing Control (global time control) module is connected with Vertical Scanning Block (vertical scan block) module, generates all timing control signals, and Vertical Scanning Block module is responsible for addressing and resetting PD. The other end of the Global Timing Control module is connected with an I2C Port (internal integrated circuit bus interface). A temperature Sensor (Temp Sensor) may also be provided in the CMOS image Sensor. The CMOS image sensor may further include Voltage & Current Generator (Voltage-current generator) that supplies power to the Pixel Array and the ADC.
The embodiment of the application also provides a circulating ADC circulating method for the CMOS image sensor, which can be applied to the circulating ADC for the CMOS image sensor; as shown in fig. 8, the method may include step S101:
s101, sequentially and circularly executing a plurality of preset working modes; and in the working modes, the output voltages of different capacitors in the circulating ADC sample the output voltages of a transconductance amplifier (OTA), and when the modes change, the connection mode of the capacitors and the polarity of the connected ends are changed, so that the charges on the capacitors are combined to eliminate offset voltages.
In an exemplary embodiment of the present application, the plurality of operation modes may include: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the capacitance may include: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected in series to the input end and the output end of the amplifier in the cyclic ADC, the at least two capacitors are connected with the input end and the output end of the digital-to-analog converter DAC, and the polarity of the input end and the output end of the at least two capacitors in the first group of capacitors in the first working mode is opposite to that of the input end and the output end of the at least two capacitors in the first group of capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; to eliminate offset voltages by charge combination on the second set of capacitors.
In the exemplary embodiment of the application, on the basis of the traditional CYCLIC ADC, the performance of CYCLIC ADC is greatly improved by adding a capacitance averaging technology and a chopper extinction technology, and 16-bit conversion accuracy can be realized.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (5)
1. A cyclic ADC for a CMOS image sensor, comprising: the transconductance amplifier, the chopper, the capacitors with the same capacitance values and the control switches;
the chopper is arranged to control the connection mode of the input end and the output end of the transconductance amplifier and the capacitor; the input terminal comprises: a forward input and a reverse input, the output comprising: a forward output and a reverse output;
the control switch is arranged to control the access mode of the transconductance amplifier and the capacitor in each working mode;
wherein the chopper and the plurality of control switches are switched such that the cyclic analog-to-digital converter ADC has a plurality of said modes of operation; the plurality of operation modes include: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the first working mode, the second working mode, the third working mode and the fourth working mode are sequentially and circularly executed; the plurality of capacitors having the same capacitance value include: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are connected in series to the input end and the output end respectively; the at least two capacitors are connected with the input end and the DAC output end, and the input ends and the output ends of the at least two capacitors in the first working mode are opposite to the polarity of the input ends and the output ends of the at least two capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; eliminating offset voltage by combining charges on the second group of capacitors;
wherein the chopper comprises a first chopper and a second chopper;
wherein the first chopper and the second chopper are both used for connecting the first group of capacitors or the second group of capacitors with the forward input end and the reverse input end;
the DAC output terminal comprises: a first DAC output and a second DAC output; the first set of capacitances includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the second set of capacitances includes: a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor;
the first capacitor, the second capacitor, the fifth capacitor and the sixth capacitor are used for being connected with an input end or an output end of the first side of the transconductance amplifier; the third capacitor, the fourth capacitor, the seventh capacitor and the eighth capacitor are used for being connected with an input end or an output end of the second side of the transconductance amplifier;
wherein, the first working mode includes: the first capacitor is connected in series between the first DAC output end and the reverse input end; the second capacitor is connected in series between the reverse input end and the forward output end; the first end of the fifth capacitor is connected with the positive output end, and the second end is applied with a common mode level; the sixth capacitor is suspended; the third capacitor is connected in series between the second DAC output end and the positive input end; the fourth capacitor is connected in series between the positive input end and the negative output end; the first end of the seventh capacitor is connected with the reverse output end, and the second end is applied with the common mode level; the eighth capacitor is suspended;
wherein, the second working mode includes: the second capacitor is connected in series between the first DAC output end and the positive input end; the first capacitor is connected in series between the positive input end and the negative output end; the first end of the sixth capacitor is connected with the reverse output end, and the second end is applied with a common mode level; the fifth capacitor is suspended; the fourth capacitor is connected in series between the second DAC output end and the reverse input end; the third capacitor is connected in series between the reverse input end and the forward output end; the first end of the eighth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the eighth capacitor; the seventh capacitor is suspended;
wherein, the third working mode includes: the fifth capacitor is connected in series between the first DAC output end and the reverse input end; the sixth capacitor is connected in series between the reverse input end and the forward output end; the first end of the first capacitor is connected with the positive output end, and the second end is applied with a common mode level; the second capacitor is suspended; the seventh capacitor is connected in series between the second DAC output end and the positive input end; the eighth capacitor is connected in series between the positive input end and the negative output end; the first end of the third capacitor is connected with the reverse output end, and the second end of the third capacitor is applied with the common mode level; the fourth capacitor is suspended;
wherein the fourth mode of operation comprises: the sixth capacitor is connected in series between the first DAC output end and the positive input end; the fifth capacitor is connected in series between the positive input end and the negative output end; the first end of the second capacitor is connected with the reverse output end, and the second end is applied with a common mode level; the first capacitor is suspended; the eighth capacitor is connected in series between the second DAC output end and the reverse input end; the seventh capacitor is connected in series between the reverse input end and the forward output end; the first end of the fourth capacitor is connected with the positive output end, and the common mode level is applied to the second end of the fourth capacitor; the third capacitor is suspended.
2. The cyclic ADC for a CMOS image sensor of claim 1, wherein the plurality of operating modes further comprises: an initial sampling mode;
in the initial sampling mode, the first group of capacitors are used as sampling capacitors for signal acquisition to acquire initial acquisition voltage; and the chopper and the transconductance amplifier, and the chopper and the capacitor are in an off state, and the capacitors in the second group of capacitors are in a floating state.
3. The cyclic ADC for a CMOS image sensor of claim 2, wherein the initial sampling mode comprises:
the first capacitor and the second capacitor are connected in parallel;
the first ends of the first capacitor and the second capacitor are connected with a forward input signal Vip, and the second ends are applied with a common mode level;
the third capacitor and the fourth capacitor are connected in parallel;
the first ends of the third capacitor and the fourth capacitor are connected with an inverted input signal Vin, and the second ends are applied with the common mode level.
4. A recycling method of a recycling ADC for a CMOS image sensor, characterized in that it is applicable to the recycling ADC for a CMOS image sensor according to any one of claims 1 to 3; the method comprises the following steps:
sequentially and circularly executing a plurality of preset working modes; and in the multiple working modes, different capacitors in the circulating ADC sample output voltages of the transconductance amplifier, and when the modes change, the connection mode of the capacitors and the polarity of the connected ends are changed, so that charges on the capacitors are combined to eliminate offset voltages.
5. The recycling method of recycling ADC for CMOS image sensors according to claim 4, wherein the plurality of operation modes comprises: a first mode of operation, a second mode of operation, a third mode of operation, and a fourth mode of operation; the capacitor includes: a first set of capacitors and a second set of capacitors;
in the first working mode and the second working mode, at least two capacitors in the first group of capacitors are respectively connected in series to the input end and the output end of the transconductance amplifier in the circulating ADC; the at least two capacitors are connected with the input end and the DAC output end, and the input ends and the output ends of the at least two capacitors in the first working mode are opposite to the polarity of the input ends and the output ends of the at least two capacitors in the second working mode;
in the first working mode and the second working mode, voltage sampling is further performed through different capacitors in at least two capacitors of the second group of capacitors;
the positions of the first group of capacitors and the second group of capacitors in the first working mode are interchanged in the third working mode; the positions of the first group of capacitors and the second group of capacitors in the second working mode are interchanged in the fourth working mode; to eliminate offset voltages by charge combination on the second set of capacitors.
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