CN114242765A

CN114242765A - Semiconductor device structure and preparation method thereof

Info

Publication number: CN114242765A
Application number: CN202111312080.0A
Authority: CN
Inventors: 李�杰; 张曌; 魏国栋; 刘玮
Original assignee: SHENZHEN SI SEMICONDUCTORS CO Ltd
Current assignee: SHENZHEN SI SEMICONDUCTORS CO Ltd
Priority date: 2021-11-08
Filing date: 2021-11-08
Publication date: 2022-03-25

Abstract

The invention discloses a semiconductor device structure and a preparation method thereof, wherein the preparation method of the semiconductor device structure comprises the following steps: providing a substrate; forming a groove in the substrate; forming a split gate structure in the groove, wherein the split gate structure comprises a virtual split gate structure and a leading-out part, and the leading-out part is positioned on the upper surface of the virtual split gate structure; compare with traditional vertical gate MOS pipe primitive cell structure, under same area size, the upper surface of extraction portion is parallel and level with the upper surface of slot, the metal electrode layer short circuit of extraction portion and follow-up formation of being convenient for, cause the central point of depletion region to move down when semiconductor device structure pressurization, electric field intensity when causing P to tie P district to exhaust reduces and increases breakdown voltage, make this application semiconductor device structure compare in traditional primitive cell structure under same breakdown voltage, primitive cell number reduces relatively, under the same specification condition, greatly reduce parasitic gate leakage capacitance Cdg, effectively reduce the switching loss of device, reduce and generate heat, improve the reliability and the security of device.

Description

Semiconductor device structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device structure and a preparation method thereof.

Background

The middle and low voltage Trench MOS is continuously flourishing and developing in recent years, the demand of the domestic market is gradually increased year by year due to the continuous demand of portable equipment and charging adapters, and the market demand of the device is explosively increased under the large environment that domestic semiconductors replace imported semiconductors. The transistor device has the advantages of small area size, low on-resistance, low dynamic loss, more energy-saving characteristic and high cost performance, can be packaged in a smaller patch packaging form, and is suitable for terminal customers to carry and move terminal products.

The traditional low-voltage groove MOS tube is not suitable for a high-power-frequency circuit, and has the disadvantages of high switching loss, obvious heating and the like, the main reason is that the parasitic capacitance of the primitive structure is large, more charge charges are needed during high-speed switching, and the formed parasitic capacitance has high alternating current passing through the switch, so that the energy loss of the device switch is high and the temperature is raised when the circuit is applied, the safe operation of a transistor is not facilitated, and the loss of lives and properties is caused by high-temperature failure.

Disclosure of Invention

Therefore, it is necessary to provide a semiconductor device structure and a manufacturing method thereof for solving the technical defects of the cell structure of the conventional low-voltage trench MOS transistor and reducing the effective area of the parasitic gate-drain capacitance in the semiconductor device structure, so as to reduce the value of the parasitic gate-drain capacitance Cdg to improve the adverse factors such as the heat generation and temperature rise of the transistor switch and improve the operational reliability of the semiconductor device structure.

In order to solve the above technical problem, a first aspect of the present application provides a method for manufacturing a semiconductor device structure, including:

providing a substrate;

forming a groove in the substrate;

forming a split gate structure in the groove, wherein the split gate structure comprises a virtual split gate structure and a leading-out part, and the leading-out part is positioned on the upper surface of the virtual split gate structure; the upper surface of the leading-out part is flush with the upper surface of the groove.

In the method for manufacturing a semiconductor device structure provided in the above embodiment, the split-gate structure formed in the trench is divided into two parts, namely the virtual split-gate structure and the lead-out portion, and the lead-out portion is located on the upper surface of the virtual split-gate structure, compared with the conventional vertical-gate MOS transistor cell structure, under the same area size, the upper surface of the lead-out portion is flush with the upper surface of the trench, so that the lead-out portion is in short circuit with a metal electrode layer formed subsequently, that is, the split-gate structure is in short circuit with the metal electrode layer, so that the central point of the depletion region moves down when the semiconductor device structure is pressurized, the electric field strength when the P region of the P junction is depleted is reduced, and the breakdown voltage is increased, so that the number of cells of the semiconductor device structure of the present application is relatively reduced under the same breakdown voltage compared with the conventional cell structure, under the same specification condition, the parasitic gate leakage capacitance Cdg is greatly reduced, and the switching loss of the device is effectively reduced, reduce the heat generation and improve the reliability and the safety of the device.

In one embodiment, the substrate comprises a substrate and an epitaxial layer which are sequentially stacked from bottom to top; the trench is located within the epitaxial layer.

In one embodiment, the forming of the split-gate structure in the trench includes:

forming a cracked gate oxide material layer on the surface of the groove and the upper surface of the epitaxial layer;

forming a virtual grid electrode material layer on the surface of the split grid oxide material layer, wherein the groove is filled with the virtual grid electrode material layer;

removing the split gate oxide material layer on the upper surface of the epitaxial layer and the virtual gate material layer on the epitaxial layer, and back-etching the reserved virtual gate material layer to obtain a virtual gate and the lead-out part; the lead-out part is positioned on the upper surface of the virtual grid.

In one embodiment, after the forming the dummy gate, the method further includes:

and removing part of the splitting gate oxide material layer by adopting wet etching to obtain a splitting gate oxide layer, wherein the splitting gate oxide layer and the virtual gate jointly form the virtual splitting gate structure.

In one embodiment, after forming the split-gate structure in the trench, the method further includes:

forming an effective grid structure on the upper surface of the virtual split grid structure and the side wall of the leading-out part;

and forming a filling oxide layer on the effective gate structure, wherein the filling oxide layer fills the groove.

In one embodiment, the forming an effective gate structure on the surface of the split-gate structure includes:

forming an effective gate oxide material layer on the surface of the split gate structure, the side wall of the groove and the upper surface of the epitaxial layer;

forming an initial effective grid electrode material layer on the surface of the effective grid oxide material layer;

removing the effective gate oxide material layer on the upper surface of the epitaxial layer and the initial effective gate material layer on the epitaxial layer, and removing the effective gate oxide material layer on the upper surface of the lead-out part and the initial effective gate material layer on the lead-out part to obtain an effective gate oxide layer and an effective gate material layer; the effective grid material layer is positioned on two sides of the leading-out part;

etching the effective grid material layer to obtain an effective grid; the effective grid electrodes are positioned on two sides of the filling oxide layer; the effective grid and the effective grid oxide layer jointly form an effective grid structure.

In one embodiment, after forming the filling oxide layer, the method further includes:

forming a body region, wherein the body region is positioned in the epitaxial layer and positioned between the adjacent trenches;

forming a source region on the upper surface of the body region, wherein the source region is positioned in the epitaxial layer;

forming isolation oxide layers on the upper surfaces of the filling oxide layers, the upper surfaces of the effective gate structures and the upper surface of the epitaxial layer;

forming a contact hole, wherein the contact hole comprises a split gate contact hole, a source contact hole and a gate contact hole, and the source contact hole penetrates through the isolation oxide layer and the source region; the split gate contact hole penetrates through the isolation oxide layer to expose the leading-out part; the grid contact hole penetrates through the isolation oxide layer to expose the effective grid;

forming a metal electrode layer on the surface of the isolation oxide layer, wherein the contact hole is filled with the metal electrode layer; the metal electrode layer is electrically connected with the lead-out part through the split gate contact hole; the metal electrode layer is electrically connected with the body region through the source contact hole; the metal electrode layer is electrically connected with the effective gate structure through the gate contact hole.

A second aspect of the present application provides a semiconductor device structure comprising:

a substrate;

a trench in the substrate;

the split gate structure is positioned in the groove; the split gate structure comprises a virtual split gate structure and a leading-out part, and the leading-out part is positioned on the upper surface of the virtual split gate structure; the upper surface of the leading-out part is flush with the upper surface of the groove.

In one embodiment, the base comprises a substrate and an epitaxial layer, wherein the epitaxial layer is positioned on the upper surface of the substrate; the trench is located within the epitaxial layer.

In one embodiment, the virtual split gate structure comprises a virtual gate and a split gate oxide layer, wherein the split gate oxide layer is positioned on the surface of the groove; the virtual grid is positioned on the surface of the split gate oxide layer; the lead-out part is positioned on the upper surface of the virtual grid.

In one embodiment, the method further comprises the following steps:

the effective grid structure covers the upper surface of the virtual split grid structure and the side wall of the leading-out part;

and the filling oxide layer is positioned on the effective gate structure and fills the groove.

In one embodiment, the effective gate structure comprises an effective gate and an effective gate oxide layer, wherein the effective gate oxide layer is positioned on the upper surface of the virtual split gate structure and the side wall of the groove and covers the side wall of the leading-out part; the effective grid electrode is positioned on the surface of the effective grid oxide layer and positioned on two sides of the filling oxide layer.

In one embodiment, the method further comprises the following steps:

the body region is positioned in the epitaxial layer and positioned between the adjacent trenches;

the source region is positioned in the epitaxial layer and positioned on the upper surface of the body region;

the isolation oxide layer is positioned on the surface of the filling oxide layer, the surface of the effective gate structure and the epitaxial layer;

the contact hole comprises a split gate contact hole, a source contact hole and a gate contact hole, and the source contact hole penetrates through the isolation oxide layer and the source region; the split gate contact hole penetrates through the isolation oxide layer to expose the leading-out part; the grid contact hole penetrates through the isolation oxide layer to expose the effective grid;

the metal electrode layer is positioned on the surface of the isolation oxide layer and fills the contact hole; the metal electrode layer is electrically connected with the lead-out part through the split gate contact hole; the metal electrode layer is electrically connected with the body region through the source contact hole; the metal electrode layer is electrically connected with the effective gate structure through the gate contact hole.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.

Fig. 1 is a schematic flow chart of a method for fabricating a semiconductor device structure provided in an embodiment of the present application;

fig. 2(a) is a schematic partial top view, fig. 2 (b) is a schematic partial cross-sectional structure taken along the direction AA 'in fig. 2(a), and fig. 2 (c) is a schematic partial cross-sectional structure taken along the direction BB' in fig. 2(a), after forming the trench, according to an embodiment of the present application;

fig. 3 is a schematic partial cross-sectional structure diagram for forming a split gate oxide layer provided in an embodiment of the present application, wherein fig. 3 (a) is a schematic partial cross-sectional structure diagram taken along direction AA 'in fig. 2(a), and fig. 3 (b) is a schematic partial cross-sectional structure diagram taken along direction BB' in fig. 2 (a);

fig. 4 is a schematic partial cross-sectional structure diagram of a dummy gate material layer formed in an embodiment of the present application, wherein fig. 4 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 4 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 5 is a schematic partial cross-sectional structure view of a structure obtained after an etching process is performed on a dummy gate material layer and a split gate oxide material layer according to an embodiment of the present disclosure, where fig. 5 (a) is a schematic partial cross-sectional structure view taken along an AA 'direction in fig. 2(a), and fig. 5 (b) is a schematic partial cross-sectional structure view taken along a BB' direction in fig. 2 (a);

fig. 6 is a schematic partial cross-sectional structure diagram of forming a dummy gate and a lead-out portion according to an embodiment of the present disclosure, wherein fig. 6 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 6 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 7 is a schematic partial cross-sectional structure diagram for forming a split gate oxide layer provided in an embodiment of the present application, wherein fig. 7 (a) is a schematic partial cross-sectional structure diagram taken along direction AA 'in fig. 2(a), and fig. 7 (b) is a schematic partial cross-sectional structure diagram taken along direction BB' in fig. 2 (a);

fig. 8 is a schematic partial cross-sectional structure for forming an effective gate oxide layer provided in an embodiment of the present application, wherein fig. 8 (a) is a schematic partial cross-sectional structure taken along direction AA 'in fig. 2(a), and fig. 8 (b) is a schematic partial cross-sectional structure taken along direction BB' in fig. 2 (a);

fig. 9 is a schematic partial cross-sectional structure diagram for forming an initial effective gate material layer provided in an embodiment of the present application, wherein (a) in fig. 9 is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and (b) in fig. 9 is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 10 is a schematic partial cross-sectional structure diagram of a structure obtained after an etching process is performed on an initial effective gate material layer and an effective gate oxide material layer according to an embodiment of the present application, where fig. 10 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 10 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 11 is a schematic partial cross-sectional structure diagram for forming an effective gate material layer provided in an embodiment of the present application, in which fig. 11 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 11 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 12 is a schematic partial cross-sectional structure diagram for forming a filler material layer provided in an embodiment of the present application, in which fig. 12 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 12 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 13 is a schematic partial cross-sectional structure diagram for forming a filling layer provided in an embodiment of the present application, in which fig. 13 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 13 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 14 is a schematic partial cross-sectional structure diagram illustrating the formation of a body region, a source region, an isolation oxide layer and a contact hole according to an embodiment of the present disclosure, wherein fig. 14 (a) is a schematic partial cross-sectional structure diagram taken along the AA 'direction in fig. 2(a), and fig. 14 (b) is a schematic partial cross-sectional structure diagram taken along the BB' direction in fig. 2 (a);

fig. 15 is a schematic partial cross-sectional structure diagram for forming a metal electrode layer according to an embodiment of the present disclosure, in which fig. 15 (a) is a schematic partial cross-sectional structure diagram taken along an AA 'direction in fig. 2(a), and fig. 15 (b) is a schematic partial cross-sectional structure diagram taken along a BB' direction in fig. 2 (a);

fig. 16 is a schematic partial top view of a semiconductor device structure formed as provided in an embodiment of the present application;

fig. 17 is a schematic partial cross-sectional structure diagram of a semiconductor device structure formed in an embodiment of the present application, where fig. 17 (a) is a schematic partial cross-sectional structure diagram taken along a direction CC 'in fig. 16, and fig. 17 (b) is a schematic partial cross-sectional structure diagram taken along a direction DD' in fig. 16.

Description of reference numerals: 10-base, 11-substrate, 12-epitaxial layer, 121-trench;

20-split gate structure, 21-virtual split gate structure, 22-lead-out part;

211-splitting gate oxide layer, 2111-splitting gate oxide layer;

212-virtual gate, 2121-virtual gate material layer;

30-an effective gate structure, 31-an effective gate oxide layer, 311-an effective gate oxide material layer, 32-an effective gate, 321-an effective gate material layer, 3211-an initial effective gate material layer;

40-filling an oxide layer, 41-filling an oxide material layer;

51-body region, 52-source region, 53-isolation oxide layer;

60-contact hole, 61-source contact hole, 62-split gate contact hole, 63-gate contact hole;

70-metal electrode layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

The parasitic capacitance of the traditional low-voltage groove MOS tube primitive cell structure is respectively provided with an input capacitance Ciss, an output capacitance Coss and a Miller capacitance Crss, and the components of each capacitance are as follows: ciss + Cdg, Coss + Cdg + Cds, and Crss Cgd (three electrodes of a MOS transistor are g: a gate, d: a drain, and S: a source), wherein a gate-drain capacitance Cdg is a main parasitic capacitance, that is, a miller capacitance Crss, and three surfaces of a long rectangular vertical polysilicon gate structure in a conventional cell structure are effective surfaces of the parasitic capacitance, which all cause that a large alternating current occurs when the transistor is turned on and off, so that high switching loss is generated and heat is generated.

Based on the capacitance calculation formula, the dielectric constant is constant, and only the dielectric area is reduced and the thickness of the dielectric is increased to reduce the parasitic gate-drain capacitance. Therefore, the semiconductor device structure and the preparation method thereof are provided, the technical defect of the original cell structure of the traditional low-voltage groove MOS tube is overcome, the effective area of the parasitic gate-drain capacitor in the semiconductor device structure is reduced, the value of the parasitic gate-drain capacitor Cdg is reduced to improve the adverse factors such as the heating temperature rise of the switch of the transistor, and the operation reliability of the semiconductor device structure is improved.

In one embodiment of the present application, as shown in fig. 1, there is provided a method of fabricating a semiconductor device structure, comprising the steps of:

step S10: providing a substrate;

step S20: forming a groove in the substrate;

step S30: forming a split gate structure in the groove, wherein the split gate structure comprises a virtual split gate structure and a leading-out part, and the leading-out part is positioned on the upper surface of the virtual split gate structure; the upper surface of the leading-out part is flush with the upper surface of the groove.

Specifically, the upper surface of the leading-out part is flush with the upper surface of the groove, the leading-out part is convenient to be in short circuit with a metal electrode layer formed subsequently, so that the central point of a depletion region moves downwards when the cell is pressurized, the electric field intensity when a P-junction P region is depleted is reduced, the breakdown voltage is increased, the resistivity of an epitaxial layer inside and outside a substrate can be reduced, and the on-resistance of a device is reduced.

In one embodiment, as shown in fig. 2, the substrate 10 provided in step S10 includes a substrate 11 and an epitaxial layer 12 stacked in sequence from bottom to top; the trench 121 in step S20 is located within the epitaxial layer 12.

In particular, both the substrate 11 and the epitaxial layer 12 are of a first conductivity type, the substrate 11 of the first conductivity type being heavily doped with a doping concentration greater than 1E18cm^-3(ii) a As an example, the first conductivity type is N-type, and the substrate 11 of the first conductivity type is heavily doped N-type, which is denoted as N +; the epitaxial layer of the first conductivity type is lightly doped N-type, denoted as N-.

In one embodiment, step S20: forming a trench 121 in the substrate 10 includes the following steps:

step S11: forming on the upper surface of the epitaxial layer

And deposited by CVD technique

The hard mask oxide layer TEOS is subjected to high-temperature oxygen densification treatment;

step S12: coating the hard mask oxide layer to a thickness of

Exposing, developing and etching the positive photoresist to clean the hard mask oxide layer of the slotted window and leak the epitaxial layer;

step S13: removing the positive photoresist on the surface, forming an initial groove by etching the epitaxial layer by a dry method based on the hard mask oxide layer, and cleaning the etched sediment in the initial groove by SC1, SC2, SC3 liquid and HF acid;

step S14: thermal growth on the sidewalls and bottom of the initial trench

The sacrificial oxide layer is used for improving and optimizing the state of the side wall of the initial groove;

step S15: and removing the residual hard mask oxide layer and the sacrificial oxide layer by wet etching to obtain the groove. As an example, in step S11, the thickness of the thermal oxidation layer may be

Or

And the like; the hard mask oxide layer TEOS may have a thickness of

Or

And the like; the sacrificial oxide layer may have a thickness of

Or

And the like; the positive photoresist has a thickness of

Or

And the like; the width of the groove is 0.7um to 1um, and the depth of the groove is 3um to 6 um. Such as trench widths of 0.7um, 0.8um, or 1um, etc.; the trench depth is 3um, 5um or 6um, etc.

By way of example, the SC1 solution is a mixed solution of ammonium hydroxide/hydrogen peroxide/deionized water; the SC2 solution is a mixed solution of hydrochloric acid/hydrogen peroxide/deionized water; the SC3 solution was a hydrogen peroxide sulfate/deionized water mixture.

In one embodiment, step S30: forming a split gate structure in the trench, comprising the steps of:

step S31: forming a gate oxide layer 2111 on the surface of the trench 121 and the upper surface of the epitaxial layer 12, as shown in fig. 3;

step S32: forming a dummy gate material layer 2121 on the surface of the split gate oxide layer 2111, wherein the dummy gate material layer 2121 fills the trench 121, as shown in fig. 4;

step S33: removing the split gate oxide material layer 2111 on the upper surface of the epitaxial layer 12 and the dummy gate material layer 2111 on the epitaxial layer 12, as shown in fig. 5; and the remaining dummy gate material layer 2111 is etched back to obtain the dummy gate 212 and the lead portion 22, as shown in fig. 6 (a); the lead portion 22 is located on the upper surface of the dummy gate 212, as shown in fig. 6 (b).

As an example, the split gate oxide material layer 2111 and the dummy gate oxide material layer 2111 are etched by a dry etching process or a Chemical Mechanical Polishing (CMP) process, and with continued reference to fig. 5, after removing a portion of the dummy gate material layer 2111 and a portion of the split gate oxide material layer 2111, the upper surface of the dummy gate material layer 2111 and the upper surface of the split gate oxide material layer 211 which remain are both flush with the upper surface of the epitaxial layer 12.

As an example, a thermal growth process is used to deposit a split gate oxide layer 2111, the split gate oxide layer 2111 having a thickness of

For example, the thickness of the split gate oxide layer 2111 is

Or

And the like; the layer 2111 of dummy gate material on the epitaxial layer 12 has a thickness of

For example, the dummy gate material layer 2111 on the epitaxial layer 12 has a thickness of

Or

And so on.

As an example, a positive photoresist layer (not shown) is coated on the remaining dummy gate material layer 12, and is exposed and developed respectively, where the positive photoresist layer is located in a region where the reserved split gate structure is short-circuited with the metal electrode layer. Etching part of the dummy gate material layer 2111 in the trench 121 by using a dry etching process including but not limited to dry etching, so as to form the dummy gate 212 and the lead-out portion 22 in one step, and meanwhile, reserving enough depth for an effective gate structure; finally, the positive photoresist layer is removed by using a dry method and a wet method.

In one embodiment, step S33: after forming the dummy gate 212, the method further includes:

step S34: and removing part of the split gate oxide material layer 2111 by wet etching to obtain a split gate oxide layer 211, wherein the split gate oxide layer 211 and the dummy gate 212 jointly form a dummy split gate structure 21, as shown in fig. 7.

By way of example, the split gate oxide layer 211 includes, but is not limited to, a silicon oxide layer; the dummy gate 212 includes, but is not limited to, a doped polysilicon layer. The lead portion 22 and the dummy gate 212 are made of the same material.

As an example, the upper surface of the split gate oxide layer 211 is flush with the upper surface of the dummy gate 212 in order to fabricate a regular effective gate structure.

In one embodiment, step S30: after forming the split-gate structure 20 in the trench 121, the method further includes:

step S40: forming an effective gate structure on the upper surface of the virtual split gate structure and the side wall of the leading-out part;

step S50: and forming a filling oxide layer on the effective gate structure, wherein the filling oxide layer fills the groove.

In one embodiment, step S40: forming an effective grid structure on the upper surface of the virtual split grid structure and the side wall of the leading-out part, and comprising the following steps of:

step S41: forming an effective gate oxide material layer 311 on the surface of the split-gate structure 20, the sidewall of the trench 121 and the upper surface of the epitaxial layer 12, as shown in fig. 8;

step S42: forming an initial effective gate material layer 3211 on the surface of the effective gate oxide material layer 311, the initial effective gate material layer 3211 filling the trench 121, as shown in fig. 9;

step S43: removing the effective gate oxide material layer 311 on the upper surface of the epitaxial layer 12 and the initial effective gate material layer 3211 on the epitaxial layer 12, as shown in fig. 10; removing the effective gate oxide material layer 311 on the upper surface of the lead-out part 22 and the initial effective gate material layer 311 on the lead-out part to obtain an effective gate oxide layer 31 and an effective gate material layer 321; the effective gate material layer 311 is located on both sides of the lead-out portion 22, as shown in fig. 10 (b);

step S44: the active gate material layer 321 is etched to obtain an active gate 32, and the active gate 32 and the active gate oxide 31 together form an active gate structure 30, as shown in fig. 11.

As an example, the effective gate oxide layer 311 is formed using an oxidation process including, but not limited to, thermal growth, the effective gate oxide layer 311 having a thickness of

For example, the effective gate oxide layer 311 has a thickness of

And the like; the thermal growth temperature of the effective gate oxide material layer 311 is 1000-1500 ℃; for example, the thermal growth temperature is 1000 deg.C, 1150 deg.C or 1500 deg.C, etc。

As an example, a positive photoresist (not shown) is formed on the upper surface of the effective gate material layer 321, and is exposed and developed; performing an etching process on the effective gate material layer 321 based on the positive photoresist to form an effective gate 32; the positive photoresist is removed, and the impurities in the exposed trench 121 are cleaned by SC1, SC2 and SC 3.

As an example, the effective gate oxide layer 31 includes, but is not limited to, a silicon oxide layer; the active gate 32 includes, but is not limited to, a polysilicon layer or a doped polysilicon layer; the material of the active gate 32 may be the same as or different from that of the dummy gate 212.

As an example, the effective gate oxide layer 311 on the upper surface of the epitaxial layer 12 and the initial effective gate material layer 3211 on the epitaxial layer 12 are removed by a chemical mechanical polishing process; it should be noted that the effective gate oxide layer 311 on the upper surface of the epitaxial layer 12 and the initial effective gate material layer 3211 on the epitaxial layer 12, and the effective gate oxide layer 311 on the upper surface of the lead portion 22 and the initial effective gate material layer 311 on the lead portion may be removed at the same time.

In one embodiment, the step of filling the oxide layer formed in step S50 includes the following steps:

step S51: forming a filling oxide material layer 41 on the upper surface of the epitaxial layer 12, the upper surface of the effective gate oxide layer, the upper surfaces of the effective gate 32 and the lead-out portion 22, as shown in fig. 12;

step S52: the filling oxide layer 41 on the upper surface of the epitaxial layer 12 and the filling oxide layer 41 on the upper surface of the lead-out portion 22 are removed to obtain the filling oxide layer 40, as shown in fig. 13.

As an example, the effective gates 32 are located at two sides of the filled oxide layer 40, and two effective gates 32 in the same trench 121 are isolated by the filled oxide layer 40, so that the gate charge of the device can be reduced, and the figure of merit of the device, which is the on-resistance of the device.

By way of example, the width of the effective gate 32 is 0.2um-0.5um, such as the width of the effective gate 32 is 0.2um, 0.3um, or 0.5um, and so on.

In the above embodiment, the gate structure in the trench 121 is divided into an upper portion and a lower portion, the upper portion is the effective gate structure 30, the lower portion is the split gate structure 20, the effective gate structure 30 and the split gate structure 20 are isolated by the effective gate oxide layer 31, the distance between the gate and the drain is increased, and the parasitic capacitance is reduced; the split gate structure 20 is in short circuit with the formed metal electrode layer, so that the central point of a depletion region moves downwards when the cell is pressurized, the electric field intensity is reduced when a P-junction P region is depleted, the breakdown voltage is increased, the resistivity of an epitaxial layer in a substrate can be reduced, and the on-resistance of a device is reduced, even if the size of the semiconductor device structure is increased, the resistivity of the epitaxial layer can be reduced, the on-resistance parameters of more traditional cell structures can be reached by using smaller number of cells, namely the effective area of the device is reduced, so that the parasitic gate-drain capacitance of the semiconductor structure and the traditional cell structure is greatly reduced compared with the traditional cell structure under the same specification and the same breakdown voltage; the thicker effective gate oxide layer 31 forms a dielectric layer between gate and drain, so that parasitic gate-drain capacitance is effectively reduced; the fill oxide layer 40 isolates the active gate 32, greatly reducing the gate charge, improving the figure of merit, and reducing the parasitic gate-to-drain capacitance when the device is in operation. The effective grid 32, the split-gate structure 20, the effective gate structure 30 and the filling oxide layer 40 jointly form a cell trench structure of the device, so that the parasitic capacitance dielectric area of the cell between the gates and the drain is reduced, the dielectric thickness is increased, the parasitic capacitance of the device is fully reduced, the grid charge Qg is reduced, the switching loss of the transistor device in circuit application is reduced, adverse factors such as temperature rise and heat generation of the transistor device are reduced, and the reliability and the safety of the operation of the transistor device are improved.

In one embodiment, step S50: after forming the filling oxide layer 40, the method further includes the following steps:

step S61: forming a body region 51, wherein the body region 51 is positioned in the epitaxial layer 12 and positioned between the adjacent trenches 121;

step S62: forming a source region 52 on the upper surface of the body region 51, the source region 52 being located in the epitaxial layer 12;

step S63: forming an isolation oxide layer 53 on the upper surface of the filling oxide layer 40, the upper surface of the effective gate structure 30 and the upper surface of the epitaxial layer 12;

step S64: forming a contact hole 60, wherein the contact hole 60 comprises a split gate contact hole 62, a source contact hole 61 and a gate contact hole 63, and the source contact hole 61 penetrates through the isolation oxide layer 53 and the source region 52; the split gate contact hole 62 penetrates through the isolation oxide layer 53 to expose the lead-out portion 22; the gate contact hole 63 penetrates through the isolation oxide layer 53 to expose the effective gate 32, as shown in fig. 14;

step S65: forming a metal electrode layer 70 on the surface of the isolation oxide layer 53, wherein the metal electrode layer 70 fills the contact hole 60; the metal electrode layer 70 is electrically connected to the lead-out portion 22 via the split gate contact hole 62; the metal electrode layer 70 is electrically connected to the body region 51 via the source contact hole 61; the metal electrode layer 70 is electrically connected to the effective gate structure 30 via the gate contact hole 63, as shown in fig. 15;

as an example, the split gate contact hole 62, the source contact hole 61, and the gate contact hole 63 are formed in one step, as shown in fig. 17.

In an embodiment of the present application, as shown in fig. 16, there is also provided a semiconductor device structure including:

a substrate 10;

a trench 121 in the substrate 10;

a split-gate structure 20 located within the trench 121; the split gate structure 20 comprises a virtual split gate structure 21 and a leading-out part 22, and the leading-out part 22 is positioned on the upper surface of the virtual split gate structure 21; the upper surface of the lead-out portion 22 is flush with the upper surface of the groove 121.

In the semiconductor device structure provided in the above embodiment, the split-gate structure formed in the trench is divided into the virtual split-gate structure and the lead-out portion, and the lead-out portion is located on the upper surface of the virtual split-gate structure, and compared with the conventional vertical-gate MOS transistor cell structure, under the same area size, the upper surface of the lead-out portion is flush with the upper surface of the trench, so that the lead-out portion is in short circuit with the subsequently formed metal electrode layer, that is, the split-gate structure is in short circuit with the metal electrode layer, so that the central point of the depletion region moves down when the semiconductor device structure is pressurized, and the electric field strength when the P-junction P region is depleted is reduced to increase the breakdown voltage, so that the number of cells is relatively reduced and the effective area is reduced compared with the conventional vertical-gate cell structure under the same breakdown voltage, and the parasitic gate leakage capacitance Cdg is greatly reduced under the same specification condition, effectively reduce the switching loss of the device, reduce the heating and improve the reliability and the safety of the device.

In one embodiment, the substrate 10 includes a substrate 11 and an epitaxial layer 12, wherein the epitaxial layer 12 is located on an upper surface of the substrate 11; trenches 121 are located within epitaxial layer 12.

In one embodiment, the dummy split-gate structure 21 includes a dummy gate 212 and a split gate oxide layer 211, the split gate oxide layer 211 is located on the surface of the trench 121; the dummy gate 212 is positioned on the surface of the split gate oxide layer 211; the lead-out portion 22 is located on the upper surface of the dummy gate 212.

In one embodiment, the semiconductor device structure further comprises:

an effective gate structure 30 covering the upper surface of the virtual split gate structure 21 and the side wall of the lead-out portion 22;

the filled oxide layer 40 is located on the effective gate structure 30 and fills the trench 121.

In one embodiment, the effective gate structure 30 includes an effective gate 32 and an effective gate oxide 31, the effective gate oxide 32 is located on the upper surface of the dummy split gate structure 21 and the sidewall of the trench 121, and covers the sidewall of the lead-out portion 22; the effective grid 32 is positioned on the surface of the effective grid oxide layer 31 and positioned on two sides of the filling oxide layer 40.

In one embodiment, the semiconductor device structure further comprises:

a body region 51 located within the epitaxial layer 12 and between adjacent trenches 121;

a source region 52 located in the epitaxial layer 12 and located on the upper surface of the body region 51;

an isolation oxide layer 53 on the surface of the filling oxide layer 40, the surface of the effective gate structure 30 and the epitaxial layer 12;

a contact hole 60, wherein the contact hole 60 comprises a split gate contact hole 62, a source contact hole 61 and a gate contact hole 63, and the source contact hole 61 penetrates through the isolation oxide layer 53 and the source region 52; the split gate contact hole 62 penetrates through the isolation oxide layer 53 to expose the lead-out portion 22; the gate contact hole 63 penetrates through the isolation oxide layer 53 to expose the effective gate 32;

a metal electrode layer 70 located on the surface of the isolation oxide layer 53 and filling the contact hole 60; the metal electrode layer 70 is electrically connected to the lead-out portion 22 via the split gate contact hole 62; the metal electrode layer 70 is electrically connected to the body region 51 via the source contact hole 61; the metal electrode layer 70 is electrically connected to the effective gate structure 30 via the gate contact hole 63.

Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application.

It should be understood that the steps described are not to be performed in the exact order recited, and that the steps may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps described may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least some of the sub-steps or stages of other steps.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor device structure, comprising:

providing a substrate;

forming a groove in the substrate;

2. The method for manufacturing a semiconductor device structure according to claim 1, wherein the base includes a substrate and an epitaxial layer stacked in this order from bottom to top; the trench is located within the epitaxial layer.

3. The method of claim 2, wherein forming a split-gate structure in the trench comprises:

4. The method for manufacturing a semiconductor device structure according to claim 3, further comprising, after the forming the dummy gate:

5. The method of claim 2, wherein after forming the split-gate structure in the trench, further comprising:

6. The method of claim 5, wherein forming the active gate structure on the surface of the split-gate structure comprises:

7. The method for fabricating the semiconductor device structure according to claim 5, further comprising, after forming the filling oxide layer:

8. A semiconductor device structure, comprising:

a substrate;

a trench in the substrate;

9. The semiconductor device structure of claim 8, wherein the base comprises a substrate and an epitaxial layer, the epitaxial layer being located on an upper surface of the substrate; the trench is located within the epitaxial layer.

10. The semiconductor device structure of claim 9, wherein the virtual split-gate structure comprises a virtual gate and a split gate oxide, the split gate oxide being located at the trench surface; the virtual grid is positioned on the surface of the split gate oxide layer; the lead-out part is positioned on the upper surface of the virtual grid.

11. The semiconductor device structure of claim 9, further comprising:

12. The semiconductor device structure of claim 11, wherein the active gate structure comprises an active gate electrode and an active gate oxide layer, the active gate oxide layer being located on an upper surface of the dummy split gate structure and on sidewalls of the trench and covering sidewalls of the lead-out portion; the effective grid electrode is positioned on the surface of the effective grid oxide layer and positioned on two sides of the filling oxide layer.

13. The semiconductor device structure of claim 11, further comprising: