CN114242715A - Bidirectional electrostatic discharge protection module - Google Patents

Bidirectional electrostatic discharge protection module Download PDF

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Publication number
CN114242715A
CN114242715A CN202111453942.1A CN202111453942A CN114242715A CN 114242715 A CN114242715 A CN 114242715A CN 202111453942 A CN202111453942 A CN 202111453942A CN 114242715 A CN114242715 A CN 114242715A
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transistor
diode
nmos transistor
protection module
pnp
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CN202111453942.1A
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CN114242715B (en
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郑飞君
王迪
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Hangzhou Aoxin Technology Co ltd
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Hangzhou Aoxin Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The invention discloses a bidirectional electrostatic discharge (ESD) protection module, which is integrated on a transceiver chip, wherein the transceiver chip is provided with at least one output end and a grounding end, and the bidirectional ESD protection module comprises at least one transistor and at least one diode; when the output end applies positive ESD stress, ESD current flows through at least one of the transistor and the diode from the output end to the grounding end to form a first current release path; when negative ESD stress is applied to the output end, ESD current flows from the grounding end to the output end through at least one of the transistor and the diode to form a second current release path; the transistor is a PNP triode or an NMOS transistor, and the diode is a parasitic body diode of the transistor or an external diode. According to the bidirectional ESD protection module provided by the invention, bidirectional ESD protection of a transceiver chip can be realized based on a common bipolar BCD process, the workload of PCB wiring layout is reduced, the PCB area is saved, the cost is reduced, and the bidirectional ESD protection module can be suitable for different voltage applications.

Description

Bidirectional electrostatic discharge protection module
Technical Field
The present invention relates to semiconductor technology, and more particularly to a bidirectional electrostatic discharge protection module.
Background
Smart car systems have intelligent sensing and control algorithms in vehicles for enabling communication between the vehicle and sensors to improve driving safety through collision warning and partial control of the vehicle. Due to the higher requirements of automotive applications on safety and reliability, intelligent automotive systems must have higher response speed and reliability. Controller Area network, CAN, (local Interconnect network) and local Interconnect network, LIN, (local Interconnect network) are common protocols used in the vehicle diagnostic standard (OBD) -II for connecting Electronic Control Units (ECUs), and both CAN and LIN buses must have ESD protection solutions to ensure reliability and safety of automotive electronics.
Fig. 1 shows a conventional ESD structure for protecting CAN and LIN buses, which uses a transient Voltage suppressor TVS (transient Voltage suppressor), but the performance of ESD protection depends on the PCB routing layout and the clamping Voltage of off-chip TVS devices, and in order to obtain the best ESD performance, the correct TVS device must be selected and a reasonable PCB layout must be performed, which requires more development time and larger PCB area, and additional cost is increased.
Furthermore, due to latch-up issues and fault voltage tolerance considerations, expensive high voltage soi (silicon On insulator) processes are required in the design of CAN and LIN transceiver chips.
Therefore, it is necessary to provide an on-chip TVS protection scheme to solve the problems in the prior art, and the off-chip TVS CAN be integrated into the CAN and LIN transceiver chips based on the common high-voltage bipolar BCD process, so as to reduce the workload of PCB routing layout, save the PCB area, and reduce the cost.
Disclosure of Invention
To overcome the deficiencies of the prior art, according to one aspect of the present invention, there is provided a bi-directional electrostatic discharge (ESD) protection module integrated on a transceiver chip having at least one output terminal and a ground terminal, the bi-directional ESD protection module comprising at least one transistor and at least one diode; when the output end applies positive ESD stress, ESD current flows through at least one of the transistor and the diode from the output end to the grounding end to form a first current release path; when negative ESD stress is applied to the output end, ESD current flows from the grounding end to the output end through at least one of the transistor and the diode to form a second current release path; the transistor is a PNP triode or an NMOS transistor, and the diode is a parasitic body diode of the transistor or an external diode.
Optionally, the transceiver chip is a CAN transceiver chip or a LIN transceiver chip.
Optionally, the transistor is a first PNP triode, an emitter of the transistor is connected to the output terminal, a collector of the transistor is connected to the ground terminal, and a base of the transistor is controlled by a first trigger circuit formed by a PMOS transistor; the drain electrode of the PMOS transistor is connected to the emitter electrode of the first PNP triode, the grid electrode of the PMOS transistor is connected to the grounding terminal, and the source electrode of the PMOS transistor is connected to the base electrode of the first PNP triode; when positive ESD stress is applied to the output end, the PMOS transistor is conducted to control the conduction of the first PNP triode, and ESD current flows from the output end through the first PNP triode to the ground end to form a first current release path; when negative ESD stress is applied to the output end, ESD current flows from the grounding end to the output end through the diode between the collector and the base of the first PNP triode, and a second current release path is formed.
Optionally, the bidirectional ESD protection module further includes a first diode string and a second diode string, wherein an anode of the first diode string is connected to the emitter of the first PNP triode, and a cathode of the first diode string is connected to the output terminal; the anode of the second diode string is connected to the output end, and the cathode of the second diode string is connected to the emitter of the first PNP triode.
Optionally, the at least one transistor includes a second PNP transistor and a third PNP transistor, wherein an emitter of the second PNP transistor is connected to the output terminal, a collector of the second PNP transistor is connected to a collector of the third PNP transistor, and a base of the second PNP transistor is connected to either one of the emitter or the collector of the second PNP transistor; the emitter of the third PNP triode is connected to the ground terminal, and the base of the third PNP triode is connected with any one of the emitter or the collector of the third PNP triode; the at least one diode includes two diodes connected between the source and base electrodes of the second PNP transistor and the third PNP transistor, respectively, or two diodes connected between the collector and base electrode.
Optionally, the base of the second PNP triode is connected to the collector, and the base of the third PNP triode is connected to the collector; and the two diodes are respectively connected between the source electrodes and the base electrodes of the second PNP triode and the third PNP triode.
Optionally, a base of the second PNP triode is connected to the emitter, and a base of the third PNP triode is connected to the emitter; the two diodes are respectively connected between the collector electrodes and the base electrodes of the second PNP triode and the third PNP triode; the bi-directional ESD protection module further includes a guard ring connected between ground and the P-type substrate, wherein the guard ring includes two anti-parallel connected diodes.
Optionally, the bidirectional ESD protection module further comprises a first diode string connected in the first current discharge path and a second diode string connected in the second current discharge path, wherein an anode of the first diode string is connected to an emitter of the second PNP diode, and a cathode is connected to the output terminal; the anode of the second diode string is connected to the output end, and the cathode of the second diode string is connected to the anode of the diode between the base electrode and the collector electrode of the second PNP triode.
Optionally, the bidirectional ESD protection module further comprises a PNP triode string connected between the output terminal and the second PNP triode emitter, and a PNP triode string connected between the third PNP triode emitter and the ground terminal, the base and emitter of each PNP triode in the PNP triode string being interconnected.
Optionally, the transceiver chip has a first floating rail and a second floating rail; at least one transistor is connected between the first floating rail and the second floating rail; the at least one diode comprises a first diode string and a second diode string which are externally connected, wherein the first diode string is connected between the output end and the first floating rail in a forward direction, and the second diode string is connected between the grounding end and the first floating rail in the forward direction.
Optionally, the at least one transistor is a fourth PNP transistor, an emitter of the fourth PNP transistor is connected to the base and to the first floating rail, and a collector of the fourth PNP transistor is connected to the second floating rail.
Optionally, the at least one transistor is a first NMOS transistor, a drain of the first NMOS transistor is connected to the first floating rail, a source of the first NMOS transistor is connected to the second floating rail, and a gate of the first NMOS transistor is controlled by the second trigger circuit.
Optionally, the second trigger circuit comprises: a second PMOS transistor, a first resistor and a first capacitor connected in series between the first floating rail and the second floating rail; the first end of the first resistor is connected with the first floating rail, the second end of the first resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the second floating rail, the grid electrode of the second PMOS transistor is connected to the common end of the first resistor and the first capacitor, the source electrode of the second PMOS transistor is connected to the first floating rail, and the drain electrode of the second PMOS transistor is connected to the second floating rail and the grid electrode of the first NMOS transistor.
Optionally, the second trigger circuit comprises: at least one zener diode connected in the forward direction between the gate of the first NMOS transistor and the first floating rail; and a resistor connected between the gate of the first NMOS transistor and the second floating rail.
Optionally, the at least one transistor is a fifth PNP triode, an emitter of the fifth PNP triode is connected to the first floating rail, a collector of the fifth PNP triode is connected to the second floating rail, and a base of the fifth PNP triode is controlled by the third trigger circuit; the third trigger circuit includes: a second NMOS transistor, at least one Zener diode forward connected between a gate of the second NMOS transistor and the first floating rail, and a resistor connected between an anode of the Zener diode and the second floating rail; the drain electrode of the second NMOS transistor is connected to the fifth PNP triode, the source electrode of the second NMOS transistor is connected to the second floating rail, and the grid electrode of the second NMOS transistor is connected to the anode of the Zener diode.
Optionally, the at least one transistor comprises a third NMOS transistor and a fourth NMOS transistor, wherein the third NMOS transistor has a drain connected to the output terminal, a gate connected to the body of the fourth NMOS transistor, and a source connected to the source of the fourth NMOS transistor; the grid electrode of the fourth NMOS transistor is connected with the body area of the third NMOS transistor, and the drain electrode of the fourth NMOS transistor is connected to the grounding end; the at least one diode includes two diodes or two sets of zener diode strings connected between the gates and drains of the third and fourth NMOS transistors, respectively.
Optionally, the at least one transistor comprises a third NMOS transistor and a fourth NMOS transistor, wherein the drain of the third NMOS transistor is connected to the output terminal, the gate is connected to the source and the body, and the source is connected to the source of the fourth NMOS transistor; the grid electrode of the fourth NMOS transistor is connected with the source electrode and the body region, and the drain electrode of the fourth NMOS transistor is connected with the grounding end.
Optionally, the third NMOS transistor and the fourth NMOS transistor share one P-channel.
Optionally, the bidirectional ESD protection module further comprises two capacitors respectively connected in parallel with the two diodes.
According to the bidirectional ESD protection module provided by the invention, bidirectional ESD protection of a transceiver chip can be realized based on a common bipolar BCD process, the workload of PCB wiring layout is reduced, the PCB area is saved, the cost is reduced, and the bidirectional ESD protection module can be suitable for different voltage applications.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings, in which:
fig. 1 is a conventional ESD structure for protecting CAN and LIN buses.
Fig. 2(a) is a circuit schematic diagram of a bidirectional esd protection module according to an embodiment of the invention.
Fig. 2(b) is a circuit diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 3(a) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 3(b) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 4(a) is a circuit schematic diagram of another bidirectional esd protection module according to an embodiment of the invention.
Fig. 4(b) is a cross-sectional view of the bi-directional esd protection module provided in the embodiment shown in fig. 4 (a).
Fig. 4(c) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 4(d) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 5(a) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 5(b) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 5(c) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 5(d) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 6(a) is a circuit schematic diagram of another bidirectional esd protection module according to an embodiment of the invention.
Fig. 6(b) is a circuit schematic diagram of another bidirectional esd protection module according to an embodiment of the invention.
Fig. 6(c) is a circuit schematic diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 7 is a circuit diagram of another bi-directional esd protection module according to an embodiment of the invention.
Fig. 8 is a cross-sectional view of a bi-directional esd protection module provided in the embodiment of fig. 7.
Detailed Description
The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of the present application, certain specific details are set forth in detail. It will be apparent to one skilled in the art that the present application may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present application.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present application, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present application, "a plurality" means two or more unless otherwise specified.
The invention provides a bidirectional electrostatic discharge (ESD) protection module integrated on a transceiver chip, the transceiver chip having at least one output terminal and a ground terminal, the bidirectional ESD protection module comprising at least one transistor and at least one diode; when the output end applies positive ESD stress, ESD current flows through at least one of the transistor and the diode from the output end to the grounding end to form a first current release path; when negative ESD stress is applied to the output end, ESD current flows from the grounding end to the output end through at least one of the transistor and the diode to form a second current release path; the transistor is a PNP triode or an NMOS transistor, and the diode is a parasitic body diode of the transistor or an external diode.
The transceiver chip may be, for example, a CAN transceiver chip, a LIN transceiver chip, etc., and the CAN chip will be described as an example.
As shown in fig. 2(a), the bidirectional electrostatic discharge (ESD) protection module according to an embodiment of the present invention is integrated on a CAN transceiver chip, and includes a first PNP transistor P1, an emitter of the first PNP transistor P1 is connected to a CANH or CANL pin of the CAN transceiver chip (i.e., an output terminal of the CAN transceiver chip), a collector is connected to a ground GND, and a base is controlled by a first trigger circuit formed by a pMOS transistor MP 1. The gate of the pMOS transistor MP1 is connected to the ground GND through a resistor, the drain is connected to the CANH or CANL pin of the CAN transceiver chip, and the source is connected to the base of the PNP transistor P1. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, the pMOS transistor is turned on, so that the base and emitter voltages of the first PNP transistor P1 are pulled high, the first PNP transistor P1 is turned on, and an ESD current flows from the CANH or CANL pin through the first PNP transistor to the ground terminal GND to form a first current discharge path for discharging the ESD current, as shown in path 1. In contrast, when a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground GND pin, the ESD current passes from the ground GND to the CANH or CANL pin through the parasitic diode D1 between the collector and the base of the first PNP transistor P1, forming a second current release path, as shown in path 2. Symmetric bidirectional ESD protection is achieved by adding pMOS transistors.
In an alternative embodiment, in order to adapt to different voltage applications and reduce the ESD capacitance of the high-speed CAN transceiver chip, a first diode string Dn1 (e.g., including a plurality of serially connected diodes Dna … … Dnx) and a second diode string Dp1 (e.g., including a plurality of serially connected diodes Dpa … … Dpx) may be added on the basis of the embodiment shown in fig. 2(a), wherein the first diode string Dn1 and the second diode string Dp1 are symmetrically arranged, as shown in fig. 2 (b). The anode of the first diode string Dn1 is connected to the source of the high voltage pMOS transistor MP1 and the emitter of the first PNP transistor P1, and the cathode is connected to the CANH or CANL pin of the CAN transceiver chip. The anode of the second diode string Dp1 is connected to the CANH or CANL pin of the CAN transceiver chip, and the cathode is connected to the emitter of the first PNP transistor P1. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, the pMOS transistor MP1 is turned on, so that the base and emitter voltages of the first PNP transistor P1 are pulled high, and an ESD current flows from the CANH or CANL pin through the second diode string Dp1 and the first PNP transistor P1 to the ground terminal GND to form a first current discharge path for discharging the ESD current, as shown in path 1. In contrast, when a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground GND pin, the ESD current flows from the ground GND to the CANH or CANL pin through the parasitic diode D1 between the collector and the base of the first PNP transistor P1 and the first diode string Dn1, forming a second current release path, as shown in path 2. Of course, it is understood by those skilled in the art that, on the basis of the embodiment shown in fig. 2(a), the first diode string Dn1 '(e.g., including a plurality of serially connected diodes Dn' … … Dnx ') and the second diode string Dp 1' (e.g., including a plurality of serially connected diodes Dpa '… … Dpx') may be connected between the anode and the ground of the parasitic diode D1 and the collector and the ground of the first PNP triode P1, respectively; alternatively, the first diode strings Dn1 and Dn1 'and the second diode strings Dp1 and Dp 1' may be added to the embodiment shown in fig. 2(a), which can also be used to adjust the voltage tolerance for different voltage applications.
As shown in fig. 3(a), another bidirectional electrostatic discharge (ESD) protection module 30 according to an embodiment of the present invention includes a second PNP transistor P2 and a third PNP transistor P3. The emitter of the second PNP triode P2 is connected to the CANH or CANL pin of the CAN transceiver chip, the base is interconnected with the collector, the collector is connected with the collector of the third PNP triode P3, the base of the third PNP triode P3 is interconnected with the collector, and the emitter is connected to the ground GND. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground terminal GND, the ESD current is discharged from the CANH or CANL pin to the ground terminal GND through the body diode D2 between the emitter and the base of the second PNP transistor P2 and the third high-voltage PNP transistor P3, forming a first current discharge path, as shown in path 1. When a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground terminal GND, the ESD current flows from the ground terminal GND through the body diode D3 of the third PNP transistor P3 and the second high-voltage PNP transistor P2 to the CANH or CANL pin of the CAN transceiver chip, forming a second current release path, as shown in path 2. By stacking two high voltage PNP transistors with interconnected base and collector, a current release path of "one diode plus one PNP transistor" can be formed and symmetric bidirectional ESD protection is formed when ESD positive and negative stresses are applied.
In an alternative embodiment, in order to adapt to different voltage applications, a first diode string Dn1 (e.g., including a plurality of diodes Dn … … Dnx connected in series) and a second diode string Dp1 (e.g., including a plurality of diodes Dpa … … Dpx connected in series) may be added on the basis of the embodiment shown in fig. 3 (a); alternatively, a first diode string Dn1 '(e.g., comprising a plurality of series-connected diodes Dna' … … Dnx ') and a second diode string Dp 1' (e.g., comprising a plurality of series-connected diodes Dpa '… … Dpx') are added; alternatively, the first diode strings Dn1 and Dn 'and the second diode string Dp1 and the second diode string Dp 1' are added at the same time, as shown in fig. 3 (b). The anode of the first diode string Dn1 is connected to the emitter of the second PNP transistor P2 in the ESD protection circuit shown in fig. 3(a), and the cathode is connected to the CANH or CANL pin of the CAN transceiver chip. The anode of the second diode string Dp1 is connected to the CANH or CANL pin of the CAN transceiver chip and the cathode is connected to the emitter of the second PNP triode P2. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current is discharged from the CANH or CANL pin to the ground terminal GND through the second diode string Dp1 and the ESD protection circuit 30 shown in fig. 3 (a). In contrast, when a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground GND pin, an ESD current flows from the ground GND through the ESD protection circuit 30 and the first diode string Dn1 shown in fig. 3(a) to the CANH or CANL pin. Thus, by simply superimposing the diode strings, the ESD protection module can be made suitable for wide voltage applications. In another alternative embodiment, a base-to-emitter interconnected PNP transistor may be used in place of the diode in fig. 3(b), by stacking multiple such PNP transistors to form transistor strings PS1 and PS 1' connected to the emitter of PNP transistor P2 and CANH/CANL terminal, respectively, and the emitter of PNP transistor P3 and ground terminal, to accommodate different voltage applications while forming symmetric bidirectional ESD protection.
As shown in fig. 4(a), another bidirectional electrostatic discharge (ESD) protection module 40 according to an embodiment of the present invention includes a second PNP transistor P2 'and a third PNP transistor P3'. The emitter of the second PNP triode P2 is connected to the CANH or CANL pin of the CAN transceiver chip, the base is interconnected with the emitter, the collector is connected with the collector of the third PNP triode P3', the base of the second PNP triode P2' is interconnected with the emitter thereof, and the emitter is connected to the ground GND. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground terminal GND, the ESD current is discharged from the CANH or CANL pin to the ground terminal GND through the parasitic body diode D3' between the collector and the base of the second PNP transistor P2' and the third PNP transistor P3', forming a first current discharge path, as shown in path 1. When a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground terminal GND, the ESD current flows from the ground terminal GND through the third PNP transistor P3' and the parasitic body diode D2' between the collector and the base of the second PNP transistor P2' to the CANH or CANL pin of the CAN transceiver chip, forming a second current release path, as shown in path 2. By stacking two high voltage PNP transistors with their bases and emitters interconnected, a current release path of "one PNP transistor plus one diode" can be formed and symmetric bidirectional ESD protection is formed when ESD positive and negative stresses are applied. In addition, in the present embodiment, a guard ring structure is further provided between the ground GND and the P-type substrate for preventing a parasitic latch-up path, specifically, the guard ring structure includes two diodes Dg1 and Dg2 connected in reverse parallel, wherein an anode of the diode Dg1 is connected to the ground GND, a cathode of the diode Dg 3526 is connected to the P-type substrate P-sub, an anode of the diode Dg2 is connected to the P-type substrate P-sub, and a cathode of the diode is connected to the ground GND, and a cross section of the bidirectional ESD protection module is shown in fig. 4 (b).
In an alternative embodiment, in order to adapt to different voltage applications, a first diode string Dn1 (e.g., including a plurality of diodes Dn … … Dnx connected in series) and a second diode string Dp1 (e.g., including a plurality of diodes Dpa … … Dpx connected in series) may be added on the basis of the embodiment shown in fig. 4 (a); alternatively, a first diode string Dn1 '(e.g., comprising a plurality of series-connected diodes Dna' … … Dnx ') and a second diode string Dp 1' (e.g., comprising a plurality of series-connected diodes Dpa '… … Dpx') are added; alternatively, the first diode strings Dn1 and Dn 'and the second diode string Dp1 and the second diode string Dp 1' are added at the same time, as shown in fig. 4 (c). The anode of the first diode string Dn1 is connected to the emitter of the second PNP transistor P2 in the ESD protection circuit shown in fig. 4(a), and the cathode is connected to the CANH or CANL pin of the CAN transceiver chip. The anode of the second diode string Dp1 is connected to the CANH or CANL pin of the CAN transceiver chip and the cathode is connected to the emitter of the second PNP triode P4. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current is discharged from the CANH or CANL pin to the ground terminal GND through the second diode string Dp1 and the ESD protection circuit 40. In contrast, when a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground GND pin, an ESD current flows from the ground GND through the ESD protection circuit 40 and the first diode string Dn1 to the CANH or CANL pin. Thus, by simply superimposing the diode strings, the ESD protection module can be adapted to wide voltage applications. In another alternative embodiment, shown in fig. 4(d), base and emitter interconnected PNP transistors may be used in place of the diodes in fig. 4(c), to accommodate different voltage applications by stacking a plurality of such PNP transistors to form a transistor string, while forming symmetrical bi-directional ESD protection.
As shown in fig. 5(a), another bidirectional electrostatic discharge (ESD) protection module according to an embodiment of the present invention includes a fourth PNP transistor P4 connected between floating rails PS _ ESD and NS _ ESD, a diode string Dn2 and a diode string Dp2 connected in a forward direction between a CANH or CANL pin of a CAN transceiver chip and the floating rail PS _ ESD, and a second diode string Dn7 'and a diode string Dp 7' connected in a forward direction between the floating rail NS _ ESD and the CANH or CANL pin of the CAN transceiver chip. Specifically, the emitter of the fourth PNP transistor P4 is connected to the floating rail PS _ ESD, the base and emitter are interconnected, and the collector is connected to the floating rail NS _ ESD. When a forward ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current flows from the CANH or CANL pin through the diode string Dn2 to the floating rail PS _ ESD, then through the fourth PNP transistor P4 to the floating rail NS _ ESD, and then through the diode string Dn 2' to the ground terminal GND, forming a first current discharge path, as shown in path 1. When a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, the ESD current flows from the ground terminal GND through the diode string Dp2 to the floating rail PS _ ESD, then through the fourth PNP transistor P4 to the floating rail NS _ ESD, and then through the diode string Dp2' to the CANH or CANL pin, forming a second current release path, as shown in path 2.
In an alternative embodiment, as shown in fig. 5(b), the fourth PNP transistor in fig. 5(a) can be replaced with an RC triggered large FET, resulting in a lower trigger voltage (VT1) during an ESD event, resulting in better protection performance. Specifically, the fourth PNP transistor is replaced by a first NMOS transistor MN1, the drain of the first NMOS transistor MN1 is connected to the first floating rail, the source is connected to the second floating rail, and the gate is controlled by the second trigger circuit. The second trigger circuit includes: a second PMOS transistor MP2, a first resistor R1 and a first capacitor C1 connected in series between the first floating rail PS _ ESD and the second floating rail NS _ ESD; a first end of the first resistor R1 is connected to the first floating rail PS _ ESD, a second end is connected to the first end of the first capacitor C1, a second end of the first capacitor C1 is connected to the second floating rail NS _ ESD, a gate of the second PMOS transistor MP2 is connected to a common end of the first resistor R1 and the first capacitor C1, a drain is connected to the first floating rail PS _ ESD, and a source is connected to the second floating rail NS _ ESD and a gate of the first NMOS transistor MN 1. When a forward ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current flows from the CANH or CANL pin through the diode string Dn2 to the floating rail PS _ ESD, then is connected to the floating rail NS _ ESD through the first NMOS transistor MN1, and then flows to the ground terminal GND through the diode string Dn 2', forming a first current release path, as shown in path 1. When a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, the ESD current flows from the ground terminal GND through the diode string Dp2 to the floating rail PS _ ESD, then through the first NMOS transistor MN1 to the floating rail NS _ ESD, and then through the diode string Dp2' to the CANH or CANL pin, forming a second current release path, as shown in path 2.
In another alternative embodiment, as shown in fig. 5(c), the second trigger circuit may include at least one zener diode, so that during normal operation, false triggering due to pin noise or fast transient events can be avoided. Specifically, the anode of the zener diode string Z1 is connected to the gate of the first NMOS transistor MN1, and the cathode is connected to the first floating rail PS _ ESD.
In an alternative embodiment, shown in fig. 5(d), the operating principle is similar to that of fig. 5(a), except that the zener diode triggers the transistor PNP, resulting in a lower trigger voltage (VT1) during an ESD event, resulting in better protection. Specifically, in the embodiment shown in fig. 5(d), the ESD protection module includes a fifth PNP transistor P5, an emitter of the fifth PNP transistor P5 is connected to the first floating rail PS _ ESD, a collector is connected to the second floating rail, and a base is controlled by the third trigger circuit; the third trigger circuit includes: a second NMOS transistor MN2, at least one zener diode connected in a forward direction between the gate of the second NMOS transistor MN2 and the first floating rail PS _ ESD, and a resistor connected between an anode of the zener diode and the second floating rail NS _ ESD; the drain of the second NMOS transistor MN2 is connected to the fifth PNP transistor P5, the source is connected to the second floating rail NS _ ESD, and the gate is connected to the anode of the zener diode.
As shown in fig. 6(a), another bidirectional electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4, wherein the drain of the third NMOS transistor MN3 is connected to a CANH or CANL pin of a CAN transceiver chip, the gate is connected to the body of the fourth NMOS transistor MN4, the source is connected to the source of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 is connected to the body of the third NMOS transistor MN3, and the drain is connected to the ground GND. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current flows from the CANH or CANL pin to the ground terminal GND through the parasitic body diode D5 between the gates and drains of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, forming a first current discharge path, as shown in path 1. When a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, the ESD current flows from the ground terminal GND through the fourth NMOS transistor MN4 and the parasitic body diode D4 between the gate and the drain of the third NMOS transistor MN3 to the CANH or CANL pin, forming a second current release path, as shown in path 2. Thus, by stacking two NMOS transistors and connecting their gates and body regions together, symmetric bi-directional ESD protection is formed.
In an alternative embodiment, as shown in fig. 6(b), zener diode strings DzS1 and DzS1' are used in place of body diodes D4 and D5, respectively, to adjust for different trigger voltages during an ESD event. In addition, in another alternative embodiment, the trigger voltage of the present invention can be further reduced by simply adding capacitors C1 and C2 connected in parallel with the body diodes D4 and D5, respectively, as shown in fig. 6 (C).
As shown in fig. 7, another bidirectional electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention includes a third NMOS transistor MN 3' and a fourth NMOS transistor MN4', wherein the drain of the third NMOS transistor MN 3' is connected to the CANH or CANL pin of the CAN transceiver chip, the gate is connected to the source and the body, and the source is connected to the source of the fourth NMOS transistor MN4', the gate of the fourth NMOS transistor MN4' is connected to the source and the body, and the drain is connected to the ground GND. When a positive ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current flows from the CANH or CANL pin to the ground terminal GND through the parasitic body diodes of the third and fourth NMOS transistors MN3 'and MN 4'. When a negative ESD stress is applied to the CANH or CANL pin of the CAN transceiver chip with respect to the ground pin GND, an ESD current flows from the ground terminal GND through parasitic body diodes of the fourth NMOS transistor MN4 'and the third NMOS transistor MN 3' to the CANH or CANL pin. Thus, by stacking two NMOS transistors with interconnected gate, source, and body regions, symmetric bi-directional ESD protection is formed. It should be noted that the third NMOS transistor and the fourth NMOS transistor share one P channel, as shown in fig. 8, so as to save the area of the ESD protection module, further reduce the chip area, and reduce the cost.
In the above example, the pMOS transistor may select a low voltage transistor, a normal transistor, or a high voltage transistor according to the actual application; the diode string can also be replaced by a triode string; the parasitic body diode can be replaced by an external diode to achieve the same function.
The above embodiments have been described only by taking the CAN transceiver chip as an example, and those skilled in the art will know that the same technical solution CAN also be applied to the LIN transceiver chip to realize bidirectional ESD protection. In addition, the technical scheme of the invention can be realized by a common high-voltage BCD process without an additional mask, and the used devices are common PNP triodes, diodes, NMOS transistors and PMOS transistors. The invention can be used for meeting the ESD requirements of a chip-level (human Body model) HBM (human Body model), a Charging Device Model (CDM) and a system level (IEC-61000-4-2).
The embodiments in the above description can be further combined or replaced, and the embodiments are only described as preferred examples of the present invention, and do not limit the concept and scope of the present invention, and various changes and modifications made to the technical solution of the present invention by those skilled in the art without departing from the design concept of the present invention belong to the protection scope of the present invention. The scope of the invention is given by the appended claims and any equivalents thereof.

Claims (19)

1. A bi-directional electrostatic discharge (ESD) protection module integrated on a transceiver chip having at least one output terminal and a ground terminal, the bi-directional ESD protection module comprising at least one transistor and at least one diode;
when the output end applies positive ESD stress, the ESD current flows from the output end to the grounding end through at least one of the transistor and the diode, and a first current release path is formed;
when negative ESD stress is applied to the output end, the ESD current flows from the grounding end to the output end through at least one of the transistor and the diode to form a second current release path;
the transistor is a PNP triode or an NMOS transistor, and the diode is a parasitic body diode or an external diode of the transistor.
2. The bi-directional ESD protection module of claim 1, wherein the transceiver chip is a CAN transceiver chip or a LIN transceiver chip.
3. The bi-directional ESD protection module of claim 1, wherein the transistor is a first PNP transistor having an emitter connected to the output terminal, a collector connected to the ground terminal, and a base controlled by a first trigger circuit comprising a PMOS transistor; the drain electrode of the PMOS transistor is connected to the emitter electrode of the first PNP triode, the grid electrode of the PMOS transistor is connected to the grounding terminal, and the source electrode of the PMOS transistor is connected to the base electrode of the first PNP triode;
when positive ESD stress is applied to the output end, the PMOS transistor is conducted to control the conduction of a first PNP triode, and the ESD current flows from the output end to the grounding end through the first PNP triode to form a first current release path;
when negative ESD stress is applied to the output end, the ESD current flows from the grounding end to the output end through a diode between the collector and the base of the first PNP triode to form the second current release path.
4. The bi-directional ESD protection module of claim 3, further comprising a first diode string and a second diode string, wherein an anode of the first diode string is connected to the emitter of the first PNP triode and a cathode is connected to the output terminal; the anode of the second diode string is connected to the output end, and the cathode of the second diode string is connected to the emitter of the first PNP triode.
5. The bi-directional ESD protection module of claim 1, wherein the at least one transistor includes a second PNP transistor and a third PNP transistor, wherein,
the emitter of the second PNP triode is connected to the output end, the collector of the second PNP triode is connected to the collector of the third PNP triode, and the base of the second PNP triode is connected with any one of the emitter or the collector of the second PNP triode;
the emitter of the third PNP triode is connected to the grounding terminal, and the base of the third PNP triode is connected with any one of the emitter or the collector of the third PNP triode;
the at least one diode includes two diodes respectively connected between the source and base electrodes of the second PNP transistor and the third PNP transistor or two diodes between the collector and base electrodes.
6. The bi-directional ESD protection module of claim 5, wherein the base of the second PNP transistor is connected to the collector, and the base of the third PNP transistor is connected to the collector; the two diodes are respectively connected between the source electrodes and the base electrodes of the second PNP triode and the third PNP triode.
7. The bi-directional ESD protection module of claim 5,
the base electrode of the second PNP triode is connected with the emitting electrode, and the base electrode of the third PNP triode is connected with the emitting electrode;
the two diodes are respectively connected between the collector electrodes and the base electrodes of the second PNP triode and the third PNP triode;
the bidirectional ESD protection module further comprises a guard ring connected between the ground terminal and the P-type substrate, wherein the guard ring comprises two diodes connected in anti-parallel.
8. The bi-directional ESD protection module of claim 6, further comprising a first diode string connected in a first current discharge path and a second diode string connected in a second current discharge path, wherein an anode of the first diode string is connected to an emitter of the second PNP diode and a cathode is connected to the output terminal; the anode of the second diode string is connected to the output end, and the cathode of the second diode string is connected to the anode of the diode between the base electrode and the collector electrode of the second PNP triode.
9. The bi-directional ESD protection module of claim 5,
the bidirectional ESD protection module further comprises a PNP triode string connected between the output end and the second PNP triode emitter, and a PNP triode string connected between the third PNP triode emitter and the ground terminal, wherein the base and the emitter of each PNP triode in the PNP triode string are connected with each other.
10. The bi-directional ESD protection module of claim 1, wherein the transceiver chip has a first floating rail and a second floating rail;
the at least one transistor is connected between the first floating rail and the second floating rail;
the at least one diode includes a first diode string and a second diode string connected externally, wherein the first diode string is connected between the output terminal and the first floating rail in a forward direction, and the second diode string is connected between the ground terminal and the first floating rail in the forward direction.
11. The bi-directional ESD protection module of claim 10, wherein the at least one transistor is a fourth PNP transistor having an emitter connected to the base and connected to the first floating rail and a collector connected to the second floating rail.
12. The bi-directional ESD protection module of claim 10,
the at least one transistor is a first NMOS transistor, the drain of the first NMOS transistor is connected to the first floating rail, the source of the first NMOS transistor is connected to the second floating rail, and the grid of the first NMOS transistor is controlled by a second trigger circuit.
13. The bi-directional ESD protection module of claim 12, wherein the second trigger circuit comprises: a second PMOS transistor, a first resistor and a first capacitor connected in series between the first floating rail and the second floating rail; the first end of the first resistor is connected with the first floating rail, the second end of the first resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the second floating rail, the grid electrode of the second PMOS transistor is connected to the common end of the first resistor and the first capacitor, the source electrode of the second PMOS transistor is connected to the first floating rail, and the drain electrode of the second PMOS transistor is connected to the second floating rail and the grid electrode of the first NMOS transistor.
14. The bi-directional ESD protection module of claim 12, wherein the second trigger circuit comprises: at least one zener diode connected in the forward direction between the gate of the first NMOS transistor and the first floating rail; and a resistor connected between the gate of the first NMOS transistor and the second floating rail.
15. The bi-directional ESD protection module of claim 10, wherein the at least one transistor is a fifth PNP transistor, an emitter of the fifth PNP transistor is connected to the first floating rail, a collector of the fifth PNP transistor is connected to the second floating rail, and a base of the fifth PNP transistor is controlled by a third triggering circuit; the third trigger circuit includes: a second NMOS transistor, at least one Zener diode connected in a forward direction between a gate of the second NMOS transistor and the first floating rail, and a resistor connected between an anode of the Zener diode and the second floating rail; the drain electrode of the second NMOS transistor is connected to the fifth PNP triode, the source electrode of the second NMOS transistor is connected to the second floating rail, and the grid electrode of the second NMOS transistor is connected to the anode of the Zener diode.
16. The bi-directional ESD protection module of claim 1, wherein the at least one transistor includes a third NMOS transistor and a fourth NMOS transistor, wherein,
the drain electrode of the third NMOS transistor is connected to the output end, the grid electrode of the third NMOS transistor is connected with the body area of the fourth NMOS transistor, and the source electrode of the third NMOS transistor is connected to the source electrode of the fourth NMOS transistor;
the grid electrode of the fourth NMOS transistor is connected with the body region of the third NMOS transistor, and the drain electrode of the fourth NMOS transistor is connected to the grounding end;
the at least one diode comprises two diodes or two groups of zener diode strings connected between the gates and drains of the third and fourth NMOS transistors, respectively.
17. The bi-directional ESD protection module of claim 1, wherein the at least one transistor includes a third NMOS transistor and a fourth NMOS transistor, wherein,
the drain electrode of the third NMOS transistor is connected to the output end, the grid electrode of the third NMOS transistor is connected with the source electrode and the body region, and the source electrode of the third NMOS transistor is connected to the source electrode of the fourth NMOS transistor;
and the grid electrode of the fourth NMOS transistor is connected with the source electrode and the body region, and the drain electrode of the fourth NMOS transistor is connected with the grounding end.
18. The bi-directional ESD protection module of claim 18, wherein the third NMOS transistor and the fourth NMOS transistor share a P-channel.
19. The bi-directional ESD protection module of claim 16, further comprising two capacitors connected in parallel with the two diodes, respectively.
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