CN114242663A - IGBT low-stress packaging structure and preparation method - Google Patents

IGBT low-stress packaging structure and preparation method Download PDF

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Publication number
CN114242663A
CN114242663A CN202111500130.8A CN202111500130A CN114242663A CN 114242663 A CN114242663 A CN 114242663A CN 202111500130 A CN202111500130 A CN 202111500130A CN 114242663 A CN114242663 A CN 114242663A
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China
Prior art keywords
metal layer
insulating substrate
base plate
insulating
upper metal
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CN202111500130.8A
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Chinese (zh)
Inventor
赵成
王毅
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Yangzhou Yangjie Electronic Co Ltd
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Yangzhou Yangjie Electronic Co Ltd
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Priority to CN202111500130.8A priority Critical patent/CN114242663A/en
Publication of CN114242663A publication Critical patent/CN114242663A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

An IGBT low stress packaging structure and a preparation method. The IGBT low-stress packaging structure and the preparation method thereof are convenient to release the thermal stress or the mechanical stress, and avoid the integral warping or breaking of the insulating substrate and the deterioration and failure of the device performance caused by the action of the chip and the chip solder layer. The chip comprises a base plate, an insulating substrate base plate and a chip which are sequentially overlapped from bottom to top; the insulating substrate base plate comprises an upper metal layer, an insulating substrate and a lower metal layer which are sequentially bonded; the insulating substrate comprises a plurality of insulating substrates, and the insulating substrates are in a regular cross structure and are combined in a staggered mode. The sides of the insulating substrate are equal in length. The adjacent side surfaces of the insulating substrates are mutually attached. The invention avoids the deterioration and failure of the device performance caused by the action of the stress on the chip and the chip solder layer, and can be applied to large-size and high-power IGBT devices or power modules.

Description

IGBT low-stress packaging structure and preparation method
Technical Field
The invention relates to the technical field of power electronic devices, in particular to an IGBT low-stress packaging structure and a preparation method thereof.
Background
IGBT (insulated gate bipolar transistor) power devices are used in a wide range of fields from inverters of hybrid vehicles to power converters of wind power generators, and are developed from conventional IGBT power devices into IGBT power modules or IGBT smart power modules with increasing application demands. In the packaging structure of the IGBT device or power module, an insulating substrate is usually used for electrical isolation between the silicon chip and the substrate, and between the silicon chip and the heat dissipation layer, and different insulating substrate materials and manufacturing techniques are used for the packaging structure of the IGBT device power module according to the performance requirements of different devices or power modules.
The strain generated in the insulating substrate due to the temperature change in the bonding process and the stress generated in the packaging structure by the power cycle during application can cause the insulating substrate to warp or even break, and act on the chip and the chip solder layer to cause the performance degradation or even failure of the device. The substrate size of the Direct Bonding Copper (DBC) insulating substrate containing the insulating substrate in the prior art is small, and the substrate is only suitable for a low-power IGBT device or a power module. The large-size insulating substrate base plate required by the high-power IGBT device or the power module generally adopts an Insulating Metal Substrate (IMS) technology, and the insulating substrate of the high-power IGBT device or the power module adopts a polymer material, so that the defects that the thermal conductivity and the heat conductivity of the polymer material are low, and the problems of capacitive crosstalk and the like related to a thin polymer layer exist.
Disclosure of Invention
Aiming at the problems, the invention provides the IGBT low-stress packaging structure and the preparation method, which are convenient for releasing the thermal stress or the mechanical stress, and can avoid the integral warping or breaking of the insulating substrate and the deterioration and failure of the device performance caused by the action on the chip and the chip solder layer.
The technical scheme of the invention is as follows:
an IGBT low stress packaging structure comprises a substrate, an insulating substrate and a chip which are sequentially overlapped from bottom to top; the insulating substrate base plate comprises an upper metal layer, an insulating substrate and a lower metal layer which are sequentially bonded;
the insulating substrate comprises a plurality of insulating substrates, and the insulating substrates are in a regular cross structure and are combined in a staggered mode.
The sides of the insulating substrate are equal in length.
The adjacent side surfaces of the insulating substrates are mutually attached.
The thickness of a plurality of the insulating substrates is equal.
The top surfaces and the bottom surfaces of a plurality of the insulating substrates which are combined in a staggered mode are in the same plane respectively.
The upper metal layer and the lower metal layer are rectangular metal foils respectively.
The upper metal layer and the lower metal layer are respectively circular metal foils.
The upper metal layer is aligned with the lower metal layer.
A preparation method of an IGBT low-stress packaging structure comprises the following steps:
1) preparation of insulating substrate
1.1) preparing a plurality of insulating substrates in a right cross shape;
1.2) respectively generating thin oxide films on the bottom surface of the upper metal layer and the top surface of the lower metal layer;
1.3) all the insulating substrates are arranged on the top surface of the lower metal layer and are laterally staggered and attached;
1.4) covering an upper metal layer, enabling the bottom surface of the upper metal layer to be attached to the top surface of each insulating substrate, and enabling the edges of the upper metal layer and the lower metal layer to be aligned up and down;
1.5) putting the assembly obtained in the step 1.4) into a reaction furnace, heating to 1066-1078 ℃, keeping for 45-60 min, and gradually cooling to room temperature;
1.6) cutting off the part which protrudes out of the upper metal layer and the lower metal layer to obtain an insulating substrate base plate with a rectangular or circular structure;
2) bonding the chip with the metalized back surface on the top surface of the insulating substrate base plate in the step 1.6) through a chip solder layer;
3) and (3) bonding the bottom surface of the insulating substrate base plate after the step 2) on the top surface of the base plate through the insulating substrate base plate solder layer to finish the preparation of the packaging structure.
The invention relates to an IGBT low stress packaging structure, which comprises a base plate, an insulating substrate base plate solder layer, an insulating substrate base plate, a chip solder layer and a chip which are sequentially overlapped from bottom to top, wherein the insulating substrate is formed by transversely and alternately laminating a plurality of cross insulating substrates, so that an insulating substrate with a larger size is formed, the upper top surface and the lower bottom surface of the insulating substrate are respectively bonded with an upper metal layer and a lower metal layer to form the insulating substrate base plate with the larger size, the insulating substrate base plate is bonded with the base plate through the insulating substrate base plate solder layer, and the chip is bonded with the insulating substrate base plate through the chip solder layer.
The side surfaces of the substrates in the insulating substrate base plate are only tightly attached but not fixedly connected with each other, when the IGBT power module bears larger heat load and power load, compared with a single large-size insulating substrate base plate, the composite large-size insulating substrate base plate comprises a structure formed by transversely and alternately attaching a plurality of cross-shaped insulating substrates, the structure can effectively release stress generated in the insulating substrate due to the heat load and the power load, avoids the substrate warpage or fracture existing in the single large-size insulating substrate base plate, avoids the performance deterioration and failure of the device due to the action of the stress on the chip and a chip solder layer, and can be applied to large-size and large-power IGBT devices or power modules.
Drawings
Figure 1 is a general structural schematic diagram of the package structure of the present invention,
figure 2 is a front view of the insulating substrate structure of the present invention,
FIG. 3 is a schematic diagram showing the positional relationship between the upper metal layer and the insulating substrate in the square insulating substrate base plate of the present invention,
figure 4 is a front view of a square insulating substrate base plate structure of the present invention,
figure 5 is a side view of a square insulating substrate base plate structure of the present invention,
FIG. 6 is a schematic diagram showing the positional relationship between the upper metal layer and the insulating substrate in the rectangular insulating substrate base plate of the present invention,
figure 7 is a front view of a rectangular dielectric substrate base plate structure of the present invention,
figure 8 is a side view of a rectangular insulating substrate base plate structure of the present invention,
FIG. 9 is a schematic diagram showing the positional relationship between the upper metal layer and the insulating substrate in the circular insulating substrate base plate of the present invention,
figure 10 is a front view of a circular insulating substrate base plate structure of the present invention,
FIG. 11 is a side view of a circular insulating substrate base plate structure of the present invention;
in the figure, 1 is a base plate, 2 is an insulating substrate base plate, 21 is an upper metal layer, 22 is an insulating substrate, 221 is an insulating substrate, 23 is a lower metal layer, 3 is an insulating substrate base plate solder layer, 4 is a chip solder layer, and 5 is a chip.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
As shown in fig. 1-11, the invention relates to an IGBT low stress package structure, which comprises a base plate 1, an insulating substrate base plate 2 and a chip 5, which are sequentially overlapped from bottom to top; the insulating substrate base plate 2 comprises an upper metal layer 21, an insulating substrate 22 and a lower metal layer 23 which are sequentially bonded; that is, the upper top surface of each insulating substrate 221 is bonded to the lower bottom surface of the upper metal layer 21, and the lower bottom surface of each insulating substrate 221 is bonded to the upper top surface of the lower metal layer 23;
the insulating substrate 22 includes a plurality of insulating substrates 221, and the plurality of insulating substrates 221 are respectively in a regular cross shape structure and are combined in a staggered manner.
In this case, the insulating substrate 2 is made of silicon oxide or aluminum nitride, and the upper metal layer 21, the lower metal layer 23, and the substrate 1 are made of copper.
Further preferably, the sides of the insulating substrate 221 in the shape of a regular cross are equal in length.
Preferably, the adjacent sides of the interlaced insulating substrates 221 are attached to each other to form a large-sized insulating substrate 22.
Preferably, the thickness of the insulating substrates 221 is equal.
Preferably, the top surfaces and the bottom surfaces of the plurality of insulating substrates 221 combined in a staggered manner are in the same plane, i.e., the top surfaces are flush with each other, and the bottom surfaces are flush with each other.
Further expanding, the upper metal layer 21 and the lower metal layer 23 are rectangular metal foils, respectively, that is, the upper metal layer 21 and the lower metal layer 23 are square metal foils or rectangular metal foils with the same shape and size, and are bonded with a rectangular insulating substrate to obtain a universal rectangular insulating substrate.
Further expanding, the upper metal layer 21 and the lower metal layer 23 are respectively circular metal foils, and are bonded with a circular insulating substrate to obtain a universal circular insulating base plate.
Further preferably, the upper metal layer 21 and the lower metal layer 23 are vertically symmetrical.
Further preferably, the insulating substrate bonded to the upper metal layer 21 and the lower metal layer 23 is cut to be flush with the outer edges of the upper metal layer 21 and the lower metal layer 23.
A preparation method of an IGBT low-stress packaging structure comprises the following steps:
1) preparation of insulating substrate
1.1) preparing a plurality of insulating substrates 221 in a right cross shape;
1.2) respectively generating thin oxide films on the bottom surface of the upper metal layer 21 and the top surface of the lower metal layer 23;
1.3) each insulating substrate 221 is arranged on the top surface of the lower metal layer 23 and is laterally staggered and attached;
1.4) covering an upper metal layer 21, enabling the bottom surface of the upper metal layer to be attached to the top surface of each insulating substrate, and enabling the edges of the upper metal layer 21 and the lower metal layer 23 to be aligned up and down;
1.5) putting the assembly obtained in the step 1.4) into a reaction furnace, heating to 1066-1078 ℃, keeping for 45-60 min, and gradually cooling to room temperature;
1.6) cutting off the parts which protrude out of the upper metal layer 21 and the lower metal layer 23 to obtain an insulating substrate base plate with a rectangular or circular structure;
2) bonding the chip 5 with the metallized back surface on the top surface of the insulating substrate base plate in the step 1.6) through a chip solder layer 4;
3) bonding the bottom surface of the insulating substrate base plate in the assembly after the step 2) is finished on the top surface of the base plate 1 through the insulating substrate base plate solder layer 3.
The invention adopts a plurality of insulating substrates 221 in the shape of a regular cross to form the insulating substrate 22 in a large size in a transverse staggered joint way, and the side surfaces of the substrates are only tightly jointed but not fixedly connected with each other, so when the IGBT power module bears a larger thermal load and a power load, compared with a single large-size insulating substrate, the composite large-size insulating substrate comprises a structure formed by the transverse staggered joint of the insulating substrates 221 in the shape of the regular cross, which can effectively release the stress generated in the insulating substrate due to the thermal load and the power load, avoid the substrate warpage or fracture existing in the single large-size insulating substrate, and avoid the performance deterioration and even failure of the device caused by the action of the stress on the chip 5 and the chip solder layer 4.
In the invention, a plurality of right cross-shaped insulating substrates 221 are transversely and alternately jointed to form an insulating substrate 22 with a larger size, the side surfaces of the substrates are mutually jointed, and after the insulating substrate is bonded with an upper metal layer 21 and a lower metal layer 23, the insulating substrate is compressed at normal temperature and mutually meshed due to the friction force between the side surfaces of the substrates because of the high thermal expansion coefficient of the copper material which is conventionally used as the upper metal layer and the lower metal layer, so that the mechanical strength of the insulating substrate and the insulating substrate base plate 2 can be increased.
The low-stress packaging structure can be applied to large-size and high-power IGBT devices or power modules.
The disclosure of the present application also includes the following points:
(1) the drawings of the embodiments disclosed herein only relate to the structures related to the embodiments disclosed herein, and other structures can refer to general designs;
(2) in case of conflict, the embodiments and features of the embodiments disclosed in this application can be combined with each other to arrive at new embodiments;
the above embodiments are only embodiments disclosed in the present disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the scope of the claims.

Claims (9)

1. An IGBT low stress packaging structure comprises a substrate, an insulating substrate and a chip which are sequentially overlapped from bottom to top; the insulating substrate base plate comprises an upper metal layer, an insulating substrate and a lower metal layer which are sequentially bonded;
the insulating substrate comprises a plurality of insulating substrates, and the insulating substrates are in a regular cross structure and are combined in a staggered mode.
2. The IGBT low stress package structure of claim 1, wherein the sides of the insulating substrate are equal in length.
3. The IGBT low stress package structure of claim 1, wherein adjacent sides of the insulating substrates are attached to each other.
4. The IGBT low stress package structure of claim 1, wherein the insulating substrates are of equal thickness.
5. The IGBT low stress package structure of claim 1, wherein the top and bottom surfaces of the insulating substrates in staggered combination are in the same plane.
6. The IGBT low stress package structure of claim 1, wherein the upper metal layer and the lower metal layer are rectangular metal foils respectively.
7. The IGBT low stress package structure of claim 1, wherein the upper metal layer and the lower metal layer are circular metal foils, respectively.
8. The IGBT low-stress packaging structure of claim 5 or 6, wherein the upper metal layer is opposite to the lower metal layer, and the edges of the insulating substrate, the upper metal layer and the lower metal layer are respectively aligned.
9. The preparation method of the IGBT low-stress packaging structure is characterized by comprising the following steps of:
1) preparation of insulating substrate
1.1) preparing a plurality of insulating substrates in a right cross shape;
1.2) respectively generating thin oxide films on the bottom surface of the upper metal layer and the top surface of the lower metal layer;
1.3) all the insulating substrates are arranged on the top surface of the lower metal layer and are laterally staggered and attached;
1.4) covering an upper metal layer, enabling the bottom surface of the upper metal layer to be attached to the top surface of each insulating substrate, and enabling the edges of the upper metal layer and the lower metal layer to be aligned up and down;
1.5) putting the assembly obtained in the step 1.4) into a reaction furnace, heating to 1066-1078 ℃, keeping for 45-60 min, and gradually cooling to room temperature;
1.6) cutting off the part which protrudes out of the upper metal layer and the lower metal layer to obtain an insulating substrate base plate with a rectangular or circular structure;
2) bonding the chip with the metalized back surface on the top surface of the insulating substrate base plate in the step 1.6) through a chip solder layer;
3) and (3) bonding the bottom surface of the insulating substrate base plate after the step 2) on the top surface of the base plate through the insulating substrate base plate solder layer to finish the preparation of the packaging structure.
CN202111500130.8A 2021-12-09 2021-12-09 IGBT low-stress packaging structure and preparation method Pending CN114242663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111500130.8A CN114242663A (en) 2021-12-09 2021-12-09 IGBT low-stress packaging structure and preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111500130.8A CN114242663A (en) 2021-12-09 2021-12-09 IGBT low-stress packaging structure and preparation method

Publications (1)

Publication Number Publication Date
CN114242663A true CN114242663A (en) 2022-03-25

Family

ID=80754354

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111500130.8A Pending CN114242663A (en) 2021-12-09 2021-12-09 IGBT low-stress packaging structure and preparation method

Country Status (1)

Country Link
CN (1) CN114242663A (en)

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