CN114242658A - Process integration method for integrating high-voltage CMOS (complementary metal oxide semiconductor) in logic process - Google Patents

Process integration method for integrating high-voltage CMOS (complementary metal oxide semiconductor) in logic process Download PDF

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CN114242658A
CN114242658A CN202111472335.XA CN202111472335A CN114242658A CN 114242658 A CN114242658 A CN 114242658A CN 202111472335 A CN202111472335 A CN 202111472335A CN 114242658 A CN114242658 A CN 114242658A
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voltage
forming
cmos
voltage cmos
region
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钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

The invention discloses a process integration method for integrating a high-voltage CMOS in a logic process, which comprises the following steps: step one, forming a first channel region of a high-voltage CMOS; step two, forming a first drift region of the high-voltage CMOS; step three, performing first furnace tube hot drive trap; step four, forming a high-voltage gate oxide layer by adopting a first thermal oxidation process; step five, forming shallow trench isolation, wherein the depth of the first shallow trench isolation positioned in the forming area of the high-voltage CMOS is smaller than the depth of the second shallow trench isolation positioned in the forming area of the logic device; sixthly, completing the process before the forming process of the grid conductive material layer in the forming area of the logic device, and then forming the grid conductive material layer; and seventhly, performing source-drain injection of the first conduction type heavy doping. The invention can eliminate the stress of the thermal process required by the high-voltage CMOS on the active region, thereby eliminating the defect of the active region caused by the stress and improving the quality of the high-voltage gate oxide layer and the performance of the high-voltage CMOS.

Description

Process integration method for integrating high-voltage CMOS (complementary metal oxide semiconductor) in logic process
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for integrating a high voltage CMOS in a logic process.
Background
The high-voltage CMOS technology is a manufacturing process of a screen display driving chip. The high-voltage CMOS device is characterized in that the high-voltage CMOS device needs to be integrated with a logic process so as to realize organic combination of high-voltage driving and logic signal processing.
Both the gate and the drain of the high voltage CMOS device need to withstand high voltages, requiring a thick gate oxide layer, i.e., a thick gate silicon oxide dielectric layer, and also requiring a drain drift region formed by thermal drive-in to be more uniformly doped, which all require a large amount of thermal processes to be introduced into the process. Although these thermal processes are performed prior to logic device fabrication, if the thermal processes occur after Shallow Trench Isolation (STI) in the logic process, large stresses can develop in the active area causing defects and dislocations in the active area, resulting in device failure.
If the oxidation process of the thick gate silicon oxide of the high-voltage CMOS is finished after STI, the oxidation speed is slower in the edge region of the STI, so that the thickness of a gate oxide layer of the high-voltage CMOS is uneven, double peaks appear in an Id-Vg curve, and a high leakage current phenomenon of a device is formed, wherein Id is drain current, and Vg is gate voltage.
The low on-resistance of high voltage CMOS requires that the STI depth in the drift region is not too deep and is not compatible with the STI depth of advanced logic processes.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a process integration method for integrating a high-voltage CMOS in a logic process, which can eliminate the stress on an active region caused by a thermal process required by the high-voltage CMOS, thereby eliminating the defect of the active region caused by the stress and simultaneously improving the performance of the CMOS.
In order to solve the above technical problem, the process integration method for integrating a high voltage CMOS in a logic process according to the present invention, in which the operating voltage of a logic device is lower than the operating voltage of the high voltage CMOS, includes the steps of:
step one, forming a first channel region doped with a second conduction type in the semiconductor substrate of the selected region of the forming region of the high-voltage CMOS.
And step two, forming a first drift region doped with a first conduction type in the semiconductor substrate of the selected region of the forming region of the high-voltage CMOS.
And step three, performing a first furnace tube hot drive well, wherein the furnace tube hot drive well has a first thermal process, the more the first thermal process, the better the doping uniformity of the first drift region, and the first thermal process is increased to ensure that the doping uniformity of the first drift region is improved to meet the withstand voltage requirement of the high-voltage CMOS.
And fourthly, forming a high-voltage gate oxide layer on the surface of the semiconductor substrate in the formation region of the high-voltage CMOS by adopting a first thermal oxidation process, wherein the first thermal oxidation process has a second thermal process, the more the second thermal process is, the thicker the thickness of the high-voltage gate oxide layer is, and the second thermal process is increased to ensure that the high-voltage gate oxide layer meets the withstand voltage requirement of the high-voltage CMOS.
And step five, forming shallow trench isolation, wherein the shallow trench isolation comprises a first shallow trench isolation positioned in a forming area of the high-voltage CMOS and a second shallow trench isolation positioned in a forming area of the logic device, and the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation by utilizing the characteristic that the high-voltage gate oxide layer is formed in the forming area of the high-voltage CMOS before the shallow trench isolation is formed.
And the semiconductor substrate of the region surrounded by the shallow trench isolation is used as an active region, and the stress applied to the active region is reduced and the defect of the active region generated by the stress is eliminated by utilizing the characteristic that the first thermal process and the second thermal process are positioned before the shallow trench isolation forming process.
The first thermal oxidation process is placed before the shallow trench isolation forming process, so that the thickness of the high-voltage gate oxide layer is not affected by the edge of the shallow trench isolation, and the uniformity of the high-voltage gate oxide layer is improved.
And step six, completing the process before the forming process of the gate conductive material layer in the forming area of the logic device, and then simultaneously forming the gate conductive material layer in the forming area of the high-voltage CMOS and the forming area of the logic device.
And seventhly, performing source-drain injection of the first conductive type heavily doped, and forming source-drain regions in the forming region of the high-voltage CMOS and the forming region of the logic device.
In a further improvement, the logic device comprises a medium-voltage CMOS and a low-voltage CMOS, wherein the operating voltage of the medium-voltage CMOS is smaller than that of the high-voltage CMOS, and the operating voltage of the medium-voltage CMOS is larger than that of the low-voltage CMOS.
The further improvement is that the medium-voltage gate oxide layer of the medium-voltage CMOS is formed by adopting a second thermal oxidation process, and the second thermal oxidation process is arranged after the first thermal oxidation process in the fourth step and before the shallow trench isolation forming process in the fifth step; the thickness of the medium-voltage gate oxide layer is thinner than that of the high-voltage gate oxide layer.
The second thermal oxidation process has a third thermal process, and the stress on the active region is reduced and the defects of the active region caused by the stress are eliminated by utilizing the characteristic that the third thermal process is positioned before the shallow trench isolation forming process.
Meanwhile, the second thermal oxidation process is placed before the shallow trench isolation forming process to ensure that the thickness of the medium-voltage gate oxide layer is not influenced by the edge of the shallow trench isolation, so that the uniformity of the medium-voltage gate oxide layer is improved.
The further improvement is that the step six comprises the following sub-steps:
and 61, forming a second channel region with second conductivity type doping of the medium-voltage CMOS in the forming region of the medium-voltage CMOS.
And 62, forming a third channel region with the second conductive type doping of the low-voltage CMOS in the forming region of the low-voltage CMOS.
And 63, removing the medium-voltage gate oxide layer in the forming area of the low-voltage CMOS.
And 64, carrying out a third thermal oxidation process to form a low-voltage gate oxide layer on the surface of the semiconductor substrate in the low-voltage CMOS forming area.
And 65, forming the grid conductive material layer, carrying out graphical etching on the grid conductive material layer, and removing the high-voltage gate oxide layer, the medium-voltage gate oxide layer and the low-voltage gate oxide layer outside the area covered by the graphical grid conductive material layer.
In a further improvement, the gate conductive material layer is made of polysilicon gate.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the high voltage CMOS comprises a high voltage NMOS and a high voltage PMOS.
For the high-voltage NMOS, the first conduction type is an N type, and the second conduction type is a P type.
For the high voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
In a further improvement, in the first step, the first channel region of the high voltage NMOS and the first channel region of the high voltage PMOS are separately performed.
In the second step, the first drift region of the high voltage NMOS and the first drift region of the high voltage PMOS are separately performed.
In a further improvement, in the third step and the fourth step, the process of forming the high voltage NMOS and the high voltage PMOS regions is performed simultaneously.
In a further improvement, the medium-voltage CMOS comprises a medium-voltage NMOS and a medium-voltage PMOS;
for the medium voltage NMOS, the first conduction type is N type, and the second conduction type is P type;
for the medium voltage PMOS, the first conductive type is P type, and the second conductive type is N type.
In a further improvement, in step 61, the second channel region of the medium voltage NMOS and the second channel region of the medium voltage PMOS are separately performed.
In a further improvement, the low voltage CMOS comprises a low voltage NMOS and a low voltage PMOS;
for the low-voltage NMOS, the first conduction type is an N type, and the second conduction type is a P type;
for the low voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
In a further improvement, in step 62, the third channel region of the low voltage NMOS and the third channel region of the low voltage PMOS are separately performed.
In a further improvement, in step 64, the low voltage NMOS and low voltage PMOS formation regions are processed simultaneously.
The further improvement is that the high-voltage CMOS is adopted in a screen display driving chip.
The invention makes special arrangement for the process sequence in the integration process of the logic device and the high-voltage CMOS, and places the thermal processes which are necessary to meet the voltage-resisting performance of the high-voltage CMOS in the high-voltage CMOS, namely the first thermal process and the second thermal process, before the forming process of the shallow trench isolation, so that the stress caused by the difference of the thermal expansion coefficients of different materials of the active region and the shallow trench isolation in the first thermal process and the second thermal process can be avoided, and the defects and the dislocation caused by the stress action of the active region can be eliminated.
Meanwhile, the thermal processes required by the high-voltage CMOS, such as the first thermal process and the second thermal process, are not limited by the adverse effect on the active region, so that the first thermal process and the second thermal process can be fully performed, the doping uniformity of the first drift region can be fully improved, the thickness of the high-voltage gate oxide layer can be increased to a voltage-resistant required value, and finally the voltage-resistant performance of the high-voltage CMOS can be improved.
In addition, the first thermal oxidation process is placed before the shallow trench isolation is formed, so that the condition that the thickness of the high-voltage gate oxide layer is reduced by the edge of the shallow trench isolation can be prevented, and finally, the thickness of the high-voltage gate oxide layer in each area can be uniform, so that the quality of the high-voltage gate oxide layer can be improved.
In addition, the high-voltage gate oxide layer is formed before the shallow trench isolation, so that when the shallow trench is formed by adopting the same etching process in the process of forming the shallow trench isolation, the region where the high-voltage gate oxide layer is formed and the region where the high-voltage gate oxide layer is not formed can obtain different shallow trench depths, and the depth of the shallow trench in the region of the high-voltage gate oxide layer can be shallower, so that the depth of the shallow trench isolation of the high-voltage CMOS, namely the first shallow trench isolation, can be shallower, which is consistent with the requirement of the high-voltage CMOS on the depth of the first shallow trench isolation arranged in the drift region, and because the requirement is favorable for reducing the on-resistance, the process cost for manufacturing the shallow trench isolations with different depths can be saved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a process integration method for integrating high voltage CMOS in a logic process according to an embodiment of the present invention;
fig. 2A to fig. 2N are schematic device structures in steps of a process integration method for integrating a high-voltage CMOS in a logic process according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a flow chart of a process integration method for integrating a high-voltage CMOS in a logic process according to an embodiment of the present invention; fig. 2A to 2N are schematic diagrams of device structures in steps of a process integration method for integrating a high-voltage CMOS in a logic process according to an embodiment of the present invention; the working voltage of a logic device in the process integration method for integrating the high-voltage CMOS in the logic process is less than that of the high-voltage CMOS, and the method comprises the following steps:
step one, as shown in fig. 2A, a first channel region 102 doped with a second conductivity type is formed in the semiconductor substrate 101 of a selected region of the formation region 201 of the high-voltage CMOS. The formation region 201 of the high-voltage CMOS is indicated in fig. 2C with a parenthesis.
In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.
Step two, as shown in fig. 2B, a first drift region 103 doped with a first conductivity type is formed in the semiconductor substrate 101 in a selected region of the formation region 201 of the high-voltage CMOS.
Step three, as shown in fig. 2B, a first furnace tube thermal drive-in is performed, the furnace tube thermal drive-in has a first thermal process, the more the first thermal process, the better the doping uniformity of the first drift region 103 is, and the first thermal process is increased to increase the doping uniformity of the first drift region 103 to meet the withstand voltage requirement of the high-voltage CMOS.
Step four, as shown in fig. 2D, a first thermal oxidation process is adopted to form a high-voltage gate oxide layer 104a on the surface of the semiconductor substrate 101 in the formation region 201 of the high-voltage CMOS, the first thermal oxidation process has a second thermal process, the more the second thermal process, the thicker the thickness of the high-voltage gate oxide layer 104a, and the second thermal process is increased to enable the high-voltage gate oxide layer 104a to meet the withstand voltage requirement of the high-voltage CMOS.
As shown in fig. 2C, before the first thermal oxidation process is performed, a step of forming a first hard mask layer 103 and patterning the first hard mask layer 103 is further included, and the patterned first hard mask layer 103 opens a formation region 201 of the high-voltage CMOS.
In the embodiment of the invention, the logic device comprises a medium-voltage CMOS and a low-voltage CMOS, wherein the working voltage of the medium-voltage CMOS is less than that of the high-voltage CMOS, and the working voltage of the medium-voltage CMOS is greater than that of the low-voltage CMOS.
As shown in fig. 2E, the medium-voltage gate oxide layer 104b of the medium-voltage CMOS is formed by a second thermal oxidation process, and the second thermal oxidation process is disposed after the first thermal oxidation process and before the shallow trench isolation formation process in the subsequent step five; the thickness of the medium-voltage gate oxide layer 104b is thinner than that of the high-voltage gate oxide layer 104 a.
The second thermal oxidation process has a third thermal process.
Step five, as shown in fig. 2I, shallow trench isolations are formed, the shallow trench isolations include a first shallow trench isolation 106a located in the formation region 201 of the high-voltage CMOS and a second shallow trench isolation 106b located in the formation region of the logic device, and the depth of the first shallow trench isolation 106a is made smaller than the depth of the second shallow trench isolation 106b by utilizing the characteristic that the high-voltage gate oxide layer 104a is formed in the formation region 201 of the high-voltage CMOS before the shallow trench isolation is formed.
The semiconductor substrate 101 in the region surrounded by the shallow trench isolation is used as an active region, and the stress applied to the active region is reduced and the defect of the active region caused by the stress is eliminated by utilizing the characteristic that the first thermal process and the second thermal process are both positioned before the shallow trench isolation forming process. Meanwhile, in the embodiment of the invention, the characteristic that the third thermal process is positioned before the shallow trench isolation forming process is also utilized, so that the stress applied to the active region is further reduced, and the defects of the active region caused by the stress are eliminated.
The first thermal oxidation process is placed before the shallow trench isolation forming process, so that the thickness of the high-voltage gate oxide layer 104a is not affected by the edge of the shallow trench isolation, and the uniformity of the high-voltage gate oxide layer 104a is improved. In the embodiment of the present invention, the second thermal oxidation process is placed before the formation process of the shallow trench isolation to ensure that the thickness of the medium voltage gate oxide layer 104b is not affected by the edge of the shallow trench isolation, so as to improve the uniformity of the medium voltage gate oxide layer 104 b.
In the embodiment of the invention, the step of forming the shallow trench isolation comprises the following sub-steps:
as shown in fig. 2F, a second hard mask layer 302 is formed. The second hard mask layer 302 is usually made of silicon nitride, and the high voltage gate oxide layer 104a and the medium voltage gate oxide layer 104b are used as buffer layers between the silicon nitride of the second hard mask layer 302 and the semiconductor substrate 101.
As shown in fig. 2G, the second hard mask layer 302 is patterned. Generally, the method includes defining a shallow trench isolation formation region by using a photolithography process, and then etching the second hard mask layer 302 according to the photolithography definition to open the shallow trench isolation formation region.
As shown in fig. 2H, the patterned second hard mask layer 302 is used as a mask to etch the bottom oxide layer, such as the high voltage gate oxide layer 104a or the medium voltage gate oxide layer 104b, and the semiconductor substrate 101, so as to form shallow trenches 105a and 105 b. The shallow trenches 105a and 105b have different depths due to the different thickness between the high voltage gate oxide 104a and the medium voltage gate oxide 104 b.
As shown in fig. 2I, the first shallow trench isolation 106a and the second shallow trench isolation 106b are formed by filling field oxygen in the shallow trenches 105a and 105b, respectively.
Thereafter, the second hard mask layer 302 is removed.
And step six, completing the processes before the forming process of the gate conductive material layer 109 in the forming area of the logic device. Thereafter, as shown in fig. 2M, a gate conductive material layer 109 is formed in both the formation region 201 of the high-voltage CMOS and the formation region of the logic device.
In the embodiment of the invention, the sixth step comprises the following sub-steps:
step 61, as shown in fig. 2J, a second channel region 107 with a second conductivity type doping of the medium voltage CMOS is formed in the formation region 202a of the medium voltage CMOS.
Step 62, as shown in fig. 2K, a third channel region 108 with the second conductivity type doping of the low-voltage CMOS is formed in the formation region 202b of the low-voltage CMOS.
Step 63, as shown in fig. 2L, removing the medium voltage gate oxide layer 104b in the formation region 202b of the low voltage CMOS.
Step 64, as shown in fig. 2L, a third thermal oxidation process is performed to form a low-voltage gate oxide layer 202c on the surface of the semiconductor substrate 101 in the low-voltage CMOS forming region 202 b.
Step 65, forming the gate conductive material layer 109, performing patterned etching on the gate conductive material layer 109, and removing the high-voltage gate oxide layer 104a, the medium-voltage gate oxide layer 104b, and the low-voltage gate oxide layer 202c outside the area covered by the patterned gate conductive material layer 109.
Preferably, the gate conductive material layer 109 is made of polysilicon gate.
Seventhly, as shown in fig. 2N, performing source-drain implantation with first conductivity type heavy doping, and forming source-drain regions 110 in the formation region 201 of the high-voltage CMOS and the formation region of the logic device.
In the embodiment of the invention, the high-voltage CMOS comprises a high-voltage NMOS and a high-voltage PMOS.
For the high-voltage NMOS, the first conduction type is an N type, and the second conduction type is a P type.
For the high voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
In the first step, the first channel region 102 of the high voltage NMOS and the first channel region 102 of the high voltage PMOS are separately performed.
In the second step, the first drift region 103 of the high voltage NMOS and the first drift region 103 of the high voltage PMOS are separately performed.
In the third step and the fourth step, the processes of forming the regions of the high-voltage NMOS and the high-voltage PMOS are simultaneously carried out.
The medium-voltage CMOS comprises a medium-voltage NMOS and a medium-voltage PMOS;
for the medium voltage NMOS, the first conduction type is N type, and the second conduction type is P type;
for the medium voltage PMOS, the first conductive type is P type, and the second conductive type is N type.
In step 61, the second channel region 107 of the medium voltage NMOS and the second channel region 107 of the medium voltage PMOS are separately performed.
The low-voltage CMOS comprises a low-voltage NMOS and a low-voltage PMOS;
for the low-voltage NMOS, the first conduction type is an N type, and the second conduction type is a P type;
for the low voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
In step 62, the third channel region 108 of the low voltage NMOS and the third channel region 108 of the low voltage PMOS are performed separately.
In step 64, the formation regions of the low voltage NMOS and the low voltage PMOS are processed simultaneously.
In the embodiment of the invention, the high-voltage CMOS is applied to a screen display driving chip.
The embodiment of the invention makes special arrangement for the process sequence in the integration process of the logic device and the high-voltage CMOS, and places the thermal processes which are necessary to meet the voltage-resisting performance of the high-voltage CMOS in the high-voltage CMOS, namely the first thermal process and the second thermal process, before the forming process of the shallow trench isolation, so that the stress caused by the difference of the thermal expansion coefficients of different materials of the active region and the shallow trench isolation in the first thermal process and the second thermal process can be avoided, and the defects and the dislocation caused by the stress action on the active region can be eliminated.
Meanwhile, the thermal processes required by the high-voltage CMOS, such as the first thermal process and the second thermal process, are not limited by adverse effects on the active region, so that the first thermal process and the second thermal process can be sufficiently performed, so that the doping uniformity of the first drift region 103 can be sufficiently improved, the thickness of the high-voltage gate oxide layer 104a can be increased to a required voltage resistance value, and finally the voltage resistance of the high-voltage CMOS can be improved.
In addition, the first thermal oxidation process of the embodiment of the invention can prevent the thickness of the high-voltage gate oxide layer 104a from being reduced by the edge of the shallow trench isolation because the first thermal oxidation process is arranged before the shallow trench isolation is formed, and finally, the thickness of the high-voltage gate oxide layer 104a in each area can be uniform, so that the quality of the high-voltage gate oxide layer 104a can be improved.
In addition, the high-voltage gate oxide layer 104a of the embodiment of the invention is formed before the shallow trench isolation, so that when the shallow trench is formed by adopting the same etching process in the shallow trench isolation forming process, the region where the high-voltage gate oxide layer 104a is formed and the region where the high-voltage gate oxide layer 104a is not formed can obtain different shallow trench depths, and the depth of the shallow trench in the region of the high-voltage gate oxide layer 104a can be shallower, so that the depth of the shallow trench isolation of the high-voltage CMOS, namely the depth of the first shallow trench isolation 106a can be shallower, which is consistent with the requirement of the high-voltage CMOS on the depth of the first shallow trench isolation 106a arranged in the drift region, and because the requirement is favorable for reducing the on-resistance, the embodiment of the invention can save the process cost for manufacturing the shallow trench isolations with different depths.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A process integration method for integrating a high-voltage CMOS in a logic process is characterized in that the working voltage of a logic device is less than that of the high-voltage CMOS, and comprises the following steps:
step one, forming a first channel region doped with a second conduction type in a semiconductor substrate of a selected region of a forming region of the high-voltage CMOS;
step two, forming a first drift region doped with a first conductive type in the semiconductor substrate of the selected region of the forming region of the high-voltage CMOS;
performing a first furnace tube thermal drive-in, wherein the furnace tube thermal drive-in has a first thermal process, the more the first thermal process, the better the doping uniformity of the first drift region, and the first thermal process is increased to improve the doping uniformity of the first drift region to meet the withstand voltage requirement of the high-voltage CMOS;
forming a high-voltage gate oxide layer on the surface of the semiconductor substrate in the formation region of the high-voltage CMOS by adopting a first thermal oxidation process, wherein the first thermal oxidation process has a second thermal process, the more the second thermal process, the thicker the thickness of the high-voltage gate oxide layer is, and the second thermal process is increased to ensure that the high-voltage gate oxide layer meets the withstand voltage requirement of the high-voltage CMOS;
forming shallow trench isolation, wherein the shallow trench isolation comprises a first shallow trench isolation positioned in a forming region of the high-voltage CMOS and a second shallow trench isolation positioned in a forming region of the logic device, and the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation by utilizing the characteristic that the high-voltage gate oxide layer is formed in the forming region of the high-voltage CMOS before the shallow trench isolation is formed;
the semiconductor substrate of the region surrounded by the shallow trench isolation is used as an active region, and the stress applied to the active region is reduced and the defect of the active region generated by the stress is eliminated by utilizing the characteristic that the first thermal process and the second thermal process are positioned before the shallow trench isolation forming process;
the first thermal oxidation process is placed before the shallow trench isolation forming process, so that the thickness of the high-voltage gate oxide layer is not influenced by the edge of the shallow trench isolation, and the uniformity of the high-voltage gate oxide layer is improved;
sixthly, completing the process before the forming process of the grid electrode conductive material layer in the forming area of the logic device, and then simultaneously forming the grid electrode conductive material layer in the forming area of the high-voltage CMOS and the forming area of the logic device;
and seventhly, performing source-drain injection of the first conductive type heavily doped, and forming source-drain regions in the forming region of the high-voltage CMOS and the forming region of the logic device.
2. The process integration method of integrating high voltage CMOS in a logic process of claim 1, wherein: the logic device comprises a medium-voltage CMOS and a low-voltage CMOS, wherein the working voltage of the medium-voltage CMOS is smaller than that of the high-voltage CMOS, and the working voltage of the medium-voltage CMOS is larger than that of the low-voltage CMOS.
3. A process integration method of integrating high voltage CMOS in a logic process according to claim 2, wherein: forming a medium-voltage gate oxide layer of the medium-voltage CMOS by adopting a second thermal oxidation process, wherein the second thermal oxidation process is placed after the first thermal oxidation process in the step four and before the shallow trench isolation forming process in the step five; the thickness of the medium-voltage gate oxide layer is thinner than that of the high-voltage gate oxide layer;
the second thermal oxidation process has a third thermal process, and the stress borne by the active region is reduced and the defects of the active region caused by the stress are eliminated by utilizing the characteristic that the third thermal process is positioned before the shallow trench isolation forming process;
meanwhile, the second thermal oxidation process is placed before the shallow trench isolation forming process to ensure that the thickness of the medium-voltage gate oxide layer is not influenced by the edge of the shallow trench isolation, so that the uniformity of the medium-voltage gate oxide layer is improved.
4. A process integration method of integrating high voltage CMOS in a logic process according to claim 3, wherein: step six comprises the following sub-steps:
step 61, forming a second channel region with second conductivity type doping of the medium-voltage CMOS in a forming region of the medium-voltage CMOS;
step 62, forming a third channel region with second conductivity type doping of the low-voltage CMOS in the forming region of the low-voltage CMOS;
step 63, removing the medium-voltage gate oxide layer in the formation region of the low-voltage CMOS;
step 64, carrying out a third thermal oxidation process to form a low-voltage gate oxide layer on the surface of the semiconductor substrate in the low-voltage CMOS forming area;
and 65, forming the grid conductive material layer, carrying out graphical etching on the grid conductive material layer, and removing the high-voltage gate oxide layer, the medium-voltage gate oxide layer and the low-voltage gate oxide layer outside the area covered by the graphical grid conductive material layer.
5. A process integration method of integrating high voltage CMOS in a logic process according to claim 3, wherein: the grid conductive material layer adopts a polysilicon grid.
6. The process integration method of integrating high voltage CMOS in a logic process of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
7. The process integration method of integrating high voltage CMOS in a logic process according to claim 1 or 4, wherein: the high-voltage CMOS comprises a high-voltage NMOS and a high-voltage PMOS;
for the high-voltage NMOS, the first conduction type is N type, and the second conduction type is P type;
for the high voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
8. The process integration method of integrating high voltage CMOS in a logic process of claim 7, wherein: in the first step, the first channel region of the high-voltage NMOS and the first channel region of the high-voltage PMOS are separately performed;
in the second step, the first drift region of the high voltage NMOS and the first drift region of the high voltage PMOS are separately performed.
9. The process integration method of integrating high voltage CMOS in a logic process of claim 8, wherein:
in the third step and the fourth step, the processes of forming the regions of the high-voltage NMOS and the high-voltage PMOS are simultaneously carried out.
10. The process integration method of integrating high voltage CMOS in a logic process of claim 4, wherein: the medium-voltage CMOS comprises a medium-voltage NMOS and a medium-voltage PMOS;
for the medium voltage NMOS, the first conduction type is N type, and the second conduction type is P type;
for the medium voltage PMOS, the first conductive type is P type, and the second conductive type is N type.
11. The process integration method of integrating high voltage CMOS in a logic process of claim 10, wherein: in step 61, the second channel region of the medium voltage NMOS and the second channel region of the medium voltage PMOS are separately performed.
12. The process integration method of integrating high voltage CMOS in a logic process of claim 4, wherein: the low-voltage CMOS comprises a low-voltage NMOS and a low-voltage PMOS;
for the low-voltage NMOS, the first conduction type is an N type, and the second conduction type is a P type;
for the low voltage PMOS, the first conductivity type is P-type and the second conductivity type is N-type.
13. The process integration method of integrating high voltage CMOS in a logic process of claim 12, wherein: in step 62, the third channel region of the low voltage NMOS and the third channel region of the low voltage PMOS are separately performed.
14. The process integration method of integrating high voltage CMOS in a logic process of claim 12, wherein: in step 64, the formation regions of the low voltage NMOS and the low voltage PMOS are processed simultaneously.
15. The process integration method of integrating high voltage CMOS in a logic process of claim 1, wherein: the high-voltage CMOS is adopted in the screen display driving chip.
CN202111472335.XA 2021-12-06 2021-12-06 Process integration method for integrating high-voltage CMOS (complementary metal oxide semiconductor) in logic process Pending CN114242658A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117577586A (en) * 2024-01-16 2024-02-20 合肥晶合集成电路股份有限公司 Semiconductor structure and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117577586A (en) * 2024-01-16 2024-02-20 合肥晶合集成电路股份有限公司 Semiconductor structure and preparation method thereof
CN117577586B (en) * 2024-01-16 2024-04-30 合肥晶合集成电路股份有限公司 Semiconductor structure and preparation method thereof

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