CN114242607A - Test structure and forming method thereof - Google Patents

Test structure and forming method thereof Download PDF

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Publication number
CN114242607A
CN114242607A CN202111538755.3A CN202111538755A CN114242607A CN 114242607 A CN114242607 A CN 114242607A CN 202111538755 A CN202111538755 A CN 202111538755A CN 114242607 A CN114242607 A CN 114242607A
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test
pixel
logic
side wall
forming
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刘敏
张栋
范晓
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements

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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A test structure and a method of forming the same, wherein the test structure comprises: the cutting path of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas, wherein the pixel test areas and the logic test areas are alternately arranged in a first direction; the pixel test gate structure is positioned on the pixel test area, and the extending direction of the pixel test gate structure is vertical to the first direction; and the extension direction of the logic test gate structure is vertical to the first direction. The test structure can reduce manufacturing cost, labor and time.

Description

Test structure and forming method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a test structure and a forming method thereof.
Background
The image sensor is constituted by a pixel unit circuit and a logic circuit.
In the related art, a wafer is generally provided, and Pixel areas (pixels) and Logic areas (Logic) performing different functions are formed in a chip area of the wafer. The pixel area has pixel unit circuit therein, and the logic area has logic circuit therein, so that the pixel area and the logic area have different designs and different internal structures. Due to the fact that the pixel area and the logic area are designed differently and have different internal structures, in the product research and development process, a sample of the pixel area in the chip area and a sample of the logic area in the chip area need to be cut respectively so as to detect the pixel area and the logic area.
However, since it is necessary to separately cut the sample of the pixel area in the chip area and the sample of the logic area in the chip area, not only a large number of trial production samples need to be provided, but also a large number of times of cutting is required, and the chip area after cutting is damaged and cannot be reused. Thus, a waste of manufacturing cost, labor and time is caused.
Disclosure of Invention
The invention provides a test structure and a forming method thereof, which aim to reduce manufacturing cost, labor and time.
In order to solve the above technical problem, a technical solution of the present invention provides a test structure, including: the cutting path of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas, wherein the pixel test areas and the logic test areas are alternately arranged in a first direction; the pixel test gate structure is positioned on the pixel test area, and the extending direction of the pixel test gate structure is vertical to the first direction; and the extension direction of the logic test gate structure is vertical to the first direction.
Optionally, the method includes: a first gate oxide layer on the pixel test region; a second gate oxide layer on the logic test region and on the first gate oxide layer; the grid electrodes are arranged on the second grid oxide layer, and the grid electrodes are arranged on the pixel test area and the logic test area respectively; and, the pixel test gate structure includes: the first gate oxide layer, the second gate oxide layer located on the first gate oxide layer, and the gate located on the pixel test region, the logic test gate structure includes: the second gate oxide layer is positioned on the logic test area, and the grid electrode is positioned on the logic test area.
Optionally, the method further includes: the first side wall is positioned on the side wall surface of the grid electrode on the pixel test area; the second side wall is positioned on the first side wall and the side wall surface of the grid electrode on the logic test area; and, the pixel test gate structure further comprises: the first side wall and be located the second side wall of the side wall face of first side wall, logic test gate structure still includes: and the second side wall is positioned on the side wall surface of the grid electrode on the logic test area.
Optionally, the method further includes: the contact blocking layer is positioned on the surfaces of the grid electrode and the second side wall on the pixel test area and the surface of the pixel test area, and the grid electrode on the logic test area and the surface of the logic test area are exposed out of the contact blocking layer; and the contact layer is positioned on the top of the grid electrode on the logic test area and on at least part of the surface of the logic test area on two sides of the logic test grid structure along the first direction.
Optionally, the method further includes: an active region located in the scribe line, the active region extending along the first direction and located in the logic test region and the pixel test region, and the first gate oxide layer and the second gate oxide layer are located on the active region, and the gate electrode crosses the active region; and the isolation structure penetrates through the active area between the adjacent logic test area and the pixel test area in the direction perpendicular to the first direction.
Optionally, the method further includes: the conductive structures are respectively positioned on the top surface of the grid electrode of the pixel test area, the surface of the active area in the pixel test area at two sides of the pixel test grid structure along the first direction, and the surface of the contact layer.
Optionally, the material of the first sidewall includes an oxide.
Optionally, the second side wall includes: the second side wall of lower floor and be located upper second side wall on lower floor's second side wall surface.
Optionally, the material of the lower second sidewall includes an oxide, and the material of the upper second sidewall includes a nitride.
Optionally, the contact barrier layer comprises: the lower layer is in contact with the barrier layer, and the upper layer is in contact with the barrier layer and is positioned on the surface of the lower layer.
Optionally, the material of the lower contact barrier layer includes an oxide, and the material of the upper contact barrier layer is a nitride.
Correspondingly, the technical scheme of the invention also provides a forming method of any one of the test structures, which comprises the following steps: providing a substrate, wherein a cutting path of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas, and the pixel test areas and the logic test areas are alternately arranged in a first direction; forming a pixel test gate structure on the pixel test area, wherein the extending direction of the pixel test gate structure is perpendicular to the first direction; and forming a logic test gate structure on the logic test area, wherein the extension direction of the logic test gate structure is vertical to the first direction.
Optionally, the method for forming the pixel test gate structure and the logic test gate structure includes: forming a first gate oxide layer on the pixel test region; forming a second gate oxide layer on the logic test region and the first gate oxide layer; and forming a plurality of gates on the second gate oxide layer, wherein the gates are respectively arranged on the pixel test region and the logic test region.
Optionally, the method for forming the first gate oxide layer on the pixel test region includes: forming a first gate oxide film on the logic test area and the pixel test area; forming a first mask layer on the pixel test area, wherein the first mask layer exposes the first gate oxide film on the logic test area; etching the first gate oxide film by taking the first mask layer as a mask until the exposed first gate oxide film is removed to form the first gate oxide layer; and removing the first mask layer after the first gate oxide layer is formed and before the second gate oxide layer is formed.
Optionally, the method for forming the pixel test gate structure and the logic test gate structure further includes: forming a first side wall on the side wall surface of the grid electrode on the pixel test area; forming a second side wall on the first side wall and the side wall surface of the grid electrode on the logic test area; and the first gate oxide layer, the second gate oxide layer positioned on the first gate oxide layer, the gate positioned on the pixel test region, the first side wall, and the second side wall positioned on the side wall surface of the first side wall form the pixel test gate structure, and the second gate oxide layer positioned on the logic test region, the gate positioned on the logic test region, and the second side wall positioned on the side wall surface of the gate positioned on the logic test region form the logic test gate structure.
Optionally, the method for forming the first sidewall on the sidewall surface of the gate on the pixel test region includes: forming an initial first side wall layer on the side wall surfaces of the grid electrodes on the logic test area and the pixel test area; forming a second mask layer on the grid electrode on the pixel test area and the initial first side wall layer, wherein the second mask layer exposes the initial first side wall layer on the logic test area; etching the initial first side wall layer by taking the second mask layer as a mask until the exposed initial first side wall layer is removed to form the first side wall; and after the first side wall is formed and before the second side wall is formed, removing the second mask layer.
Optionally, the method for forming the initial first sidewall layer on the sidewall surfaces of the gates in the logic test area and the pixel test area includes: forming a first side wall film on the surface of the logic test area, the surface of the pixel test area and the surfaces of the gates on the logic test area and the pixel test area; and etching the first side wall film by adopting an anisotropic etching process until the first side wall film on the surfaces of the logic test area, the pixel test area and the top surfaces of the gates on the logic test area and the pixel test area is removed.
Optionally, the method for forming the second sidewall on the first sidewall and the sidewall surface of the gate on the logic test area includes: forming a second side wall film on the gate and the first side wall surface on the pixel test area, the gate surface on the logic test area, the logic test area surface and the pixel test area surface; and etching the second side wall film by adopting an anisotropic etching process until the first side wall and the grid top surface on the pixel test area, the grid top surface on the logic test area, the surface of the logic test area and the second side wall film on the surface of the pixel test area are removed.
Optionally, after forming the pixel test gate structure and the logic test gate structure, the method further includes: forming a contact barrier layer on the surfaces of the grid electrode and the second side wall on the pixel test area and the surface of the pixel test area, wherein the contact barrier layer exposes the grid electrode on the logic test area and the surface of the logic test area; after the contact barrier layer is formed, a contact layer is formed on the top of the grid electrode on the logic test area and at least part of the surface of the logic test area on two sides of the logic test grid structure along the first direction.
Optionally, before forming the first gate oxide layer, the method further includes: forming an active area and an isolation structure in the scribe line, wherein the active area extends along the first direction and is located in the logic test area and the pixel test area, and the isolation structure penetrates through the active area between the adjacent logic test area and the pixel test area in a direction perpendicular to the first direction; the first gate oxide layer and the second gate oxide layer are located on the active region, and the gate electrode crosses the active region.
Optionally, the method further includes: after the contact layer is formed, a plurality of conductive structures are formed on the top surface of the grid electrode of the pixel test area, the surfaces of the active areas on two sides of the pixel test grid structure along the first direction and the surface of the contact layer.
Optionally, the substrate further includes a chip region for forming a chip, and the method for forming the test structure further includes: forming a pixel unit circuit in the chip area, and forming the pixel test gate structure in the process of forming the pixel unit circuit; logic circuits are formed in the chip area, and the logic test gate structures are formed in the process of forming the logic circuits.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the test structure provided by the technical scheme of the invention, on one hand, the cutting channel of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas which are alternately arranged in a first direction, and on the other hand, the pixel test areas are provided with pixel test grid structures which are provided with logic test grid structures so as to respectively form a test structure for testing a pixel unit circuit and a test structure for testing a logic circuit, and the extending directions of the pixel test grid structures and the logic test grid structures are vertical to the first direction, so that by cutting the structures of the logic test areas and the pixel test areas which are alternately arranged in the cutting channel, on the basis of not damaging the pixel unit circuit and the logic unit circuit in the chip area, through a small amount of samples, even 1 sample and a small amount of cutting times, a cut sample is obtained for detection. Thereby, manufacturing costs, labor and time are reduced.
Drawings
Fig. 1 to 13 are schematic structural diagrams of steps in a method for forming a test structure according to an embodiment of the invention.
Detailed Description
As described in the background art, since it is necessary to separately cut a sample of a pixel region in a chip region and a sample of a logic region in the chip region, not only a large number of trial production samples need to be provided, but also a large number of times of cutting is required, and at the same time, the cut chip region is damaged and cannot be reused. Thus, a waste of manufacturing cost, labor and time is caused.
In order to solve the above technical problems, a technical solution of the present invention provides a test structure and a method for forming the same, in which the test structure includes: the cutting path of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas, wherein the pixel test areas and the logic test areas are alternately arranged in a first direction; the pixel test gate structure is positioned on the pixel test area, and the extending direction of the pixel test gate structure is vertical to the first direction; and the extension direction of the logic test gate structure is vertical to the first direction. Therefore, the manufacturing cost, labor and time can be reduced by the test structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 to 13 are schematic structural diagrams of steps in a method for forming a test structure according to an embodiment of the invention.
Referring to fig. 1 and 2, fig. 1 is a schematic top view of fig. 2, and fig. 2 is a schematic cross-sectional view of fig. 1 along a direction a-a, providing a substrate 100.
The substrate 100 includes a plurality of chip regions (not shown) for forming chips, and dicing streets 101 are formed between adjacent chip regions of the substrate 100.
Specifically, the chip area includes a pixel area (not shown) and a logic area (not shown). The pixel area is used for forming a plurality of pixel unit circuits, and the logic area is used for forming a logic circuit to form at least one part of the chip.
After the wafer level manufacturing is completed, the dicing streets 101 are diced to separate the plurality of chip regions without damaging the chips, thereby forming individual chips.
The scribe line 101 of the substrate 100 includes a plurality of pixel test regions PT and a plurality of logic test regions LT, which are alternately arranged in the first direction X.
The pixel test region PT is used to form a test structure for testing the pixel unit circuit, and the logic test region LT is used to form a test structure for testing the logic circuit.
In this embodiment, the first direction X is: the dry pixel test area PT and the logic test areas LT are located in the extending direction of the cutting path 101.
The material of the substrate 100 includes a semiconductor material.
Specifically, the material of the substrate 100 in this embodiment includes silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
Next, pixel unit circuits are formed in the pixel region, and logic circuits are formed in the logic region. In addition, in the present embodiment, in the process of forming the pixel unit circuit, a test structure for testing the pixel unit circuit is formed in the pixel test region PT and on the pixel test region PT of the scribe line 101. And forming a test structure for testing the logic circuit in the logic test area LT and on the logic test area LT of the scribe lane 101 in the process of forming the logic circuit.
Therefore, the consistency of the processes of forming the pixel unit circuit and forming the test structure for testing the pixel unit circuit is better ensured, and the consistency of the processes of forming the logic circuit and forming the test structure for testing the logic circuit is better ensured, so that the detection accuracy is improved.
Specifically, in the present embodiment, the subsequent processing steps performed in the pixel test region PT and on the pixel test region PT of the scribe line 101 to form the test structure are synchronized with at least part of the processing steps performed to form the pixel unit circuit in the pixel region. Similarly, the subsequent process steps performed to form test structures in and on logic test region LT of scribe line 101 are synchronized with at least some of the process steps used to form logic circuits in the logic region LT.
Referring to fig. 3 and 4, fig. 3 is a schematic top view of fig. 4, and fig. 4 is a schematic cross-sectional view of fig. 3 along a direction a-a, wherein an active region S and an isolation structure 110 are formed in the scribe line 101.
The active region S extends in the first direction X and is located within the logic test region LT and the pixel test region PT.
The isolation structure 110 penetrates the active region S between the adjacent logic test region LT and pixel test region PT in a second direction Y perpendicular to the first direction X. With this, isolation between the adjacent logic test region LT and pixel test region PT is achieved.
In the present embodiment, more than 2 active regions S independent of each other are formed in the second direction Y to further increase the number of test structures that can be cut for detection in one sample.
In other embodiments, only 1 active region S is formed.
In this embodiment, the process of forming the active region S includes an ion implantation process and the like.
In this embodiment, the method for forming the isolation structure 110 includes: forming an isolation structure mask layer (not shown) on the surface of the scribe line 101, wherein the isolation structure mask layer exposes the surface of the scribe line 101 between the adjacent logic test area LT and pixel test area PT; etching the cutting channel 101 by using the isolation structure mask layer as a mask to form an isolation opening (not shown); the isolation opening is filled with a material to form the isolation structure 110.
The material of the isolation structure 110 is a dielectric material.
The process of etching the scribe line 101 to form an isolation opening includes at least one of a wet etching process and a dry etching process, and the process of filling a material to form the isolation structure 110 includes a chemical vapor deposition process or a physical vapor deposition process.
Then, forming a pixel test gate structure on the pixel test area PT, wherein the extending direction of the pixel test gate structure is vertical to the first direction X; forming a logic test gate structure on the logic test region LT, wherein an extending direction of the logic test gate structure is perpendicular to the first direction X. Please refer to fig. 5 to 9 for specific steps of forming the pixel test gate structure and the logic test gate structure.
Referring to fig. 5, in the same view direction as fig. 4, a first gate oxide layer 121 is formed on the pixel test region PT in fig. 5.
Specifically, the first gate oxide layer 121 is located on the active region S.
In this embodiment, the material of the first gate oxide layer 121 includes silicon oxide.
Specifically, the method for forming the first gate oxide layer 121 includes: forming a first gate oxide film (not shown) on the logic test region LT and the pixel test region PT; forming a first mask layer (not shown) on the pixel test region PT, the first mask layer exposing the first gate oxide film on the logic test region LT; etching the first gate oxide film by taking the first mask layer as a mask until the exposed first gate oxide film is removed to form the first gate oxide layer 121; after the first gate oxide layer 121 is formed and before the second gate oxide layer is formed, the first mask layer is removed.
In this embodiment, the material of the first mask layer includes a photoresist, and the process for removing the first mask layer includes an ashing process.
In the present embodiment, the process of forming the first gate oxide film includes a chemical vapor deposition process, a physical vapor deposition process, an oxidation process, an atomic layer deposition process, or the like.
In this embodiment, the process of etching the first gate oxide film includes at least one of a wet etching process and a dry etching process.
With continued reference to fig. 5, after the first gate oxide layer 121 is formed, a second gate oxide layer 122 is formed on the logic test region LT and on the first gate oxide layer 121.
Specifically, the second gate oxide layer 122 is located on the active region S.
Thereby, it is achieved that a thicker gate oxide layer (including the first gate oxide layer 121 and the second gate oxide layer 122) is formed on the pixel test region PT, and at the same time, a thinner gate oxide layer (i.e., the second gate oxide layer 122) is formed on the logic test region LT.
In this embodiment, the material of the second gate oxide layer 122 includes silicon oxide.
In the present embodiment, the process of forming the second gate oxide layer 122 includes a chemical vapor deposition process, a physical vapor deposition process, an oxidation process, an atomic layer deposition process, or the like.
Referring to fig. 6, in the view direction of fig. 6 and fig. 5, a plurality of gates 130 are formed on the second gate oxide layer 122, and the gates 130 are respectively disposed on the pixel test region PT and the logic test region LT.
The gate 130 extends in the second direction Y, and the gate 130 crosses the active region S.
In the present embodiment, the material of the gate 130 includes polysilicon.
In this embodiment, the method for forming the gates 130 includes: depositing a gate material layer (not shown) on the pixel test region PT and the logic test region LT; forming a plurality of gate mask structures (not shown) independent of each other, the gate mask structures extending in the second direction Y and crossing the active region S, and the gate mask structures being provided on each pixel test region PT and the gate mask junctions being provided on each logic test region LT; and etching the gate material layer by taking the gate mask structure as a mask until the surface of the isolation structure 110, part of the surface of the pixel test region PT and part of the surface of the logic test region LT are exposed.
It should be noted that, according to practical situations, the critical dimensions of the gate 130 on the pixel test region PT and the gate 130 on the logic test region LT may be different.
Referring to fig. 7, in the same direction as the view of fig. 6 in fig. 7, a first sidewall 141 is formed on the sidewall of the gate 130 over the pixel test area PT.
In this embodiment, the material of the first sidewall spacers 141 includes an oxide.
Specifically, the material of the first sidewall 141 includes silicon oxide.
In this embodiment, the method for forming the first sidewall 141 on the sidewall surface of the gate 130 in the pixel test area PT includes: forming an initial first sidewall layer (not shown) on sidewall surfaces of the gate electrode 130 on the logic test area LT and the pixel test area PT; forming a second mask layer (not shown) on the gate 130 and the initial first sidewall layer on the pixel test region PT, the second mask layer exposing the initial first sidewall layer on the logic test region LT; and etching the initial first side wall layer by taking the second mask layer as a mask until the exposed initial first side wall layer is removed to form the first side wall 141.
In this embodiment, the material of the second mask layer includes a photoresist.
In this embodiment, the method of forming the initial first sidewall layer includes: depositing a first sidewall film (not shown) on the surface of the logic test region LT, the surface of the pixel test region PT, and the surface of the gate electrode 130 on the logic test region LT and the pixel test region PT; and etching the first side wall film by adopting an anisotropic etching process until the first side wall film on the surfaces of the logic test area LT, the pixel test area PT and the top surfaces of the grid electrodes 130 on the logic test area LT and the pixel test area PT are removed.
In this embodiment, after the first sidewall 141 is formed and before the second sidewall is formed subsequently, the second mask layer is removed.
In this embodiment, the process of removing the second mask layer includes an ashing process.
In this embodiment, before forming the first side walls 141, a silicon oxide film 131 is formed on the surface of the gate 130.
In other embodiments, the silicon oxide film is not formed.
Referring to fig. 8 and 9, fig. 8 is a schematic top view of fig. 9, fig. 9 is a schematic cross-sectional view in the direction a-a of fig. 8, and a second sidewall 142 is formed on the first sidewall 141 and the sidewall of the gate 130 over the logic test area LT.
Thereby, the pixel test gate structure 150 and the logic test gate structure 160 are formed.
Specifically, in this embodiment, the pixel test gate structure 150 includes: a first gate oxide layer 121, a second gate oxide layer 122 on the first gate oxide layer 121, a gate 130 on the pixel test region PT, the first sidewall 141, and a second sidewall 142 on a sidewall surface of the first sidewall 141. The logic test gate structure 160 includes: a second gate oxide layer 122 located on the logic test region LT, a gate 130 located on the logic test region LT, and a second sidewall 142 located on a sidewall surface of the gate 130 located on the logic test region LT.
Meanwhile, the pixel test gate structure 150 can have thicker sidewalls (including the first sidewall 141 and the second sidewall 142), and the logic test gate structure 160 can have thinner sidewalls (i.e., the second sidewall 142).
In this embodiment, the method for forming the second sidewall spacers 142 on the first sidewall spacers 141 and the sidewall surfaces of the gate 130 in the logic test area LT includes: depositing a second sidewall film (not shown) on the surfaces of the gate electrode 130 and the first sidewall 141 on the pixel test region PT, the surface of the gate electrode 130 on the logic test region LT, the surface of the logic test region LT, and the surface of the pixel test region PT; and etching the second side wall film by adopting an anisotropic etching process until the first side wall 141 and the top surface of the grid 130 on the pixel test region PT, the top surface of the grid 130 on the logic test region LT, the surface of the logic test region LT and the second side wall film on the surface of the pixel test region PT are removed.
In this embodiment, the second sidewall film includes: the lower floor second side wall membrane and be located upper second side wall membrane on lower floor second side wall membrane surface.
Correspondingly, the second side wall comprises: a lower second sidewall (not shown), and an upper second sidewall (not shown) on the surface of the lower second sidewall.
In this embodiment, the material of the lower second sidewall spacer includes an oxide, and the material of the upper second sidewall spacer includes a nitride.
Specifically, the material of the lower second sidewall includes silicon oxide, and the material of the upper second sidewall includes silicon nitride.
Referring to fig. 10, in a manner consistent with the view of fig. 9, fig. 10 is a view of forming a contact barrier layer 170(SAB, Salicide Block) on the surfaces of the gate 130 and the second sidewall 142 on the pixel test region PT and on the surface of the pixel test region PT, and the contact barrier layer 170 exposes the gate 130 on the logic test region LT and the surface of the logic test region LT.
The contact blocking layer 170 is used to block a reaction between the metal material layer and the surface of the pixel test region PT and the surface of the gate electrode 130 on the pixel test region PT when a contact layer is formed later, so that the contact layer can be formed on the logic test region LT later without forming a contact layer on the pixel test region PT.
In this embodiment, the method for forming the contact blocking layer 170 on the surfaces of the gate 130 and the second sidewall 142 on the pixel test region PT includes: depositing contact barrier films (not shown) on the surfaces of the pixel test region PT, the logic test region LT, and the surfaces of the gates 130 and the second sidewalls 142 on the pixel test region PT and the logic test region LT; forming a third mask structure (not shown) on the pixel test region PT, the third mask structure exposing the logic test region LT; and etching the contact barrier film by taking the third mask structure as a mask until the logic test region LT is exposed.
In this embodiment, the contact barrier film includes: a lower contact barrier film (not shown), and an upper contact barrier film (not shown) on the surface of the lower contact barrier film.
Accordingly, the contact barrier layer 170 includes: a lower contact barrier layer (not shown), and an upper contact barrier layer (not shown) on the surface of the lower contact barrier layer.
In this embodiment, the material of the lower contact barrier layer includes an oxide, and the material of the upper contact barrier layer is a nitride.
Specifically, the material of the lower contact barrier layer comprises silicon oxide, and the material of the upper contact barrier layer is silicon nitride.
Referring to fig. 11, fig. 11 is the same as the view direction of fig. 10, after the contact blocking layer 170 is formed, a contact layer 180 is formed on the top of the gate 130 on the logic test region LT and on at least a portion of the surface of the logic test region LT on both sides of the logic test gate structure 160 along the first direction X.
Specifically, in this embodiment, the contact layer 180 is located on the top of the gate 130 on the logic test region LT and on the surface of the active region S on both sides of the logic test gate structure 160 along the first direction X in the logic test region LT.
The contact layer 180 is used to improve the conductivity between the subsequently formed conductive structure and the gate 130 on the logic test region LT and the active region S of the logic test region LT.
In the present embodiment, the material of the contact layer 180 includes metal silicide.
In this embodiment, the method for forming the contact layer 180 includes: forming a third mask layer (not shown) on the logic test region LT and the pixel test region PT, the third mask layer exposing a portion of the surface of the silicon oxide film 131 on the top surface of the gate 130 on the logic test region LT and at least a portion of the surface of the second gate oxide layer 122 on the active region S on both sides of the logic test gate structure 160 in the first direction X; etching the exposed silicon oxide film 131 and the second gate oxide layer 122 by taking the third mask layer as a mask until the top surface of the gate 130 and the surface of the active region S are exposed; removing the third mask layer after etching the exposed silicon oxide film 131 and the second gate oxide layer 122 with the third mask layer as a mask; after removing the third mask layer, forming a metal material layer (not shown) on the logic test region LT and the pixel test region PT, and contacting the exposed top surface of the gate 130 and the surface of the active region S with the metal material layer; after the metal material layer is formed, an annealing process is performed to react the metal material layer with the top surface of the gate 130 and the surface of the active region S in contact, so as to form the contact layer 180.
Since the contact blocking layer 170 is formed on the pixel test region PT, the contact layer 180 is not formed on the pixel test region PT.
Referring to fig. 12 and 13, fig. 12 is a schematic top view of fig. 13, fig. 13 is a schematic cross-sectional view of fig. 12 in a direction a-a, and a plurality of conductive structures 190 are formed on a top surface of the gate 130 of the pixel test region PT, surfaces of the active region S of the pixel test gate structure 150 along two sides of the first direction X, and a surface of the contact layer 180.
In the present embodiment, the conductive structure 190 is a conductive plug.
In this embodiment, the method of forming the plurality of conductive structures 190 includes: after forming the contact layer 180, forming an etching stop film 191 and a dielectric layer 192 on the surface of the etching stop film 191 on the cutting street 101; forming a fourth mask layer on the surface of the dielectric layer 192, wherein the fourth mask layer exposes a part of the surface of the dielectric layer 192; etching the dielectric layer 192 and the etching stop film 191 by using the fourth mask layer as a mask until the top surface of the gate 130 of the pixel test region PT, the surface of the active region S on both sides of the pixel test gate structure 150 along the first direction X, and the surface of the contact layer 180 are exposed, and forming a plurality of contact holes (CT, not shown) in the dielectric layer 192; depositing material within the number of contact holes forms a number of conductive structures 190.
In the present embodiment, the material of the conductive structure 190 includes tungsten.
Note that, in fig. 12, the etch stop film 191, the dielectric layer 192, the contact stop layer 170, and the contact layer 180 are not shown for ease of understanding and explanation.
Accordingly, an embodiment of the present invention further provides a test structure formed by the above method, please continue to refer to fig. 12 and 13, including: a substrate 100, wherein a scribe line 101 of the substrate 100 includes a plurality of pixel test regions PT and a plurality of logic test regions LT, and the pixel test regions PT and the logic test regions LT are alternately arranged in a first direction X; a pixel test gate structure 150 located on the pixel test region PT, wherein an extending direction of the pixel test gate structure 150 is perpendicular to the first direction X; a logic test gate structure 160 located on the logic test region LT, an extending direction of the logic test gate structure 160 being perpendicular to the first direction X.
In the test structure, on one hand, the scribe line 101 of the substrate 100 includes a plurality of pixel test regions PT and a plurality of logic test regions LT, and the pixel test regions PT and the logic test regions LT are alternately arranged in the first direction X, and on the other hand, the pixel test region PT has a pixel test gate structure 150 and the logic test region LT has a logic test gate structure 160 to respectively constitute a test structure for testing a pixel unit circuit and a test structure for testing a logic circuit, and the extending directions of the pixel test gate structure 150 and the logic test gate structure 160 are perpendicular to the first direction X, so that by cutting the structures of the logic test regions and the pixel test regions alternately arranged in the scribe line, it is possible to perform a test by a small number of samples (wafers) or even by 1 sample without damaging the pixel unit circuit and the logic unit circuit in the chip region, the cut sample for detection is obtained, and when cutting in the first direction X, the number of cuts can be effectively reduced. Thereby, manufacturing costs, labor and time are reduced.
Specifically, the test structure includes: a first gate oxide layer 121 on the pixel test region PT; forming a second gate oxide layer 122 on the logic test region LT and on the first gate oxide layer 121; a plurality of gates 130 disposed on the second gate oxide layer 122, and the gates 130 are disposed on the pixel test region PT and the logic test region LT, respectively.
In this embodiment, the pixel test gate structure 150 includes: the first gate oxide layer 121, the second gate oxide layer 122 on the first gate oxide layer 121, and the gate 130 on the pixel test region PT.
In this embodiment, the logic test gate structure 160 includes: a second gate oxide layer 122 on the logic test region LT, and a gate electrode 130 on the logic test region LT.
In this embodiment, the material of the first gate oxide layer 121 and the second gate oxide layer 122 each include silicon oxide, and the material of the gate 130 includes polysilicon.
In this embodiment, the test structure further includes: a first sidewall 141 on a sidewall surface of the gate electrode 130 on the pixel test region PT; and a second sidewall 142 located on the first sidewall 141 and a sidewall surface of the gate 130 above the logic test region LT. Also, the pixel test gate structure 150 further includes: the first side wall 141, and a second side wall 142 located on a side wall surface of the first side wall 141. The logic test gate structure 160 further includes: and a second sidewall 142 positioned on a sidewall surface of the gate 130 above the logic test region LT. Thus, the structures available for inspection in the test structure are further increased to better reduce manufacturing costs, labor and time.
In this embodiment, the material of the first sidewall spacers 141 includes an oxide.
Specifically, the material of the first sidewall 141 includes silicon oxide.
In this embodiment, the second side wall includes: a lower second sidewall (not shown), and an upper second sidewall (not shown) on the surface of the lower second sidewall.
In this embodiment, the material of the lower second sidewall spacer includes an oxide, and the material of the upper second sidewall spacer includes a nitride. Specifically, the material of the lower second sidewall includes silicon oxide, and the material of the upper second sidewall includes silicon nitride.
In this embodiment, the test structure further includes: a contact blocking layer 170 on the surfaces of the gate 130 and the second sidewall 142 on the pixel test region PT and on the surface of the pixel test region PT, the contact blocking layer 170 exposing the gate 130 on the logic test region LT and the surface of the logic test region LT; a contact layer 180 on the top of the gate 130 on the logic test region LT and on at least a portion of the surface of the logic test region LT on both sides of the logic test gate structure 160 in the first direction X. Thus, the structures available for inspection in the test structure are further increased to better reduce manufacturing costs, labor and time.
In this embodiment, the contact barrier layer 170 includes: a lower contact barrier layer (not shown), and an upper contact barrier layer (not shown) on the surface of the lower contact barrier layer. The material of the lower contact barrier layer comprises oxide, and the material of the upper contact barrier layer is nitride. Specifically, the material of the lower contact barrier layer comprises silicon oxide, and the material of the upper contact barrier layer is silicon nitride.
In the present embodiment, the material of the contact layer 180 includes metal silicide.
In this embodiment, the test structure further includes: an active region S located in the scribe line 101, the active region S extending in the first direction X and located in the logic test region LT and the pixel test region PT; the isolation structure 110, in the second direction Y, the isolation structure 110 penetrates the active region S between the adjacent logic test region LT and pixel test region PT. Thus, the structures available for inspection in the test structure are further increased to better reduce manufacturing costs, labor and time.
In the present embodiment, more than 2 active regions S independent of each other are formed in the second direction Y to further increase the number of test structures that can be cut for detection in one sample.
In other embodiments, only 1 active region S is formed.
The material of the isolation structure 110 is a dielectric material.
Specifically, the first gate oxide layer 121 and the second gate oxide layer 122 are both located on the active region S, the gate 130 crosses the active region S, and the contact layer 180 is located on the top of the gate 130 on the logic test region LT and on the surface of the active region S in the logic test region LT on both sides of the logic test gate structure 160 along the first direction X.
In this embodiment, the test structure further includes: and a plurality of conductive structures 190 respectively located on the top surface of the gate 130 of the pixel test region PT, the surface of the active region S in the pixel test region PT on both sides of the pixel test gate structure 150 along the first direction X, and the surface of the contact layer 180. Thus, the structures available for inspection in the test structure are further increased to better reduce manufacturing costs, labor and time.
In this embodiment, the conductive structure 190 is a conductive plug, and the material of the conductive structure 190 includes tungsten.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (22)

1. A test structure, comprising:
the cutting path of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas, wherein the pixel test areas and the logic test areas are alternately arranged in a first direction;
the pixel test gate structure is positioned on the pixel test area, and the extending direction of the pixel test gate structure is vertical to the first direction;
and the extension direction of the logic test gate structure is vertical to the first direction.
2. The test structure of claim 1, comprising: a first gate oxide layer on the pixel test region; a second gate oxide layer on the logic test region and on the first gate oxide layer; the grid electrodes are arranged on the second grid oxide layer, and the grid electrodes are arranged on the pixel test area and the logic test area respectively; and, the pixel test gate structure includes: the first gate oxide layer, the second gate oxide layer located on the first gate oxide layer, and the gate located on the pixel test region, the logic test gate structure includes: the second gate oxide layer is positioned on the logic test area, and the grid electrode is positioned on the logic test area.
3. The test structure of claim 2, further comprising: the first side wall is positioned on the side wall surface of the grid electrode on the pixel test area; the second side wall is positioned on the first side wall and the side wall surface of the grid electrode on the logic test area; and, the pixel test gate structure further comprises: the first side wall and be located the second side wall of the side wall face of first side wall, logic test gate structure still includes: and the second side wall is positioned on the side wall surface of the grid electrode on the logic test area.
4. The test structure of claim 3, further comprising: the contact blocking layer is positioned on the surfaces of the grid electrode and the second side wall on the pixel test area and the surface of the pixel test area, and the grid electrode on the logic test area and the surface of the logic test area are exposed out of the contact blocking layer; and the contact layer is positioned on the top of the grid electrode on the logic test area and on at least part of the surface of the logic test area on two sides of the logic test grid structure along the first direction.
5. The test structure of claim 4, further comprising: an active region located in the scribe line, the active region extending along the first direction and located in the logic test region and the pixel test region, and the first gate oxide layer and the second gate oxide layer are located on the active region, and the gate electrode crosses the active region; and the isolation structure penetrates through the active area between the adjacent logic test area and the pixel test area in the direction perpendicular to the first direction.
6. The test structure of claim 5, further comprising: the conductive structures are respectively positioned on the top surface of the grid electrode of the pixel test area, the surface of the active area in the pixel test area at two sides of the pixel test grid structure along the first direction, and the surface of the contact layer.
7. The test structure of claim 3, wherein a material of the first sidewall spacer comprises an oxide.
8. The test structure of claim 3, wherein the second sidewall comprises: the second side wall of lower floor and be located upper second side wall on lower floor's second side wall surface.
9. The test structure of claim 8, wherein the material of the lower second sidewall spacer comprises an oxide and the material of the upper second sidewall spacer comprises a nitride.
10. The test structure of claim 4, wherein the contact barrier layer comprises: the lower layer is in contact with the barrier layer, and the upper layer is in contact with the barrier layer and is positioned on the surface of the lower layer.
11. The test structure of claim 10, wherein the material of the lower contact barrier layer comprises an oxide and the material of the upper contact barrier layer is a nitride.
12. A method of forming a test structure according to any of claims 1 to 11, comprising:
providing a substrate, wherein a cutting path of the substrate comprises a plurality of pixel test areas and a plurality of logic test areas, and the pixel test areas and the logic test areas are alternately arranged in a first direction;
forming a pixel test gate structure on the pixel test area, wherein the extending direction of the pixel test gate structure is perpendicular to the first direction;
and forming a logic test gate structure on the logic test area, wherein the extension direction of the logic test gate structure is vertical to the first direction.
13. The method of forming a test structure of claim 12, wherein the method of forming the pixel test gate structure and the logic test gate structure comprises: forming a first gate oxide layer on the pixel test region; forming a second gate oxide layer on the logic test region and the first gate oxide layer; and forming a plurality of gates on the second gate oxide layer, wherein the gates are respectively arranged on the pixel test region and the logic test region.
14. The method of forming a test structure of claim 13, wherein forming a first gate oxide layer over the pixel test region comprises: forming a first gate oxide film on the logic test area and the pixel test area; forming a first mask layer on the pixel test area, wherein the first mask layer exposes the first gate oxide film on the logic test area; etching the first gate oxide film by taking the first mask layer as a mask until the exposed first gate oxide film is removed to form the first gate oxide layer; and removing the first mask layer after the first gate oxide layer is formed and before the second gate oxide layer is formed.
15. The method of forming a test structure of claim 13, wherein the method of forming the pixel test gate structure and the logic test gate structure further comprises: forming a first side wall on the side wall surface of the grid electrode on the pixel test area; forming a second side wall on the first side wall and the side wall surface of the grid electrode on the logic test area; and the first gate oxide layer, the second gate oxide layer positioned on the first gate oxide layer, the gate positioned on the pixel test region, the first side wall, and the second side wall positioned on the side wall surface of the first side wall form the pixel test gate structure, and the second gate oxide layer positioned on the logic test region, the gate positioned on the logic test region, and the second side wall positioned on the side wall surface of the gate positioned on the logic test region form the logic test gate structure.
16. The method for forming a test structure according to claim 15, wherein the step of forming the first sidewall on the sidewall surface of the gate over the pixel test region comprises: forming an initial first side wall layer on the side wall surfaces of the grid electrodes on the logic test area and the pixel test area; forming a second mask layer on the grid electrode on the pixel test area and the initial first side wall layer, wherein the second mask layer exposes the initial first side wall layer on the logic test area; etching the initial first side wall layer by taking the second mask layer as a mask until the exposed initial first side wall layer is removed to form the first side wall; and after the first side wall is formed and before the second side wall is formed, removing the second mask layer.
17. The method of forming a test structure as claimed in claim 16, wherein the step of forming an initial first sidewall layer on the sidewall surfaces of the gate electrode over the logic test area and the pixel test area comprises: forming a first side wall film on the surface of the logic test area, the surface of the pixel test area and the surfaces of the gates on the logic test area and the pixel test area; and etching the first side wall film by adopting an anisotropic etching process until the first side wall film on the surfaces of the logic test area, the pixel test area and the top surfaces of the gates on the logic test area and the pixel test area is removed.
18. The method for forming a test structure according to claim 15, wherein the method for forming the second sidewall spacers on the first sidewall spacers and the sidewall surfaces of the gates in the logic test area comprises: forming a second side wall film on the gate and the first side wall surface on the pixel test area, the gate surface on the logic test area, the logic test area surface and the pixel test area surface; and etching the second side wall film by adopting an anisotropic etching process until the first side wall and the grid top surface on the pixel test area, the grid top surface on the logic test area, the surface of the logic test area and the second side wall film on the surface of the pixel test area are removed.
19. The method of forming a test structure of claim 15, further comprising, after forming the pixel test gate structure and the logic test gate structure: forming a contact barrier layer on the surfaces of the grid electrode and the second side wall on the pixel test area and the surface of the pixel test area, wherein the contact barrier layer exposes the grid electrode on the logic test area and the surface of the logic test area; after the contact barrier layer is formed, a contact layer is formed on the top of the grid electrode on the logic test area and at least part of the surface of the logic test area on two sides of the logic test grid structure along the first direction.
20. The method of forming a test structure of claim 19, further comprising, prior to forming the first gate oxide layer: forming an active area and an isolation structure in the scribe line, wherein the active area extends along the first direction and is located in the logic test area and the pixel test area, and the isolation structure penetrates through the active area between the adjacent logic test area and the pixel test area in a direction perpendicular to the first direction; the first gate oxide layer and the second gate oxide layer are located on the active region, and the gate electrode crosses the active region.
21. The method of forming a test structure of claim 20, further comprising: after the contact layer is formed, a plurality of conductive structures are formed on the top surface of the grid electrode of the pixel test area, the surfaces of the active areas on two sides of the pixel test grid structure along the first direction and the surface of the contact layer.
22. The method of forming a test structure of claim 12, wherein the substrate further comprises a chip region for forming a chip, the method of forming a test structure further comprising: forming a pixel unit circuit in the chip area, and forming the pixel test gate structure in the process of forming the pixel unit circuit; logic circuits are formed in the chip area, and the logic test gate structures are formed in the process of forming the logic circuits.
CN202111538755.3A 2021-12-15 2021-12-15 Test structure and forming method thereof Pending CN114242607A (en)

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