CN114242608A - Forming method of semiconductor structure, online detection method and test structure - Google Patents
Forming method of semiconductor structure, online detection method and test structure Download PDFInfo
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- CN114242608A CN114242608A CN202111538766.1A CN202111538766A CN114242608A CN 114242608 A CN114242608 A CN 114242608A CN 202111538766 A CN202111538766 A CN 202111538766A CN 114242608 A CN114242608 A CN 114242608A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
A forming method, an online detection method and a test structure of a semiconductor structure are provided, wherein the online detection method comprises the following steps: detecting the film thickness of the buffer film on the test structure area; and judging whether the material of the precursor film on the chip area is remained or not according to the film thickness of the buffer film on the test structure area. Thus, the loss of wafer fabrication is reduced.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure, an on-line detection method and a test structure.
Background
In current semiconductor manufacturing processes, forming an opening in an interlayer dielectric layer using an etching process, and then forming a conductive structure in the opening for electrical connection between semiconductor devices is a widely used process.
In order to reduce the contact resistance, metal (precursor layer) is generally deposited on the surface of the substrate and the surface of the gate structure before the interlayer dielectric layer is formed, and the precursor layer is in contact with the surface of the substrate where the conductive structure is located and the top surface of the gate structure. And then, carrying out a rapid annealing process to enable the precursor layer to react with the contacted substrate and the contacted grid electrode to form metal silicide, and removing the unreacted precursor layer.
When the unreacted deposited metal (precursor layer) is not completely removed but remains on the sidewall surface of the gate structure, since the deposited metal generally has a strong conductive property, during the operation of the semiconductor device, breakdown easily occurs between the conductive structure and the adjacent gate (as shown in fig. 1), which causes bridging between the conductive structure and the adjacent gate (as shown in region S in fig. 1), and thus the device is shorted.
In the prior art, the residual condition of the unreacted deposited metal is generally monitored in the Wafer Acceptance Test (WAT) and yield Test (CP Test) stages. However, the wafer receiving test and the yield test are delayed in time, so that it is difficult to find out the unqualified residual situation in the wafer manufacturing process in time, which results in a large loss of wafer manufacturing.
Disclosure of Invention
The invention aims to provide a forming method of a semiconductor structure, an on-line detection method and a test structure, which can realize the on-line detection of the residual condition of a precursor film and reduce the loss of wafer manufacture.
In order to solve the above technical problem, an aspect of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a chip area and a test structure area located in a cutting channel of the substrate, a grid structure is arranged on the chip area, and the grid structure comprises a grid oxide layer, a grid located on the grid oxide layer and a grid side wall located on the side wall of the grid; forming a precursor film on the surface of the gate structure, the surface of the chip region and the surface of the test structure region, wherein the precursor film contains a metal element, and the precursor film is in contact with the top surface of the gate, part of the surface of the chip region and the surface of the test structure region; after the precursor film is formed, carrying out first annealing treatment, and enabling materials of the top surface of the grid electrode, the partial surface of the chip area and the surface of the test structure area which are in contact with the precursor film to react with the precursor film to form a contact layer; removing the unreacted precursor film after forming the contact layer; and after removing the unreacted precursor film, forming a buffer film on the surface of the grid structure, the surface of the chip area and the surface of the test structure area.
Optionally, the method further includes: after removing the unreacted precursor film and before forming the buffer film, performing a second annealing treatment, wherein the temperature of the second annealing treatment is higher than that of the first annealing treatment.
Optionally, a source-drain structure is provided in a chip region on at least one side of the gate structure along a first direction, and a part of a surface of the chip region in contact with the precursor layer includes a surface of the source-drain structure, the first direction is perpendicular to an extending direction of the gate structure, and during the first annealing treatment, the precursor film reacts with a material on the surface of the source-drain structure to form the contact layer.
Optionally, the method further includes: forming a contact barrier layer on the substrate surface and the gate structure surface before forming the precursor film, and the contact barrier layer exposing the top surface of the gate, a portion of the surface of the chip region, and a surface of the test structure region in contact with the precursor film.
Optionally, the buffer film includes a lower buffer film and an upper buffer film located on the surface of the next buffer film.
Optionally, the material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.
Optionally, the material of the precursor film comprises NiPt.
Optionally, the material of the precursor film further comprises TiN.
Optionally, the material of the contact layer includes a metal silicide.
Correspondingly, the technical solution of the present invention further provides an online inspection method for a semiconductor structure formed by the above semiconductor structure forming method, including: detecting the film thickness of the buffer film on the test structure area; and judging whether the material of the precursor film on the chip area is remained or not according to the film thickness of the buffer film on the test structure area.
Optionally, the method for judging whether the material of the precursor film on the chip area remains according to the film thickness of the buffer film on the test structure area includes: acquiring a monitoring film thickness deviation according to the film thickness of the buffer film on the test structure area and a preset film thickness; judging whether the material of the precursor film on the chip area is residual or not according to the monitored film thickness deviation; when the monitored film thickness deviation is within a first preset deviation range, judging that no material of a precursor film on the chip area remains; and when the thickness deviation of the monitored film exceeds the first preset deviation range, judging that the material of the precursor film on the chip area has residue.
Optionally, the first predetermined deviation range is 0 to 2.5 angstroms.
Optionally, the method for detecting the film thickness of the buffer film on the test structure region includes: designating a plurality of sampling locations on a buffer film on the test structure area; and detecting a plurality of film thicknesses of a plurality of sampling positions.
Optionally, the method for obtaining the deviation of the monitored film thickness according to the film thickness of the buffer film on the test structure area and the preset film thickness includes: acquiring initial film thickness deviation corresponding to each sampling position according to the deviation between the film thickness of each sampling position and the preset film thickness; and acquiring the initial film thickness deviation with the maximum deviation from a plurality of initial film thickness deviations corresponding to a plurality of sampling positions as the monitored film thickness deviation.
Optionally, the method for obtaining the deviation of the monitored film thickness according to the film thickness of the buffer film on the test structure area and the preset film thickness includes: obtaining an average film thickness according to the film thicknesses of the sampling positions; and acquiring the deviation of the monitored film thickness according to the deviation between the average film thickness and the preset film thickness.
Optionally, the method for obtaining the deviation of the monitored film thickness according to the film thickness of the buffer film on the test structure area and the preset film thickness includes: and acquiring the thickness deviation of the monitored film according to the deviation between the film thickness of any sampling position and the preset film thickness.
Optionally, an optical film thickness measuring device is used to detect the film thickness of the buffer film on the test structure region.
Correspondingly, the technical solution of the present invention further provides a test structure formed by using the above method for forming a semiconductor structure, including: the test structure area is positioned in the cutting channel of the substrate, a contact layer is arranged in the test structure area, and the surface of the contact layer is exposed in the test structure area; and the buffer film is positioned on the surface of the contact layer of the test structure area.
Optionally, the buffer film includes a lower buffer film and an upper buffer film located on the surface of the next buffer film.
Optionally, the material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the forming method of the test structure provided by the technical scheme of the invention, a precursor film is formed on the surface of the grid structure, the surface of the chip area and the surface of the test structure area, the precursor film contains metal elements, and the precursor film is in contact with the top surface of the grid, part of the surface of the chip area and the surface of the test structure area; after the precursor film is formed, carrying out first annealing treatment, and enabling materials of the top surface of the grid electrode, the partial surface of the chip area and the surface of the test structure area which are in contact with the precursor film to react with the precursor film to form a contact layer; removing the unreacted precursor film after forming the contact layer; and after removing the unreacted precursor film, forming a buffer film on the surface of the grid structure, the surface of the chip area and the surface of the test structure area. On the one hand, the surface roughness of the substrate and the surface of the grid structure under the buffer film when the precursor film is remained is larger than that when no precursor film is remained, so that the buffer film formed when the precursor film is remained is thinner and has larger deviation with the preset film thickness compared with the condition that no precursor film is remained. On the other hand, since the processes of forming the precursor film and removing the unreacted precursor film are kept consistent on the chip region and the test structure region, and the process of forming the buffer film is also kept consistent on the chip region and the test structure region, after the unreacted precursor film is removed, the residual condition of the precursor film on the surface of the test structure region is kept consistent with the residual condition of the precursor film on the surface of the chip region and the surface of the gate structure, and the buffer film formed on the surface of the test structure region and the buffer films formed on the surface of the chip region and the surface of the gate structure are also consistent. Therefore, the residual condition of the materials of the precursor films on the surface of the chip area and the surface of the grid structure can be judged according to the film thickness of the buffer film on the test structure area. Meanwhile, the buffer film with the planar structure is formed on the surface of the test structure area, so that the difficulty of online detection of the film thickness of the buffer film on the test structure area is low. Therefore, the residual conditions of the materials of the precursor films on the surfaces of the chip area and the grid structure can be judged with low on-line detection difficulty through the contact layer in the test structure area and the buffer film on the test structure area, and further, the loss of wafer manufacturing is reduced.
Drawings
FIG. 1 is a schematic diagram of a bridge between a conductive structure and an adjacent gate when breakdown occurs;
FIGS. 2 to 9 are schematic structural diagrams illustrating steps in a method for forming a test structure according to an embodiment of the present invention;
FIG. 10 is a schematic flow chart of a method of on-line detection according to an embodiment of the invention;
FIG. 11 is a diagram illustrating an exemplary method for detecting a thickness of a buffer film on a test structure region according to an embodiment of the present invention.
Detailed Description
As described in the background, in the prior art, the residual of the unreacted deposited metal (precursor layer) is typically monitored during the Wafer Acceptance Test (WAT) and yield Test (CP Test) stages. However, the wafer receiving test and the yield test are delayed in time, so that it is difficult to find out the unqualified residual situation in the wafer manufacturing process in time, which results in a large loss of wafer manufacturing.
In order to solve the above technical problems, an aspect of the present invention provides a method for forming a semiconductor structure, a method for on-line inspection, and a test structure, in which a thickness of a buffer film on a test structure region is detected, and whether a material of a precursor film on a chip region in the semiconductor structure formed by the method for forming a semiconductor structure remains is determined according to the thickness of the buffer film on the test structure region, thereby reducing a loss in wafer manufacturing.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 9 are schematic structural diagrams of steps in a method for forming a test structure according to an embodiment of the invention.
Referring to fig. 2, a substrate 100 is provided, wherein the substrate 100 includes a chip region a and a test structure region B located in a scribe line (not shown) of the substrate 100.
The chip region a is used to form a chip.
The dicing street surrounds the chip region a, and by dicing the dicing street, the chip region a can be separated from the substrate 100 without damaging the chip region a, thereby forming an independent chip.
The material of the substrate 100 includes a semiconductor material.
Specifically, the material of the substrate 100 in this embodiment includes silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In the present embodiment, the chip region a has a gate structure 110 thereon, and at least one side of the gate structure 110 has a source/drain structure 120 in the chip region a in the first direction X. Wherein the first direction X is perpendicular to the extending direction of the gate structure 110.
In this embodiment, the gate structure 110 includes: the gate oxide layer 111, the gate 112 located on the surface of the gate oxide layer 111, and the gate sidewall 113 located on the sidewall surface of the gate 112.
The gate oxide layer 111 is made of silicon oxide, the gate 112 is made of polysilicon, and the gate sidewall 113 is made of a dielectric material.
The source drain structure 120 may be a doped region or an epitaxial layer.
Next, a contact barrier layer (SAB) is formed on the surface of the substrate 100 and the surface of the gate structure 110, and the contact barrier layer exposes the top surface of the gate 112, a part of the surface of the chip region a (including the surface of the source/drain structure 120), and the surface of the test structure region B.
The contact barrier layer is used for: the surface of the area of the substrate 100, where the contact layer is not required to be formed, is isolated from the precursor layer to be formed later, so as to prevent the reaction between the material on the surface of the area and the precursor layer, and achieve the purpose of not forming the contact layer in the area.
Therefore, by exposing the top surface of the gate 112, part of the surface of the chip region a (including the surface of the source/drain structure 120), and the contact barrier layer on the surface of the test structure region B, on one hand, the top surface of the gate 112, part of the surface of the chip region a (including the surface of the source/drain structure 120), and the surface of the test structure region B can be contacted with a precursor layer formed subsequently to form a contact layer, and at the same time, the contact layer is not formed in the rest region of the substrate 100. Please refer to fig. 3 to 4 for steps of forming the contact barrier layer.
Referring to fig. 3, an initial contact barrier layer 130 is formed on the surface of the substrate 100 and the surface of the gate structure 110.
The formation process of the initial barrier contact layer 130 includes a chemical vapor deposition process.
Referring to fig. 4, a mask layer (not shown) is formed on the surface of the initial contact blocking layer 130, and the mask layer exposes the surface of the initial contact blocking layer 130 on the gate structure 110, on a portion of the chip region a, and on the test structure region B; the initial contact barrier layer 130 is etched by using the mask layer as a mask until the top surface of the gate 112, a portion of the surface of the chip region a, and the surface of the test structure region B are exposed, thereby forming a contact barrier layer (not shown).
In this embodiment, the portion of the surface of the chip region a exposed by the contact blocking layer at least includes the surface of the source/drain structure 120.
In this embodiment, the contact barrier layer also exposes the surface of the gate sidewall spacer 113.
The material of the contact barrier layer is a dielectric material. The mask layer is made of photoresist.
In this embodiment, the process of etching the initial contact barrier layer 130 includes: at least one of a dry etching process and a wet etching process.
In this embodiment, after the contact barrier layer is formed, the mask layer is removed.
Referring to fig. 5, after the contact barrier layer is formed, a precursor film 140 is formed on the surface of the gate structure 110, the surface of the chip region a, and the surface of the test structure region B, the precursor film 140 includes a metal element, and the precursor film 140 is in contact with the top surface of the gate 112, a portion of the surface of the chip region a, and the surface of the test structure region B.
In this embodiment, a portion of the surface of the chip region a in contact with the precursor film 140 at least includes the surface of the source/drain structure 120.
The process of forming the precursor film 140 includes: chemical vapor deposition processes, physical vapor deposition processes, electroplating processes, atomic layer deposition processes, or the like.
In the present embodiment, the material of the precursor film 140 at least includes NiPt.
Preferably, the material of the precursor film 140 further includes TiN.
Referring to fig. 6, a first annealing process is performed to react materials of the top surface of the gate electrode 112, a portion of the surface of the chip region a, and the surface of the test structure region B, which are in contact with the precursor film 140, with the precursor film 140 to form a contact layer 150.
Specifically, during the first annealing treatment, the precursor film 150 reacts with the material on the surface of the source/drain structure 120.
The contact layer 150 is used to reduce contact resistance and improve conductivity of a subsequently formed conductive structure.
The material of the contact layer 150 includes a metal silicide.
Specifically, the material of the contact layer 150 includes NiSi.
Referring to fig. 7, after the contact layer 150 is formed, the unreacted precursor film 140 is removed.
In the present embodiment, the process of removing the unreacted precursor film 140 includes: and (5) wet cleaning process.
The isotropic wet cleaning process enables a higher etching selectivity for each location to better clean the unreacted precursor film 140 and reduce the material residue of the precursor film 140.
It should be noted that, in the actual process of manufacturing the semiconductor structure, the precursor film 140 may be left with material due to unclean cleaning.
Referring to fig. 8, after removing the unreacted precursor film 140, a second annealing process is performed, wherein the temperature of the second annealing process is higher than that of the first annealing process.
Therefore, after the contact layer 150 is formed through the first annealing treatment, the second annealing treatment with higher temperature is performed, on one hand, the material of the contact layer 150 is subjected to phase change, and on the other hand, the interface state expression of the contact layer 150 is favorably improved, so that the resistance of the contact layer 150 is further reduced, and the conductivity of a subsequently formed conductive structure is better improved.
Referring to fig. 9, after the second annealing process, a buffer film 160 is formed on the surface of the gate structure 110, the surface of the chip region a, and the surface of the test structure region B.
Since the precursor film 140 is formed on the surface of the gate structure 110, the surface of the chip area a, and the surface of the test structure area B, the precursor film 140 contains a metal element, and the precursor film 140 is in contact with the top surface of the gate 112, a part of the surface of the chip area a, and the surface of the test structure area B, then, a first annealing process is performed to react materials of the top surface of the gate 112, the part of the surface of the chip area a, and the surface of the test structure area B, which are in contact with the precursor film 140, with the precursor film 140 to form the contact layer 150, then, the unreacted precursor film 140 is removed, and after removing the unreacted precursor film 140, the buffer film 160 is formed on the surface of the gate structure 110, the surface of the chip area a, and the surface of the test structure area B.
Therefore, on the one hand, the surface roughness of the substrate 100 and the gate structure 110 under the buffer film 160 is larger when the material of the precursor film 140 is left than when the material is not left, so that the buffer film 160 formed when the material of the precursor film 140 is left is thinner and has a larger deviation from the predetermined film thickness than when the material is left.
On the other hand, the processes of forming the precursor film 140, removing the unreacted precursor film 140, and forming the buffer film 160 are consistent on the chip area a and the test structure area B, so that after removing the unreacted precursor film 140, the material of the precursor film 140 on the surface of the contact layer 150 of the test structure area B is consistent with the material of the precursor film 140 on the surface of the chip area a and the surface of the gate structure 110, and the buffer film 160 formed on the surface of the test structure area B and the buffer film 160 formed on the surface of the chip area a and the surface of the gate structure 110 are also consistent.
Accordingly, the material of the precursor film 140 remaining on the surface of the chip region a and the surface of the gate structure 110 can be determined according to the film thickness of the buffer film 160 on the test structure region B. Meanwhile, since the buffer film 160 of the planar structure is formed on the surface of the test structure region B, the difficulty of performing online detection of the film thickness of the buffer film 160 on the test structure region B is low (easy to measure).
Therefore, the contact layer 150 and the buffer film 160 in the test structure region B can determine the residual condition of the material of the precursor film 150 on the surface of the chip region a and the surface of the gate structure 110 with low on-line detection difficulty, and further, the loss of wafer manufacturing is reduced.
In other embodiments, the second annealing treatment is not performed, and the buffer film is directly formed after removing the unreacted precursor film 140.
In this embodiment, the process of forming the buffer film 160 includes: chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, or the like.
Preferably, the buffer film 160 is formed using a chemical vapor deposition process.
In this embodiment, the buffer film 160 includes a lower buffer film (not shown) and an upper buffer film (not shown) on the surface of the next buffer film. Wherein the material of the lower buffer film comprises SiN, and the material of the upper buffer film comprises SiON.
In this embodiment, after the buffer film is formed, the semiconductor structure is subjected to an in-line inspection to determine whether the material of the precursor film 140 remains on the chip area a.
When the residual semiconductor structure is judged, the operation of the production line in which the residual semiconductor structure is positioned is stopped, and the steps of checking, cleaning and the like are carried out on the equipment on the production line, so that the residual precursor film 140 can be found in time, the situation that the residual semiconductor structure produced on the production line subsequently is generated can be reduced, and the wafer manufacturing loss is reduced.
When no residue is determined, a contact hole process (CT) is used to form a conductive structure (not shown) on the surface of the source/drain structure 120 and the top surface of the gate 112. Wherein the material of the conductive structure comprises tungsten.
Fig. 10 is a flow chart illustrating a method of online detection according to an embodiment of the invention.
Accordingly, an embodiment of the present invention further provides a method for performing an on-line inspection on the semiconductor structure, please refer to fig. 10 in conjunction with fig. 9, which includes:
step S100, detecting the film thickness of the buffer film on the test structure area;
and step S200, judging whether the material of the precursor film on the chip area is residual or not according to the film thickness of the buffer film on the test structure area.
The following detailed description is made with reference to the accompanying drawings.
Referring to fig. 11, fig. 11 is a schematic diagram illustrating the detection of the film thickness of the buffer film on the test structure region according to an embodiment of the present invention, and the detection of the film thickness of the buffer film 160 on the test structure region B.
In this embodiment, the method for detecting the film thickness of the buffer film 160 on the test structure region B includes: designating a number of sampling locations (not shown) on the buffer film 160 on the test structure zone B; several film thicknesses H at several sampling positions are detected.
For convenience of explanation and understanding, fig. 11 schematically shows any one of the sampling positions and the film thickness H corresponding to the sampling position.
It should be understood that there is a one-to-one correspondence between the sampling locations and the film thicknesses H. In addition, in practical application, technicians can specify the number and specific positions of the sampling positions according to requirements.
Since the buffer film 160 on the test structure region B is a planar structure, the film thickness H is easily detected by the optical film thickness measuring apparatus, so that the on-line detection is convenient and difficult.
Specifically, the film thickness of the buffer film 160 on the test structure region B in this embodiment includes: a plurality of film thicknesses H corresponding to the plurality of sampling positions one by one.
In the present embodiment, an optical film thickness measuring apparatus is used to detect the film thickness of the buffer film 160 on the test structure region B. Specifically, the optical film thickness measuring device is used for detecting the film thicknesses H.
Referring to fig. 11, it is determined whether the material of the precursor film 140 on the chip area a remains according to the thickness of the buffer film 160 on the test structure area B.
Thus, the presence of the material of the precursor film 140 on the sidewall of the conductive opening 131 is determined by detecting the film thickness of the buffer film 160 on the test structure region B on line. Meanwhile, the difficulty of detecting the film thickness of the buffer film 160 on the test structure region B on line is low (easy to measure). Thus, the loss of wafer fabrication can be reduced. For a detailed explanation of the principles, reference is made to the related descriptions in the embodiments of the method for forming the semiconductor structure, which are not repeated herein.
In this embodiment, the method for determining whether the material of the precursor film 140 on the chip area a remains according to the film thickness of the buffer film 160 on the test structure area B includes: acquiring a monitored film thickness deviation according to the film thickness and the preset film thickness of the buffer film 160 on the test structure area B; judging whether the material of the precursor film 140 on the chip area A is remained or not according to the monitored film thickness deviation; when the monitored film thickness deviation is within a first preset deviation range, judging that no material of the precursor film 140 on the chip area A remains; when the thickness deviation of the monitored film exceeds the first preset deviation range, the material of the precursor film 140 on the chip area a is judged to be residual.
Preferably, the first predetermined deviation ranges from 0 angstroms to 2.5 angstroms.
In this embodiment, the method for obtaining the deviation of the monitored film thickness according to the film thickness of the buffer film 160 on the test structure region B and the preset film thickness includes: acquiring initial film thickness deviation corresponding to each sampling position according to the deviation between the film thickness H of each sampling position and the preset film thickness; and acquiring the initial film thickness deviation with the maximum deviation from a plurality of initial film thickness deviations corresponding to a plurality of sampling positions as the monitored film thickness deviation.
By acquiring the initial film thickness deviation with the maximum deviation from the initial film thickness deviations corresponding to the sampling positions as the monitored film thickness deviation, whether the material of the precursor film 140 on the chip area a is remained can be more accurately judged.
In another embodiment, the method for obtaining the deviation of the monitored film thickness according to the film thickness of the buffer film 160 on the test structure region B and the preset film thickness includes: obtaining an average film thickness according to the film thicknesses H of the sampling positions; and acquiring the deviation of the monitored film thickness according to the deviation between the average film thickness and the preset film thickness. Thus, it is advantageous to more accurately determine whether the material of the precursor film 140 remains on the chip area a.
In another embodiment, the method for obtaining the deviation of the monitored film thickness according to the film thickness of the buffer film 160 on the test structure region B and the preset film thickness includes: and acquiring the thickness deviation of the monitored film according to the deviation between the film thickness H at any sampling position and the preset film thickness. Therefore, the online detection time is reduced, and the manufacturing efficiency is improved.
It should be understood by those skilled in the art that the in-line inspection method provided in the present embodiment and the formation method of the foregoing semiconductor structure are complementary in specific implementation principle and logic. Therefore, the term explanation in the present embodiment may refer to the related description of the method for forming the semiconductor structure, and will not be repeated herein.
Accordingly, an embodiment of the present invention further provides a test structure formed by the method for forming a semiconductor structure, please refer to fig. 9, which includes: a test structure region B located in a scribe line (not shown) of the substrate 100, the test structure region B having a contact layer 150 therein, the test structure region B exposing a surface of the contact layer 150; and a buffer film 160 located on the surface of the contact layer 150 in the test structure region B.
The test structure is used for on-line testing to determine whether the material of the precursor film 140 on the chip area a remains.
The material of the substrate 100 includes a semiconductor material. Specifically, the material of the substrate 100 in this embodiment includes silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, the buffer film 160 includes a lower buffer film (not shown) and an upper buffer film (not shown) on the surface of the next buffer film. Wherein the material of the lower buffer film comprises SiN, and the material of the upper buffer film comprises SiON.
It should be understood by those skilled in the art that the test structure provided in the present embodiment, the forming method of the semiconductor structure and the on-line detection method are complementary to each other in terms of specific implementation principles and logic. Therefore, the terms used in the present embodiment may refer to the formation method of the semiconductor structure and the related description of the on-line inspection method, and are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a chip area and a test structure area located in a cutting channel of the substrate, a grid structure is arranged on the chip area, and the grid structure comprises a grid oxide layer, a grid located on the grid oxide layer and a grid side wall located on the side wall of the grid;
forming a precursor film on the surface of the gate structure, the surface of the chip region and the surface of the test structure region, wherein the precursor film contains a metal element, and the precursor film is in contact with the top surface of the gate, part of the surface of the chip region and the surface of the test structure region;
after the precursor film is formed, carrying out first annealing treatment, and enabling materials of the top surface of the grid electrode, the partial surface of the chip area and the surface of the test structure area which are in contact with the precursor film to react with the precursor film to form a contact layer;
removing the unreacted precursor film after forming the contact layer;
and after removing the unreacted precursor film, forming a buffer film on the surface of the grid structure, the surface of the chip area and the surface of the test structure area.
2. The method of forming a semiconductor structure of claim 1, further comprising: after removing the unreacted precursor film and before forming the buffer film, performing a second annealing treatment, wherein the temperature of the second annealing treatment is higher than that of the first annealing treatment.
3. The method for forming a semiconductor structure according to claim 1, wherein a source/drain structure is provided in a chip region on at least one side of the gate structure along a first direction, and a portion of a surface of the chip region in contact with the precursor layer includes a surface of the source/drain structure, the first direction is perpendicular to an extending direction of the gate structure, and the precursor film reacts with a material of the surface of the source/drain structure to form the contact layer during the first annealing treatment.
4. The method of forming a semiconductor structure of claim 1, further comprising: forming a contact barrier layer on the substrate surface and the gate structure surface before forming the precursor film, and the contact barrier layer exposing the top surface of the gate, a portion of the surface of the chip region, and a surface of the test structure region in contact with the precursor film.
5. The method of claim 1, wherein the buffer film comprises a lower buffer film and an upper buffer film on a surface of a next buffer film.
6. The method of forming a semiconductor structure according to claim 5, wherein a material of the lower buffer film includes SiN, and a material of the upper buffer film includes SiON.
7. The method of forming a semiconductor structure of claim 1, in which a material of the precursor film comprises NiPt.
8. The method of forming a semiconductor structure of claim 7, wherein the material of the precursor film further comprises TiN.
9. The method of forming a semiconductor structure of claim 1, wherein a material of the contact layer comprises a metal silicide.
10. A method for performing on-line inspection of a semiconductor structure formed by the method of forming a semiconductor structure of any of claims 1-9, comprising:
detecting the film thickness of the buffer film on the test structure area;
and judging whether the material of the precursor film on the chip area is remained or not according to the film thickness of the buffer film on the test structure area.
11. The method for on-line testing as claimed in claim 10, wherein the method for determining whether the material of the precursor film on the chip area remains based on the film thickness of the buffer film on the test structure area comprises: acquiring a monitoring film thickness deviation according to the film thickness of the buffer film on the test structure area and a preset film thickness; judging whether the material of the precursor film on the chip area is residual or not according to the monitored film thickness deviation; when the monitored film thickness deviation is within a first preset deviation range, judging that no material of a precursor film on the chip area remains; and when the thickness deviation of the monitored film exceeds the first preset deviation range, judging that the material of the precursor film on the chip area has residue.
12. The method of on-line testing as defined in claim 11, wherein said first predetermined deviation is in the range of 0 angstroms to 2.5 angstroms.
13. The method for on-line inspection according to claim 11, wherein the method for inspecting the film thickness of the buffer film on the test structure region comprises: designating a plurality of sampling locations on a buffer film on the test structure area; and detecting a plurality of film thicknesses of a plurality of sampling positions.
14. The method for on-line inspection according to claim 13, wherein the method for obtaining the deviation of the monitored film thickness based on the film thickness of the buffer film on the test structure region and the preset film thickness comprises: acquiring initial film thickness deviation corresponding to each sampling position according to the deviation between the film thickness of each sampling position and the preset film thickness; and acquiring the initial film thickness deviation with the maximum deviation from a plurality of initial film thickness deviations corresponding to a plurality of sampling positions as the monitored film thickness deviation.
15. The method for on-line inspection according to claim 13, wherein the method for obtaining the deviation of the monitored film thickness based on the film thickness of the buffer film on the test structure region and the preset film thickness comprises: obtaining an average film thickness according to the film thicknesses of the sampling positions; and acquiring the deviation of the monitored film thickness according to the deviation between the average film thickness and the preset film thickness.
16. The method for on-line inspection according to claim 13, wherein the method for obtaining the deviation of the monitored film thickness based on the film thickness of the buffer film on the test structure region and the preset film thickness comprises: and acquiring the thickness deviation of the monitored film according to the deviation between the film thickness of any sampling position and the preset film thickness.
17. The in-line inspection method of claim 10, wherein an optical film thickness measurement device is used to inspect the film thickness of the buffer film on the test structure area.
18. A test structure formed by the method of forming a semiconductor structure of any of claims 1-9, comprising:
the test structure area is positioned in the cutting channel of the substrate, a contact layer is arranged in the test structure area, and the surface of the contact layer is exposed in the test structure area;
and the buffer film is positioned on the surface of the contact layer of the test structure area.
19. The test structure of claim 18, wherein the buffer film comprises a lower buffer film and an upper buffer film on a surface of a next buffer film.
20. The test structure of claim 19, wherein the material of the lower buffer film comprises SiN and the material of the upper buffer film comprises SiON.
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| CN116936475A (en) * | 2023-09-15 | 2023-10-24 | 粤芯半导体技术股份有限公司 | Method for manufacturing semiconductor device |
| CN116936475B (en) * | 2023-09-15 | 2023-12-22 | 粤芯半导体技术股份有限公司 | Method for manufacturing semiconductor device |
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