CN114242594A - Surrounding gate device, back gate single diffusion isolation process method thereof and device preparation method - Google Patents
Surrounding gate device, back gate single diffusion isolation process method thereof and device preparation method Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a back grid single diffusion partition process method on a ring grid device, wherein the etching of a dummy grid for forming a single diffusion partition cavity is carried out after the preparation of an active metal grid of a GAA device is finished, and a source/drain region applies stress to fin structures on two sides; after the channel is released, only the channel layer is left in the fin structure corresponding to the active dummy gate, so that the stress of the source/drain region is concentrated on the channel layer, and the stress of the channel layer is enhanced. At the moment, the dummy gate and the corresponding fin structure are not processed, so that the dummy gate can transfer stress to the channel layer of the GAA device, and the stress of the channel layer of the GAA device is maximized; meanwhile, before the etching of the dummy grid, the channel layer of the GAA device is wrapped by the active metal grid, and the channel layer has a confining effect on the stress of the channel layer, so that the influence of the stress of the channel layer of the GAA device caused by relaxation is reduced to the minimum after the subsequent etching of the dummy grid.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a ring gate device, a back gate single diffusion isolation process method thereof and a device preparation method.
Background
Transistor devices are understood to be switching structures made of semiconductor materials. As semiconductor technology evolves, transistor devices evolve from planar transistors to FinFET transistors to gate-all-around transistors. A gate-all-around transistor may also be understood as a GAA transistor, GAAFET. Wherein, GAA is called as: Gate-All-Around Gate technology.
For an N-type transistor and a P-type transistor, the mobility of carriers is different, so that the current capacities of the N-type transistor and the P-type transistor are different under the same size. For a planar transistor, the electron mobility of an N-type transistor is almost twice as high as the hole mobility of a P-type transistor, and the carrier mobility of an N-type transistor channel and the carrier mobility of a P-type transistor channel are adjusted by a source-drain germanium-silicon (SiGe) stress technology of the planar transistor. With the development of the FinFE transistor, the carrier mobility of the N-type transistor is not much different from that of the P-type transistor. When the transistor is developed into a GAA transistor, the electron mobility of an N-type transistor is greatly improved, and the hole mobility of a P-type transistor is reduced, so that the carrier mobility of the N-type GAA transistor and the carrier mobility of the P-type GAA transistor are greatly different. Thus, when integrating N-type GAA transistors and P-type GAA transistors, the current matching problem is very prominent. At the same time, the sensitivity of hole mobility to stress increases and the sensitivity of electron mobility to stress decreases, which increases the stress requirements on the GAA transistor.
Below the 7nm technology node, Single Diffusion Break (SDB) has replaced Double Diffusion Break (DDB) to further increase transistor density. Both conventional SDB and self-aligned SDB (SA-SDB) schemes cause channel stress relaxation to varying degrees.
Therefore, how to solve the problem of stress relaxation in the single diffusion blocking process has become an urgent technical problem in the industry.
Disclosure of Invention
The invention provides a ring gate device, a back gate single diffusion partition process method thereof and a device preparation method, which are used for reducing stress relaxation in a single diffusion partition process and improving device performance.
According to a first aspect of the present invention, a back gate single diffusion isolation process method on a gate-all-around device is provided, which includes:
providing a substrate structure;
forming a plurality of fin structures on the substrate structure, wherein the fin structures are distributed on the substrate structure along a first direction, and a shallow trench isolation structure is arranged between every two adjacent fin structures; each fin structure of the plurality of fin structures includes a sacrificial layer and a channel layer that are alternately stacked;
forming a plurality of dummy gate structures on each fin structure along a second direction, the dummy gate structures crossing over the corresponding fin structures; the dummy gate structure comprises a dummy gate and an active dummy gate; the second direction is perpendicular to the first direction;
performing source/drain etching on the fin structure by taking the pseudo gate structure as a mask to form a source/drain cavity;
extending a source/drain layer in the source/drain cavity to form a source/drain region;
removing the active dummy gate and the sacrificial layer in the fin structure corresponding to the active dummy gate, and releasing a channel;
forming an active metal gate;
etching the dummy gate and the fin structure covered by the dummy gate until part of the substrate structure is etched away to form a single diffusion partition cavity; and
and forming a diffusion isolation layer in the single diffusion partition cavity.
Optionally, the forming of the plurality of fin structures on the substrate structure specifically includes:
forming a stack on the substrate structure, the stack including sacrificial layers and channel layers alternately stacked;
and etching the stack to form a fin structure.
Optionally, before performing source/drain etching on the fin structure by using the gate structure as a mask to form a source/drain cavity, the method further includes: a spacer layer is deposited over the dummy gate structure.
Optionally, extending the source/drain layer in the source/drain cavity, before forming the source/drain region, the method further includes:
etching the sacrificial layer exposed on the surface after the source and drain etching to make part of the sacrificial layer sunken;
an inner spacer layer is formed in the recessed region.
Optionally, extending the source/drain layer in the source/drain cavity, and after forming the source/drain region, the method further includes:
and depositing an interlayer dielectric on the substrate structure, wherein the interlayer dielectric covers the source/drain region.
Optionally, the forming of the active metal gate specifically includes:
depositing a high dielectric constant dielectric on the channel layer after the channel is released; and
a metal gate is deposited on the high-k dielectric.
According to a second aspect of the present invention, a method for manufacturing a gate all around device is also provided, which includes the above-mentioned back-gate single diffusion isolation process method on the gate all around device.
Optionally, the method for manufacturing a gate-all-around device further includes, after forming the diffusion isolation layer in the single diffusion isolation cavity: forming device contacts.
According to the third aspect of the invention, the invention also provides a gate-all-around device which is prepared by adopting the preparation method of the gate-all-around device.
The invention provides a back grid single diffusion partition process method on a ring grid device, wherein the etching of a dummy grid for forming a single diffusion partition cavity is carried out after the active metal grid of a GAA device is prepared, and because a source/drain region can apply stress to fin structures at two sides (the fin structure corresponding to the active dummy grid and the fin structure corresponding to the dummy grid); after the channel is released, only the channel layer is left in the fin structure corresponding to the active dummy gate, so that the stress of the source/drain region is concentrated on the channel layer, and the stress of the channel layer is enhanced. At the moment, the dummy gate and the corresponding fin structure are not processed, so that the dummy gate can transfer stress to the channel layer of the GAA device, and the stress of the channel layer of the GAA device is maximized; meanwhile, the channel layer of the GAA device is wrapped by the active metal grid before the etching of the dummy grid, and the high-dielectric-constant dielectric material in the active metal grid is not easy to deform, so that the stress of the channel layer is restrained, and the influence of the stress of the channel layer of the GAA device caused by the relaxation is reduced to the minimum after the subsequent etching of the dummy grid. The stress relaxation problem in the existing single diffusion partition process is effectively solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a first schematic flow chart of a back-gate single-diffusion isolation process method on a gate-all-around device according to an embodiment of the present invention;
fig. 2 is a second schematic flow chart illustrating a back-gate single-diffusion isolation process method on a gate-all-around device according to an embodiment of the present invention;
fig. 3 to fig. 15 are partial schematic views of device structures corresponding to steps of a back-gate single diffusion isolation process method on a gate-all-around device according to an embodiment of the present invention.
Fig. 16 is a graph of stress simulation effect for steps of the back gate single diffusion barrier process method of the present invention and the conventional single diffusion barrier process and self-aligned single diffusion barrier process for P-type GAA devices;
fig. 17 is a schematic structural diagram of a complete device prepared by the back gate single diffusion partition process method.
Description of reference numerals:
1-local device repeatable unit;
101-a substrate structure;
a 110-fin structure;
111-a sacrificial layer;
112-a channel layer;
130-dummy gate stack;
131-an active dummy gate;
132-dummy gate;
140-a spacer layer;
150-source/drain cavity;
141-an inner spacer layer;
151-source/drain layer;
160-interlayer dielectric;
170-high K gate dielectric;
180-a diffusion barrier layer;
A-A, B-B-Cross section line;
a-stress simulation curves corresponding to each step of the traditional single diffusion partition process;
b, stress simulation curves corresponding to each step of the self-aligned single diffusion partition process;
c-stress simulation curves corresponding to all steps of the back gate single diffusion partition process method.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "upper surface", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
In the description of the present invention, "a plurality" means a plurality, e.g., two, three, four, etc., unless specifically limited otherwise.
In the description of the present invention, unless otherwise explicitly specified or limited, the terms "connected" and the like are to be construed broadly, e.g., as meaning fixedly attached, detachably attached, or integrally formed; can be mechanically connected, electrically connected or can communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Before the invention is provided, the applicant makes full research on the single diffusion isolation process of the GAA device of the advanced node, and the current single diffusion isolation process aiming at the GAA device mainly comprises the following steps:
one, traditional single diffusion partition process
The specific process of the process comprises the following steps:
a. epitaxial fin structure stack (sacrificial layer/channel layer alternating) on substrate structure;
b. patterning the fin structure stack;
c. etching the fin structure and cutting off the fin structure to form the fin structure and a single diffusion partition cavity;
d. filling the isolation layer to form STI and a diffusion isolation layer;
e. forming a dummy gate on the fin structure;
f. etching source/drain and forming source/drain area;
g. forming an interlayer dielectric;
h. removing the dummy gate;
i. removing the sacrificial layer and releasing the channel;
j. forming a high-K gate dielectric;
k. forming a metal contact.
Two, self-aligning single diffusion partition process
Compared with the traditional process, the process puts the step of forming the single diffusion partition cavity between the step of forming the interlayer dielectric and the step of removing the dummy gate, and other process steps are similar to the traditional process.
For GAA devices, the stress of the source/drain regions on the channel layer is critical to the performance of the device. For both processes, the applicants have found that there is a different degree of stress relaxation. To clarify the origin of stress relaxation, applicants conducted a series of stress simulations, and found that in both processes, after forming the single diffusion barrier cavity, the stress is relaxed to different degrees, so that the stress of the final channel layer is maintained at a low level.
After the applicant further tracks stress simulation of each process step and studies and analyzes, the two processes mentioned above are found to cause stress relaxation because: in the two processes, free surfaces are formed at two ends of the channel layer when the single diffusion partition cavity is formed, and stress is relaxed by the channel on the free surfaces, so that the stress of the final channel layer is lower.
Based on this, the applicant has creatively proposed a new back gate single diffusion isolation process method on a gate-all-around device aiming at the needs of the GAA device, please refer to fig. 1 in combination with fig. 3 to fig. 15, wherein fig. 1 is a schematic flow chart of the back gate single diffusion isolation process method on the gate-all-around device according to an embodiment of the present invention; fig. 3 to fig. 15 are schematic device structures corresponding to steps of a back-gate single diffusion isolation process method on a gate-all-around device according to an embodiment of the present invention. Wherein fig. 4 is a cross-sectional view of fig. 3 taken along cross-sectional line B-B, fig. 5 is a cross-sectional view of fig. 3 taken along cross-sectional line a-a, and fig. 6-15 are device structure diagrams at different process steps shown on the basis of fig. 5.
With reference to fig. 1, fig. 3 to fig. 15, the method for processing back gate single diffusion and isolation on a gate-all-around device according to the embodiment of the present invention includes the following steps:
s1, a substrate structure 101 is provided.
The substrate structure 101 may be a silicon substrate or a Strain Relaxed Buffer (SRB), or may be other substrates. Substrate structures that meet the requirements of GAA devices are within the scope of the invention.
S2, forming a plurality of fin structures 110 on the substrate structure 101, wherein the plurality of fin structures 110 are arranged on the substrate structure 101 along a first direction, as shown in fig. 3; the first direction in fig. 3 can be understood as the direction perpendicular to the channel direction of the final GAA device and the second direction can be understood as the direction along the channel of the final GAA device, so that the first direction is perpendicular to the second direction.
Wherein a Shallow Trench Isolation (STI) structure 120 is disposed between each adjacent fin structure 110, and each fin structure 110 of the plurality of fin structures includes a sacrificial layer 111 and a channel layer 112 that are alternately stacked, as shown in fig. 4.
Four fin structures are shown as an example in fig. 3 and 4, and in fact, after this step is completed, a plurality of fin structures, not limited to four, may be formed on the underlying structure.
In a specific embodiment, the forming a plurality of fin structures on a substrate structure further comprises:
forming a stack including a sacrificial layer 111 and a channel layer 112 alternately stacked on the substrate structure 101;
the stack is subjected to a fin structure etch to form fin structure 110. And adjacent fin structures 110 are isolated from each other by shallow trench isolation structures 120.
S3: forming a plurality of dummy gate structures on each fin structure along a second direction, the dummy gate structures crossing over the corresponding fin structures; the dummy gate structure includes a dummy gate 132 and an active dummy gate 131, as shown in fig. 6.
Specifically, step S3 may include the following sub-steps:
first, a plurality of dummy gate stacks 130 are formed on each fin structure along the second direction, as shown in fig. 5; the dummy gate stack 130 spans the corresponding fin structure, specifically, the dummy gate stack 130 covers the top and both sides of the fin structure;
next, the dummy gate stack 105 is etched to form a plurality of dummy gate structures, as shown in fig. 6; the plurality of dummy gate structures are sequentially distributed along the second direction. The dummy gate structure may be divided into a dummy gate 132 and an active dummy gate 131 according to the function of the dummy gate structure, wherein the dummy gate 132 is etched to form a single-diffusion isolation cavity; the active dummy gate 131 is etched to form an active metal gate. The dummy gate structure may be made of a metal gate material, and specifically, different metal gate materials may be used according to the type of ions doped in the corresponding region.
As a preferred embodiment, as shown in fig. 2, after forming a plurality of dummy gate structures, the method further includes step S31: a spacer layer 140 is deposited on the dummy gate structure, and the device structure after this step is shown in fig. 7.
S4: performing source/drain etching on the fin structure by using the dummy gate structure as a mask to form a source/drain cavity 150; the structure of the device after etching is shown in fig. 8.
As a preferred embodiment, as shown in FIG. 2, after the step S4, the method further includes the steps of S41 forming an inner spacer layer; specifically, step S41 includes the following sub-steps:
etching the sacrificial layer 111 exposed on the surface after the source-drain etching to make part of the sacrificial layer sunken;
forming an inner spacer layer 141 in the recess region; the schematic diagram of the device structure after this step is completed is shown in fig. 9.
S5: source/drain regions 151 are formed by epitaxial source/drain layers within the source/drain cavities 150.
As a preferred embodiment, as shown in fig. 2, after forming the source/drain regions 151, the method further includes step S51: depositing an interlayer dielectric 160; the method specifically comprises the following steps:
depositing an interlayer dielectric 160 on the substrate structure, the interlayer dielectric 160 covering the source/drain regions 151;
the deposited interlayer dielectric 160 is planarized, and in particular, chemical mechanical polishing may be performed to planarize the deposited interlayer dielectric 160. The schematic diagram of the device structure after this step is completed is shown in fig. 10.
S6: the sacrificial layer 111 in the fin structure corresponding to the active dummy gate 131 and the active dummy gate 131 is removed, and channel release is performed. Specifically, this step includes the following substeps:
removing the active dummy gate 131, and the schematic diagram of the device structure after this step is completed is shown in fig. 11; wherein, the active dummy gate 131 may be removed by an etching process;
removing the sacrificial layer 111 in the corresponding fin structure, and the device structure after this step is completed is schematically shown in fig. 12; wherein the sacrificial layer 111 may be removed by an etching process.
S7: and forming an active metal gate. The method specifically comprises the following steps:
depositing a high-k dielectric 170 on the channel layer 112 after the channel is released; the schematic diagram of the device structure after this step is completed is shown in fig. 13; and
a metal gate (not shown) is deposited over the high-k dielectric 170.
The high-k dielectric 170 may be formed of a conventional high-k dielectric material.
S8: etching the dummy gate 132 and the fin structure covered by the dummy gate until part of the substrate structure is etched away to form a single diffusion partition cavity; the schematic diagram of the device structure after this step is completed is shown in fig. 14; and
forming a diffusion isolation layer 180 in the single diffusion partition cavity; the schematic diagram of the device structure after this step is completed is shown in fig. 15. The diffusion isolation layer 180 may be an insulating layer, such as silicon dioxide.
The invention provides a back grid single diffusion partition process method on a ring grid device, wherein the etching of a dummy grid for forming a single diffusion partition cavity is carried out after the active metal grid of a GAA device is prepared, and because a source/drain region can apply stress to fin structures at two sides (the fin structure corresponding to the active dummy grid and the fin structure corresponding to the dummy grid); after the channel is released, only the channel layer is left in the fin structure corresponding to the active dummy gate, so that the stress of the source/drain region is concentrated on the channel layer, and the stress of the channel layer is enhanced. At the moment, the dummy gate and the corresponding fin structure are not processed, so that the dummy gate can transfer stress to the channel layer of the GAA device, and the stress of the channel layer of the GAA device is maximized; meanwhile, the channel layer of the GAA device is wrapped by the active metal grid before the etching of the dummy grid, and the high-dielectric-constant dielectric material in the active metal grid is not easy to deform, so that the stress of the channel layer is restrained, and the influence of the stress of the channel layer of the GAA device caused by the relaxation is reduced to the minimum after the subsequent etching of the dummy grid. The stress relaxation problem in the existing single diffusion partition process is effectively solved.
In order to compare with the existing single diffusion partition process, the applicant has performed stress simulation tracking on each corresponding step for each process method, please refer to fig. 16, in which a curve a is a stress simulation curve corresponding to each step of the conventional single diffusion partition process; the curve b is a stress simulation curve corresponding to each step of the self-aligned single diffusion partition process; the curve c is a stress simulation curve corresponding to each step of the back gate single diffusion partition process method; the ordinate of fig. 16 represents the magnitude of the stress, and the abscissa thereof represents the respective process steps; the SDB in the figure represents a single diffusion cutoff step (i.e., forming a single diffusion cutoff cavity). As can be seen from fig. 16, for the P-type GAA device, the stress level in curve a after SDB formation is around 1.5GPa, and the stress level of the subsequent channel layer is maintained around-1 GPa; in the curve b, after the SDB is formed, the stress of the SDB is about 1GPa, and the stress of a subsequent channel layer is maintained at about 0 GPa; in curve c, after the SDB is formed, the stress level is around-4.4 GPa, and the stress level of the subsequent channel layer is maintained around-4.4 GPa. Therefore, the channel stress is obviously improved by adopting the back gate single diffusion partition process method.
Similarly, for the N-type GAA device, the applicant also carries out stress simulation of each process step, and the channel stress is improved to about +3.2GPa by adopting the back gate single diffusion partition process method. A significant boost is also obtained.
It should be noted that fig. 3-fig. 15 only show the schematic structural diagrams of the local device prepared by the post-gate single-diffusion partition process method on the gate-around device according to the present invention, in practical cases, in the single-diffusion partition process, there are usually one or more active dummy gates between two dummy gates along the channel length direction. In the present application, a case where one active dummy gate exists between two dummy gates is schematically described, and referring to fig. 17, the partial device repeatable unit 1 in fig. 17 is the structure illustrated in fig. 3 to 15. The complete repeatable unit shown in fig. 17 is a structure in which one active dummy gate exists between two dummy gates; wherein the local device repeatable unit 1 is half of the complete repeatable unit.
According to a second aspect of the present invention, a method for manufacturing a gate all around device is also provided, which includes the above-mentioned back-gate single diffusion isolation process method on the gate all around device. In addition, the preparation method of the gate-all-around device further comprises the following steps after the diffusion isolation layer is formed in the single diffusion isolation cavity: forming device contacts.
According to the third aspect of the invention, the invention also provides a gate-all-around device which is prepared by adopting the preparation method of the gate-all-around device.
In the description herein, reference to the terms "an implementation," "an embodiment," "a specific implementation," "an example" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A back gate single diffusion partition process method on a ring gate device is characterized by comprising the following steps:
providing a substrate structure;
forming a plurality of fin structures on the substrate structure, wherein the fin structures are distributed on the substrate structure along a first direction, and a shallow trench isolation structure is arranged between every two adjacent fin structures; each fin structure of the plurality of fin structures includes a sacrificial layer and a channel layer that are alternately stacked;
forming a plurality of dummy gate structures on each fin structure along a second direction, the dummy gate structures crossing over the corresponding fin structures; the dummy gate structure comprises a dummy gate and an active dummy gate; the second direction is perpendicular to the first direction;
performing source/drain etching on the fin structure by taking the pseudo gate structure as a mask to form a source/drain cavity;
extending a source/drain layer in the source/drain cavity to form a source/drain region;
removing the active dummy gate and the sacrificial layer in the fin structure corresponding to the active dummy gate, and releasing a channel;
forming an active metal gate;
etching the dummy gate and the fin structure covered by the dummy gate until part of the substrate structure is etched away to form a single diffusion partition cavity; and
and forming a diffusion isolation layer in the single diffusion partition cavity.
2. The method according to claim 1, wherein the forming a plurality of fin structures on the substrate structure specifically comprises:
forming a stack on the substrate structure, the stack including sacrificial layers and channel layers alternately stacked;
and etching the stack to form a fin structure.
3. The method of claim 1, wherein before performing source/drain etching on the fin structure using the gate structure as a mask to form a source/drain cavity, the method further comprises: a spacer layer is deposited over the dummy gate structure.
4. The method of claim 1, wherein extending the source/drain layer in the source/drain cavity further comprises, before forming the source/drain region:
etching the sacrificial layer exposed on the surface after the source and drain etching to make part of the sacrificial layer sunken;
an inner spacer layer is formed in the recessed region.
5. The method of claim 1, wherein the step of extending a source/drain layer in the source/drain cavity further comprises, after forming a source/drain region:
and depositing an interlayer dielectric on the substrate structure, wherein the interlayer dielectric covers the source/drain region.
6. The method according to claim 5, wherein the forming of the active metal gate specifically comprises:
depositing a high dielectric constant dielectric on the channel layer after the channel is released; and
a metal gate is deposited on the high-k dielectric.
7. A method for preparing a gate-all-around device, comprising the back-gate single diffusion isolation process method on the gate-all-around device as claimed in any one of claims 1 to 6.
8. The method for manufacturing a gate-all-around device according to claim 7, further comprising, after forming the diffusion isolation layer in the single diffusion blocking cavity:
forming device contacts.
9. A gate-all-around device, characterized by being prepared by the method for preparing the gate-all-around device of claim 7.
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