CN114566549A - Semiconductor device having high driving capability and steep SS characteristic and method of manufacturing the same - Google Patents

Semiconductor device having high driving capability and steep SS characteristic and method of manufacturing the same Download PDF

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Publication number
CN114566549A
CN114566549A CN202210131205.8A CN202210131205A CN114566549A CN 114566549 A CN114566549 A CN 114566549A CN 202210131205 A CN202210131205 A CN 202210131205A CN 114566549 A CN114566549 A CN 114566549A
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gate
stack
layer
semiconductor
dielectric layer
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李永亮
程晓红
赵飞
罗军
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202210131205.8A priority Critical patent/CN114566549A/en
Publication of CN114566549A publication Critical patent/CN114566549A/en
Priority to US18/059,960 priority patent/US20230261050A1/en
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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Abstract

A semiconductor device and a method of manufacturing the same are disclosed. According to an embodiment, a semiconductor device may include: a substrate; a channel portion including: a first portion comprising a fin structure protruding relative to a substrate; a second portion above and spaced apart from the first portion comprising one or more nanowires or nanoplatelets spaced apart from one another; source/drain portions provided on opposite sides of the channel portion in the first direction and connected to the channel portion; and a gate stack extending in a second direction crossing the first direction on the substrate to cross the channel portion.

Description

Semiconductor device having high driving capability and steep SS characteristic and method of manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device having high drive capability and a steep sub-threshold swing (SS) and a method of fabricating the same.
Background
Fin field effect transistors (finfets) are currently the predominant device. However, as the devices are further scaled down, the gate control capability thereof is reduced, the short channel effect is deteriorated, which is expressed as a sub-threshold swing (SS) deterioration, the leakage current is increased, and especially, the power consumption of the devices in the switching process is increased. To improve device performance, nanowire or nanosheet ring-gate devices may be employed. Gate-all-around (GAA) devices, particularly nanowire-gate-around devices, have significantly improved SS, but their driving performance is reduced. To improve the driving performance, stacking of more nanowires (process difficulty) or juxtaposition of more devices (large footprint) is required.
Disclosure of Invention
In view of the above, it is an object of the present disclosure to provide a semiconductor device with high driving capability and a steep sub-threshold swing (SS) and a method for fabricating the same.
According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a channel portion including: a first portion comprising a fin structure protruding relative to a substrate; a second portion above and spaced apart from the first portion comprising one or more nanowires or nanoplatelets spaced apart from one another; source/drain portions provided on opposite sides of the channel portion in the first direction and connected to the channel portion; and a gate stack extending in a second direction crossing the first direction on the substrate to cross the channel portion.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: providing a ridge structure extending in a first direction on a substrate, wherein the ridge structure has a first stack of a first plurality of semiconductor layers at least at an upper portion; forming a dummy gate extending in a second direction crossing the first direction on the substrate to intersect the ridge structure; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer exposes the dummy gate; removing the dummy gate to form a gate trench in the interlayer dielectric layer; removing a portion of the semiconductor layer from the first stack of ridge structures in the gate trench to form one or more nanowires or nanoplates separated from each other, and a lower portion of the ridge structures being separated from the nanowires or nanoplates to form a fin structure; and forming a gate stack in the gate trench to intersect the nanowire or nanoplate and the fin structure.
According to another aspect of the present disclosure, there is also provided an electronic device including the above semiconductor device.
According to embodiments of the present disclosure, a semiconductor device may resemble a fin field effect transistor (FinFET) in a lower portion and a gate-all-around (GAA) nanowire or nanosheet device in an upper portion. In the switching process, the advantages of the upper GAA device can be utilized to obtain a steeper SS, so that the leakage current is reduced and the power consumption is reduced. And when the device is completely conducted, the lower FinFET and the upper GAA device can provide conducting current together, so that larger current is realized compared with the situation that the device completely adopts a GAA structure, and the driving performance of the device is improved. Accordingly, the semiconductor device or an Integrated Circuit (IC) chip including the same according to the embodiments of the present disclosure has improved performance in power consumption, speed, and the like. In addition, the manufacturing method according to the embodiment of the disclosure is compatible with a mainstream FinFET process, is not greatly different from a GAA device process, and can be realized by only adding a few process steps.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
fig. 1 to 11(c) schematically show some stages in a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 12(a) to 13(b) schematically show some stages in a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure;
figures 14 through 17 schematically illustrate some stages in a process for fabricating a semiconductor device according to yet another embodiment of the present disclosure,
wherein,
FIGS. 2(a), 2(b), 5(a), 6(a), 7(a), 11(a) are top views showing the positions of AA 'and BB' lines, respectively;
FIGS. 1, 3(a), 4(a), 5(b), 6(b), 7(b), 8(a), 9(a), 10(a), 11(b), 12(a), 13(a) are cross-sectional views taken along line AA';
fig. 3(b), 4(b), 5(c), 6(c), 7(c), 8(b), 9(b), 10(b), 11(c), 12(b), 13(b), 14 to 17 are sectional views along the line BB'.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required. In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
According to an embodiment of the present disclosure, a semiconductor device is provided. A semiconductor device according to an embodiment of the present disclosure may include a channel portion and source/drain portions on opposite sides of the channel portion. The source/drain portions may be electrically connected to each other through the channel portion. The channel portion may take different forms at the upper and lower portions, respectively. In particular, an upper portion of the channel portion may include nanowire or nanoplate(s) or spaced apart nanowire or nanoplate(s) from each other, while a lower portion of the channel portion may include a fin structure protruding with respect to the substrate. The fin structure may be unitary or a stack of multiple semiconductor layers, such as an alternating stack of two or more semiconductor layers. The nanowires or nanoplatelets in the upper portion of the channel portion may be of the same semiconductor material as the lower portion of the channel portion or a portion of the layers in the lower portion. In addition, the upper and lower portions of the channel portion may be self-aligned in the vertical direction.
The gate stack may be formed to intersect the channel portion. In one aspect, the gate stack may surround the upper nanowire or nanosheet of the channel portion, forming a gate-all-around (GAA) configuration, and thus may achieve a steeper sub-threshold swing (SS) characteristic. On the other hand, the gate stack may cover the sidewalls (and optionally the top surface) of the lower portion of the fin-shaped channel portion, thereby resembling a fin field effect transistor (FinFET) configuration and thus may achieve higher drive performance.
Such a semiconductor device can be manufactured, for example, as follows. A ridge structure extending in a first direction may be provided on the substrate. The ridge structure has, at least in the upper part, a stack of several semiconductor layers, for example an alternating stack of two (or more) semiconductor layers with etch selectivity with respect to each other, so that subsequently channel portions in the form of discrete nanoplates or nanoplates can be released in the upper part. The ridge structure may similarly be in the form of a semiconductor layer stack in the lower portion (which may have the same or similar configuration as the upper semiconductor layer stack, or may have a different configuration), or may be unitary.
A semiconductor device can be manufactured on the basis of such a ridge structure. Fabrication methods according to embodiments of the present disclosure may be compatible with mainstream FinFET processes because such ridge structures are similar to fins.
For example, a dummy gate extending in a second direction crossing (e.g., perpendicular to) the first direction may be formed on the substrate. The portion of the ridge structure covered by the dummy gate may then define a channel portion. Source/drain portions may be formed at opposite sides of the dummy gate in the first direction. For example, the source/drain portion may be formed by ion implantation into a portion of the ridge structure exposed by the dummy gate, or may be formed by etching the ridge structure with the dummy gate as a mask and additionally growing an epitaxial layer (which may be doped in situ when grown).
Thereafter, an interlayer dielectric layer may be formed on the substrate to cover the source/drain portions while exposing the dummy gate so as to perform a replacement gate process. In the replacement gate process, the dummy gate may be removed so that a gate groove may be formed in the interlayer dielectric layer and thus a portion of the ridge structure (a portion between the source/drain portions) previously covered by the dummy gate may be exposed to define the channel portion. Unlike in FinFET processes, one or more semiconductor layers may be released here on top of the ridge structure. Here, "releasing" may mean separating the respective semiconductor layers from other semiconductor layers between the source/drain portions. In this way, the subsequently formed gate stack may surround the released semiconductor layer. While the lower portion of the ridge structure may remain substantially unaffected and thus form a fin structure. The channel portion may then include a lower fin structure and one or more (separate from each other) nanowires or nanoplates above and separate from the fin structure.
The gate stack may be formed to intersect the channel portion. More specifically, the gate stack may be formed in the gate trench, and thus may surround the nanowire or the nanosheet on the upper portion of the channel portion, and may cover the top surface and the sidewalls (in the second direction) of the fin structure on the lower portion of the channel portion. Different configurations of gate stacks may be formed for upper and lower portions of the channel portion, respectively.
The present disclosure may be presented in various forms, some examples of which are described below. In the following description, reference is made to the selection of various materials. The choice of material takes into account the etch selectivity in addition to its function (e.g., semiconductor material for forming the active region, dielectric material for forming the electrical isolation). In the following description, the required etch selectivity may or may not be indicated. It will be clear to those skilled in the art that when etching a layer of material is referred to below, such etching may be selective if it is not mentioned that other layers are also etched or not shown, and the layer of material may be etch selective with respect to other layers exposed to the same etch recipe.
Fig. 1 to 11(c) schematically show some stages in a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure.
As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SO1) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation. Here, a silicon wafer is provided as the substrate 1001.
On substrate 1001, a plurality of stacked layers S may be formed1、S2、S3、S4Each stack comprising a stack of two or more semiconductor layers. For example, as shown in FIG. 1, a first stack S1May include a stack of a first semiconductor layer 1003-1 and a second semiconductor layer 1005-1, a second stack S2May include a stack of a first semiconductor layer 1003-2 and a second semiconductor layer 1005-2, a third stack S3May include a stack of a first semiconductor layer 1003-3 and a second semiconductor layer 1005-3, and a fourth stack S4A stack of a first semiconductor layer 1003-4 and a second semiconductor layer 1005-4 may be included. That is, the stack S is realized by the alternating arrangement of the first semiconductor layer and the second semiconductor layer in this example1、S2、S3、S4This is technically convenient.
Here, four stacks S are shown1、S2、S3、S4. However, the present disclosure is not limited thereto. For example, more or fewer stacks may be formed. In addition, two semiconductor layers are not limited to be included in each stack, and more semiconductor layers may be included. The thickness of the individual semiconductor layers in each stack may be the same or different, and the thickness of the semiconductor layers in different stacks may be the same or different.
Here, the lower M (in the example of fig. 1, M is 2) stacks (i.e., S)1And S2) May then be used to define the fins with the upper N (in the example of fig. 1, N-2) stacks (i.e., S)3And S4) Which can then be used to define nanowires or nanoplatelets. The values of M and N may be set differently according to device design.
These semiconductor layers may be formed on the substrate 1001 by, for example, epitaxial growth. Thus, each semiconductor layer can have good crystal quality and can be a single crystal structure. Adjacent ones of the semiconductor layersThere may be etch selectivity between bulk layers. Where substrate 1001 is a silicon wafer, each stack may be Si/Si1-xGexStack, Si/Ge stack, Si1-xGexa/Ge stack, etc. (0 < x < 1). For example, the first semiconductor layers 1003-1, 1003-2, 1003-3, 1003-4 may include Si1-xGex(0 < x < 1), and the second semiconductor layers 1005-1, 1005-2, 1005-3, 1005-4 may include Si. Typically, each semiconductor layer is not intentionally doped. According to other embodiments of the present disclosure, each semiconductor layer may also be doped in-situ during epitaxial growth to achieve certain doping characteristics. For example, the doping characteristics in the channel portions (subsequently formed by portions of these semiconductor layers) may enable the adjustment of the threshold voltage (Vt).
In this example, each stack has the same or similar configuration, e.g., each stack has two semiconductor layers, respective first semiconductor layers in each stack may be of the same material (and may be equal in thickness) and respective second semiconductor layers may also be of the same material (and may be equal in thickness). However, the present disclosure is not limited thereto. For example, there may be some of the stacked layers having different configurations, for example, different in at least one of the number of stacked semiconductor layers, the material of the semiconductor layers, and the thickness of the semiconductor layers. In particular, the lower M stacks (i.e., S)1And S2) With upper N stacks (i.e. S)3And S4) May have different configurations, even the lower M stacks may be realized by a single layer (e.g., Si layer).
The subsequent process can proceed as in the fabrication process of conventional GAA nanowire or nanosheet devices until the channel portion is released.
For example, as shown in fig. 2(a) and 2(b), a mask layer 1007a or 1007b may be formed on the above stack by patterning the mask layer 1007a or 1007b into the form of a nanowire (fig. 2(a)) or a nanosheet (fig. 2(b)), for example, a linear or stripe shape extending in the horizontal direction in the drawing (which may be referred to as "first direction"). For example, the mask layer 1007a or 1007b may include a photoresist or a hard mask (e.g., an oxide, a nitride, or a stack thereof), or the like. In the following description, the case of nanosheets is mainly taken as an example, but the descriptions are equally applicable to the case of nanowires.
Then, as shown in fig. 3(a) and 3(b), the layers on the substrate 1001 may be selectively etched in sequence by, for example, Reactive Ion Etching (RIE) in the vertical direction, self-aligned dual imaging technique (SADP), or the like, using the mask layer 1007a or 1007b as an etching mask. In addition, an etch may be performed into substrate 1001 to form a trench in substrate 1001 for subsequent isolation. Thus, each layer on the substrate 1001 is patterned into a ridge structure corresponding to the mask layer 1007a or 1007 b. Thereafter, the mask layer 1007a or 1007b may be removed as needed.
For electrical isolation purposes, as shown in fig. 4(a) and 4(b), an isolation 1009, such as a Shallow Trench Isolation (STI), may be formed on the substrate 1001, such as in a trench as described above. The isolation 1009 may achieve electrical isolation of the device, and may include, for example, an oxide (e.g., silicon oxide). For example, the isolation 1021 may be fabricated by depositing an oxide on the substrate 1001, subjecting the deposited oxide to a planarization process such as Chemical Mechanical Polishing (CMP), and subjecting the planarized oxide to an etch back process such as RIE.
As shown in fig. 5(a), 5(b), and 5(c), on the spacer 1009, a dummy fence 1011 extending in a second direction (e.g., a vertical direction within the paper plane in fig. 5(a), a direction perpendicular to the paper plane in fig. 5(b), a horizontal direction within the paper plane in fig. 5 (c)) intersecting (e.g., perpendicular to) the first direction may be formed so as to intersect the ridge structure. The dummy gate 1011 may include a material having an etch selectivity with respect to the ridge structure, such as polysilicon, amorphous silicon, or the like. The ridge structure may be ion implanted using the pattern of the dummy gate 1011 (typically having a hard mask formed thereon, not shown) as a mask to achieve the desired source/drain doping characteristics.
In addition, a sidewall spacer (not shown) may be formed on the sidewall of the dummy gate. The side wall and the manufacturing method thereof can be the same as those in the conventional technology, and are not described herein again.
As shown in fig. 6(a), 6(b), and 6(c), an interlayer dielectric layer 1013 may be formed on a substrate 1001. For example, the interlayer dielectric layer 1013 may be formed by depositing an oxide and subjecting the deposited oxide to a planarization process such as CMP. The CMP may stop at the dummy gate 1011 to expose the dummy gate 1011.
Here, the interlayer dielectric layer 1013 is directly formed so as to cover portions of the ridge structure on opposite sides (right and left sides in fig. 6(a) and 6 (b)) of the dummy gate 1011, and these covered ridge structure portions can then be used as source/drain portions of the device. However, the present disclosure is not limited thereto. For example, before forming the inter-level dielectric layer 1013, each stack may be selectively etched using the dummy gate 1011 (and the hard mask thereon and the sidewalls thereon) as a mask, so that each stack remains under the dummy gate 1011 (and the sidewalls thereon). Additional source/drain portions may be formed by epitaxial growth on the sidewalls of each stack on opposite sides of the dummy gate 1011. The material of the grown source/drain may be selected to achieve device performance optimization. For example, semiconductor materials having different lattice constants may be selected so as to apply stress to the channel portion realized by the respective stacked layers.
As shown in fig. 7(a), 7(b) and 7(c), the dummy gate 1011 can be removed by selective etching, thereby forming a gate groove (a space originally occupied by the dummy gate 1011) in the interlayer dielectric layer 1013. Thus, the portion of the ridge structure previously covered by the dummy gate 1011 can be exposed. This portion may be used to define the channel portion.
Next, an operation of releasing the channel portion may be performed. In a GAA nanowire or nanosheet device, to achieve a GAA configuration, a certain space needs to be freed around the channel portion in the form of a nanowire or nanosheet, so that a gate stack subsequently formed in this space can surround the channel portion in the form of a nanowire or nanosheet. This is the operation of the so-called "relief channel portion".
Unlike conventional GAA nanowire or nanosheet fabrication processes, in accordance with embodiments of the present disclosure, the operation of releasing the channel portion may be directed only to the upper N stacks (i.e., S)3And S4) Is performed without being directed to the lower M stacks (i.e., S)1And S2) The process is carried out. Note that the values of M and N may be set differently depending on device design, and may be smaller (e.g., 1) or larger.
To realize different processing for the upper and lower portions, a mask layer 1015 may be formed on the substrate as shown in fig. 8(a) and 8 (b). The mask layer 1015 may have an etch selectivity with respect to the interlayer dielectric layer 1013, the isolation portion 1009 (and the semiconductor layers in the ridge structure), for example, including Spin On Carbon (SOC), Advanced Patterning Film (APF), amorphous silicon, or the like. A mask layer 1015 may be formed within the gate trench. For example, a mask material may be deposited so as to sufficiently fill the space left in the interlayer dielectric layer 1013 due to the removal of the dummy gate 1011, and the deposited mask material may be subjected to a planarization process such as CMP, which may be stopped at the interlayer dielectric layer 1013, thereby forming the mask layer 1015.
Note that, in this embodiment, the mask layer 1015 is formed anew after the dummy gate 1011 is removed. However, the present disclosure is not limited thereto. For example, the dummy gate 1011 may be directly used as a mask without additionally forming the mask layer 1015. Alternatively, according to another embodiment, in the case where the etching recipe used in the operation of relieving the channel portion has selectivity to each semiconductor layer (or to a single semiconductor layer in the case where the lower portion is the single semiconductor layer) in the lower M stacks, the operation of relieving the channel portion may be directly performed after removing the dummy gate 1011 without forming a mask layer.
As shown in fig. 9(a) and 9(b), with the mask layer 1015 thus formed, it is possible to etch back so that its top surface is lowered, and thus to expose the upper N stacks (i.e., S)3And S4). The etch-back may employ a dry etching process such as RIE, or a wet etching process. The etch recipe used not only has a certain selectivity to the interlayer dielectric layer 1013, but also has a higher selectivity (e.g., greater than 20: 1) to the exposed stack. In the case where the mask layer 1015 includes amorphous silicon, wet etching may be performed using an alkaline solution such as ammonia water to achieve high selectivity.
In fig. 9(b), the top surface of the mask layer 1015' after etch back is shown (slightly) lower than the lower M stacks (i.e., S)1And S2) Top surface of the uppermost semiconductor layer 1005-2. This may result in an upper N stack (i.e., S)3And S4) Sufficiently exposed to release the channel portion.
Here, adjustment of M and N can be achieved by controlling the etch-back depth of the mask layer 1015. For example, if the etch-back depth is small, N is small and M is large; the etch-back depth is larger, N is larger and M is smaller. Here, M and N are both natural numbers greater than zero.
For exposed N stacks (i.e., S)3And S4) The channel portion may be released. For example, as shown in fig. 10(a) and 10(b), each stack S may be removed by selective etching3、S4While leaving at least one further semiconductor layer. For example, each stack S3、S4The first semiconductor layers 1003-3, 1003-4 may be removed and the second semiconductor layers 1005-3, 1005-4 may be left. In this way, the middle portion (the portion originally covered by the dummy gate 1011) of the second semiconductor layers 1005-3, 1005-4 may be formed in a suspended form, and thus a defined channel portion may be surrounded by the gate stack from all sides to form a GAA structure. The second semiconductor layers 1005-3, 1005-4 having the channel portions in the middle portion may have a suitable semiconductor material, for example, Si or Si as described above1-xGexIn Si1-xGexThe mobility is higher under the condition of (2), and the device performance is improved. Of course, the top N stacks (i.e., S) are considered for uniformity of device performance3And S4) May have the same configuration so that the same semiconductor layer of each of the N stacks may be released to define the channel portion.
Lower M stacks (i.e., S)1And S2) Covered by the mask layer 1015' may remain substantially unaffected and may form a fin structure protruding relative to the substrate 1001. Thereafter, the mask layer 1015' may be removed by selective etching. The selective etching may be dry etching or wet etching. For example, in the case of SOC or APF, oxygen plasma may be employed; in the case of amorphous silicon, an alkaline solution such as ammonia (e.g., about 60 to 70 ℃ C., a concentration of more than 1: 100) may be used.
Thereafter, a gate stack may be fabricated.
For example, as shown in fig. 11(a), 11(b), and 11(c), in the gate trench, a gate dielectric layer 1019 and a gate metal layer (e.g., including a work function adjusting layer 1021 and a gate conductor layer 1023) may be sequentially formed. For example, the gate dielectric layer 1019 may comprise a high-k gate dielectric such as HfO2、Al2O3、ZrO2Etc. or a stack thereof; the work function adjusting layer 1021 may include TiN, TiAlN, TaN, or the like or a stack thereof such as TiN/TaN/TiN, TiN/TaN/TiN/TiAlN/TiN, or the like; the gate conductor layer 1023 may include W, Co, Ru, or the like. An interfacial layer may also be formed prior to forming the high-k gate dielectric, such as an oxide formed by an oxidation process or deposition, such as Atomic Layer Deposition (ALD).
In addition, before fabricating the gate stack, inner sidewalls (not shown) may be formed on sidewalls of the upper first semiconductor layers 1003-3 and 1003-4 exposed by the operation of releasing the channel portion. The inner sidewall and the method for fabricating the same may be the same as those in the conventional art, and are not described herein again.
As shown by the dotted circle in fig. 11(c), the channel portion of the semiconductor device thus obtained may include two upper and lower portions: at the upper part, the channel parts are in the form of nano-sheets or nano-wires separated from each other, the number of nano-sheets or nano-wires is N, and the nano-sheets or nano-wires are respectively surrounded by the gate stacks, thereby forming a GAA configuration; in the lower portion, the channel portion is in the form of a fin structure protruding relative to the substrate 1001, and the gate stack surrounds the sidewalls and top surface of the fin structure, thereby resembling a FinFET configuration. Thus, on the one hand, a steeper SS characteristic can be achieved by the upper GAA configuration; on the other hand, with the FinFET configuration at the lower portion, enhancement of driving performance can be achieved. Also, the upper and lower portions of the semiconductor device are uniform in the fabrication process, except that a channel portion release operation is additionally performed for the upper portion.
In addition, as shown in fig. 11(b), the positions of the source/drain portion and the channel portion are schematically shown by dotted lines. Specifically, the channel portion is located in the middle, and the source/drain portions are located at opposite sides of the channel portion. Although the channel portion is different in form in the upper and lower portions as described above, the source/drain portions of the respective sides are integrated.
Since the channel portions are in different forms at the upper and lower portions, the configuration of the gate stack can also be optimized for the upper and lower portions in order to optimize device performance.
The gate stack (gate dielectric layer 1019/work function adjusting layer 1021/gate conductor layer 1023) formed above may be provided for the lower channel portion to achieve a certain equivalent work function or threshold voltage (Vt). Different gate stacks may be additionally provided for the upper channel portion, for example, at least one of the gate dielectric layer and the gate metal layer (including the work function adjusting layer and the gate conductor layer) may be different, so as to achieve a certain equivalent work function or threshold voltage (Vt). The entire semiconductor device may have a substantially uniform threshold voltage (Vt).
For example, as shown in fig. 12(a) and 12(b), the previously formed gate stack may be etched back to expose the upper channel portion. In this example, a case where both the gate dielectric layer 1019 and the gate metal layer (the work function adjusting layer 1021, the gate conductor layer 1023) are etched back is shown. However, the present disclosure is not limited thereto. For example, only the gate metal layer may be etched back, leaving the gate dielectric layer 1019.
Thereafter, as shown in fig. 13(a) and 13(b), another gate stack including a gate dielectric layer 1019 ' (which need not be additionally formed in the case where the gate dielectric layer 1019 is left) and a gate metal layer (including a work function adjusting layer 1021 ' and a gate conductor layer 1023 ') may be similarly formed in a space in the interlayer dielectric layer 1013 due to etch-back. In addition, the gate conductor layer 1023 'may include the same material as the gate conductor layer 1023, and adjustment of the work function or Vt is achieved by the work function adjustment layer 1021'.
In the case of forming the gate dielectric layer 1019 'additionally, the gate conductor layers formed twice in succession may be separated by the gate dielectric layer 1019'. The gate conductor layers may be connected to each other by interconnects in a subsequent metallization process.
In the above embodiments, the channel portion is released first, and then the gate stack is formed. However, the present disclosure is not limited thereto.
For example, as shown in fig. 14, the gate stack (the gate dielectric layer 1019/the work function adjusting layer 1021/the gate conductor layer 1023) may be directly formed without releasing the channel portion for the upper portion. Then, as shown in FIG. 15As shown, the gate stack can be etched back with its top surface down to expose the upper N stacks (i.e., S)3And S4). That is, in this embodiment, the gate stack may be used as a mask layer in the channel portion release operation without additionally forming the mask layer 1015 as described above. Here, the top surface of the gate stack (gate dielectric layer 1019 '/work function adjusting layer 1021 '/gate conductor layer 1023 ') after etch back may be (slightly) higher than the lower M stacks (i.e., S)1And S2) Top surface of the uppermost semiconductor layer 1009 so that the gate stack after etch back (gate dielectric layer 1019 "/work function adjusting layer 1021"/gate conductor layer 1023 ") can cover the entire sidewalls of the lower M stacks very well. As shown in fig. 16, for the exposed laminate, the channel portion can be released as described above. Thereafter, as shown in fig. 17, additional gate stacks may be formed, including a gate dielectric layer 1019 ', a work function adjusting layer 1021 ', and a gate conductor layer 1023 '. Here, the gate stacks formed successively may have the same configuration as each other or different configurations from each other.
The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, an Integrated Circuit (IC) may be formed based on such a semiconductor device, and an electronic apparatus may be constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device. The electronic device may also include components such as a display screen that cooperates with the integrated circuit and a wireless transceiver that cooperates with the integrated circuit. Such electronic devices are for example smart phones, computers, tablets, wearable smart devices, artificial smart devices, mobile power supplies, etc.
According to an embodiment of the present disclosure, there is also provided a method of manufacturing a system on chip (SoC). The method may include the above-described method. In particular, a variety of devices may be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.
In the above description, details of the techniques such as patterning and etching of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. Further, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (20)

1. A semiconductor device, comprising:
a substrate;
a channel portion including:
a first portion comprising a fin structure protruding relative to the substrate;
a second portion above and spaced apart from the first portion comprising one or more nanowires or nanoplatelets spaced apart from one another;
the source/drain parts are arranged on two opposite sides of the channel part in the first direction and are connected with the channel part; and
a gate stack extending in a second direction crossing the first direction on the substrate to intersect the channel part.
2. The semiconductor device according to claim 1, wherein the first part of the channel portion comprises a stack of a plurality of semiconductor layers.
3. The semiconductor device of claim 1, wherein the first portion of the channel portion comprises an alternating stack of first and second semiconductor layers, and the nanowires or nanoplates each comprise one of the first and second semiconductor layers.
4. The semiconductor device of claim 1, wherein the first portion and the second portion of the channel portion are self-aligned in a vertical direction.
5. The semiconductor device of claim 1, wherein the gate stack covers a top surface of a first portion of the channel portion and sidewalls opposite each other in the second direction and surrounds the nanowires or nanoplatelets of a second portion of the channel portion.
6. The semiconductor device of claim 1, wherein the gate stack comprises:
a first portion intersecting the first portion of the channel portion; and
a second portion intersecting a second portion of the channel portion.
7. The semiconductor device of claim 6,
the first part of the gate stack comprises a first gate dielectric layer and a first gate metal;
the second portion of the gate stack includes a second gate dielectric layer and a second gate metal,
the first gate dielectric layer is different from the second gate dielectric layer and/or the first gate metal is different from the second gate metal.
8. The semiconductor device of claim 6, wherein the first and second portions of the gate stack have different configurations to achieve the first and second portions of the channel portion having substantially the same threshold voltage.
9. The semiconductor device of claim 6, wherein a first portion of the gate stack covers a top surface of a first portion of the channel portion and sidewalls opposite each other in the second direction, and a second portion of the gate stack surrounds the nanowire or nanoplatelet.
10. The semiconductor device of claim 6, wherein a first portion of the gate stack covers sidewalls of the first portion of the channel portion that are opposite to each other in the second direction, and a second portion of the gate stack surrounds the nanowire or nanoplatelet and covers a top surface of the first portion of the channel portion.
11. The semiconductor device of claim 3,
the first semiconductor layer and the second semiconductor layer include Si and Si, respectively1-xGexOr comprises Si and Ge, respectively, or comprises Ge and Si, respectively1-xGexWherein x is more than 0 and less than 1,
the nano-wire or nano-sheet comprises Si and Si1-xGexOr Ge, wherein 0 < x < 1.
12. A method of manufacturing a semiconductor device, comprising:
providing a ridge structure extending in a first direction on a substrate, wherein the ridge structure has a first stack of a first plurality of semiconductor layers at least at an upper portion;
forming a dummy gate extending in a second direction crossing the first direction on the substrate to intersect the ridge structure;
forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer exposes the dummy gate;
removing the dummy gate, thereby forming a gate trench in the interlayer dielectric layer;
removing, in the gate trench, a portion of the semiconductor layer from the first stack of ridge-like structures to form one or more nanowires or nanoplates separated from each other, and a lower portion of the ridge-like structures being separated from the nanowires or nanoplates to form fin-like structures; and
forming a gate stack in the gate trench to intersect the nanowire or nanoplate and the fin structure.
13. The method of claim 12, wherein providing the ridge structure comprises:
forming one semiconductor layer or a second stack having a second plurality of semiconductor layers and forming the first stack on the one semiconductor layer or the second stack by epitaxial growth.
14. The method of claim 13, wherein the nanowires or nanoplatelets each comprise the same material as at least one of the one semiconductor layer or the second stack.
15. The method of claim 13, wherein the first and second stacks each comprise an alternating stack of first and second semiconductor layers, and the nanowires or nanoplates each comprise one of the first and second semiconductor layers.
16. The method of claim 12, wherein removing portions of the semiconductor layer from the first stack of ridge structures comprises:
forming a mask layer in the gate trench to shield a lower portion of the ridge structure;
removing the portion of the semiconductor layer from the first stack by selective etching; and
and removing the mask layer.
17. The method of claim 12, wherein forming a gate stack comprises:
and sequentially forming a first gate dielectric layer and a first gate metal layer in the gate groove.
18. The method of claim 17, further comprising:
recessing the first gate metal layer to expose the nanowires or nanoplatelets; and
a second gate metal layer is further formed in the gate trench to surround the nanowire or nanosheet.
19. The method of claim 18, wherein,
in the operation of exposing the nanowires or nanoplatelets, the method further comprises: recessing the first gate dielectric layer in a recess,
the method further comprises the following steps: and further forming a second gate dielectric layer in the gate groove, wherein the second gate metal layer is formed on the second gate dielectric layer.
20. The method of claim 12, wherein,
removing a portion of the semiconductor layer from the first stack of ridge structures comprises:
sequentially forming a first gate dielectric layer and a first gate metal layer in the gate groove;
recessing the first gate dielectric layer and the first gate metal layer to expose the first stack;
removing said part of the semiconductor layer from said first stack by selective etching, an
Forming the gate stack includes:
and further sequentially forming a second gate dielectric layer and a second gate metal layer in the gate groove so as to surround the nanowire or the nanosheet.
CN202210131205.8A 2022-02-11 2022-02-11 Semiconductor device having high driving capability and steep SS characteristic and method of manufacturing the same Pending CN114566549A (en)

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