CN114240913A - Semiconductor abnormality analysis method, semiconductor abnormality analysis device, terminal device, and storage medium - Google Patents
Semiconductor abnormality analysis method, semiconductor abnormality analysis device, terminal device, and storage medium Download PDFInfo
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Abstract
The invention discloses an abnormality analysis method of a semiconductor, which is used for terminal equipment and comprises the following steps: acquiring a binary thermodynamic diagram of a semiconductor to be analyzed; framing out a target area in the binary thermodynamic diagram by using a preset detection frame; determining a fitness function value corresponding to the target area; determining a result area in the binary thermodynamic diagram according to the fitness function value; and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area. The invention also discloses a semiconductor abnormity analysis device, terminal equipment and a storage medium. By using the method of the invention, the terminal equipment automatically utilizes the binary thermodynamic diagram to obtain the abnormal analysis result of the semiconductor to be analyzed, manual analysis is not needed, the analysis time is greatly reduced, and the analysis efficiency is improved.
Description
Technical Field
The present invention relates to the field of semiconductor analysis and detection technologies, and in particular, to a method and an apparatus for analyzing semiconductor anomalies, a terminal device, and a storage medium.
Background
Currently, in a semiconductor packaging scenario, a technician is required to manually perform an anomaly analysis on a semiconductor to obtain an analysis result, and then evaluate the packaging or manufacturing of the semiconductor according to the analysis result.
However, when the conventional method is used to analyze the abnormality of the semiconductor, the analysis efficiency is low.
Disclosure of Invention
The invention mainly aims to provide a semiconductor abnormality analysis method, a semiconductor abnormality analysis device, a terminal device and a storage medium, and aims to solve the technical problem that analysis efficiency is low when abnormality analysis is carried out on a semiconductor in the prior art.
In order to achieve the above object, the present invention provides an abnormality analysis method for a semiconductor, which is used for a terminal device, the method including the steps of:
acquiring a binary thermodynamic diagram of a semiconductor to be analyzed;
framing out a target area in the binary thermodynamic diagram by using a preset detection frame;
determining a fitness function value corresponding to the target area;
determining a result area in the binary thermodynamic diagram according to the fitness function value;
and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area.
Optionally, the semiconductor to be analyzed comprises a plurality of semiconductors; before the step of obtaining the binary thermodynamic diagram corresponding to the semiconductor to be analyzed, the method further includes:
acquiring a plurality of initial thermodynamic diagrams corresponding to a plurality of semiconductors to be analyzed;
performing a superposition operation on the plurality of initial thermodynamic diagrams to obtain a superposition thermodynamic diagram, wherein the superposition thermodynamic diagram comprises a plurality of unit areas, and each unit area corresponds to a plurality of heat force values;
obtaining a unit yield of each unit area according to the plurality of heat values of each unit area;
obtaining a mean value and a standard deviation of the unit yield rates according to the unit yield rates;
obtaining a binarization threshold value according to the mean value and the standard deviation;
and carrying out binarization processing on the superimposed thermodynamic diagram by using the binarization threshold value to obtain the binarization thermodynamic diagram.
Optionally, the step of determining the fitness function value corresponding to the target area includes:
determining the total area of the target region, the abnormal area of the abnormal region in the target region and the total abnormal area of the abnormal region in the binary thermodynamic diagram;
obtaining a first area ratio according to the abnormal area and the total area;
obtaining a second area ratio according to the abnormal area and the total abnormal area;
and obtaining a fitness function value corresponding to the target region by using the first area ratio and the second area ratio.
Optionally, the target area includes a plurality of target areas corresponding to a plurality of preset detection frames, and the fitness function value includes a plurality of fitness function values corresponding to a plurality of target areas; before the step of determining a result region in the binary thermodynamic diagram according to the fitness function value, the method further includes:
determining a plurality of initial selection fitness function values in the fitness function values;
when the iterated times do not reach the preset times, updating the iterated times;
carrying out inheritance, intersection or variation operation on the plurality of preset detection frames to obtain a plurality of new preset detection frames;
adjusting a plurality of primary selection target areas corresponding to the plurality of primary selection fitness function values by using a plurality of new detection frames to obtain a plurality of new target areas;
updating a plurality of target areas by using a plurality of new target areas, and returning to execute the step of obtaining the fitness function value corresponding to the target area according to the target areas until the iteration times reach the preset times to obtain a plurality of selected fitness function values;
the step of determining a result area in the binary thermodynamic diagram according to the fitness function value comprises the following steps:
and determining a result area in the binary thermodynamic diagram according to the selected fitness function values.
Optionally, the step of determining a result region in the binarization thermodynamic diagram according to the plurality of selected fitness function values includes:
determining a plurality of selected areas corresponding to the selected fitness function values in the binary thermodynamic diagram;
and combining the selected areas to obtain a result area.
Optionally, the step of performing merging processing on the multiple selected regions to obtain a result region includes:
determining a coincidence area and a combination area for any two selected areas in the plurality of selected areas to obtain a plurality of coincidence areas and a plurality of combination areas;
obtaining the coincidence degree corresponding to each coincidence area according to each coincidence area and the combination area corresponding to each coincidence area;
and carrying out merging operation on the two selected areas with the contact ratio larger than a preset contact ratio threshold value to obtain the result area.
Optionally, before the step of obtaining the abnormal analysis result of the semiconductor to be analyzed according to the result region, the method further includes:
obtaining the area reject ratio of the result area;
the step of obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area includes:
and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the area reject ratio and a preset area reject ratio threshold value.
In addition, in order to achieve the above object, the present invention also provides an abnormality analysis apparatus for a semiconductor, which is used for a terminal device, the apparatus including:
the acquisition module is used for acquiring a binary thermodynamic diagram of a semiconductor to be analyzed;
the frame selection module is used for selecting a target area in the binary thermodynamic diagram by using a preset detection frame;
the first determining module is used for determining a fitness function value corresponding to the target area;
the second determining module is used for determining a result area in the binary thermodynamic diagram according to the fitness function value;
and the obtaining module is used for obtaining the abnormal analysis result of the semiconductor to be analyzed according to the result area.
In addition, to achieve the above object, the present invention further provides a terminal device, including: the semiconductor abnormality analysis program is stored in the memory and runs on the processor, and when being executed by the processor, the semiconductor abnormality analysis program realizes the steps of the semiconductor abnormality analysis method according to any one of the above items.
In order to achieve the above object, the present invention further provides a storage medium having a semiconductor abnormality analysis program stored thereon, the semiconductor abnormality analysis program implementing the semiconductor abnormality analysis method according to any one of the above steps when executed by a processor.
The technical scheme of the invention provides an anomaly analysis method of a semiconductor, which is used for terminal equipment and is used for obtaining a binary thermodynamic diagram of the semiconductor to be analyzed; framing out a target area in the binary thermodynamic diagram by using a preset detection frame; determining a fitness function value corresponding to the target area; determining a result area in the binary thermodynamic diagram according to the fitness function value; and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area.
In the prior art, a technician manually performs anomaly analysis on the binary thermodynamic diagram to obtain an anomaly analysis result of a semiconductor to be analyzed, and the technician has low manual analysis speed, so that the analysis time is long and the analysis efficiency is low. By using the method, the terminal equipment automatically utilizes the binary thermodynamic diagram to obtain the fitness function value corresponding to the target area, so that the corresponding result area is determined according to the fitness function value, the abnormal analysis result of the semiconductor to be analyzed is further obtained according to the result area, manual analysis is not needed, the analysis time is greatly shortened, and the analysis efficiency is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a terminal device in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a method for analyzing an abnormality of a semiconductor device according to a first embodiment of the present invention;
FIG. 3 is a schematic illustration of an initial thermodynamic diagram of the present invention;
FIG. 4 is a schematic representation of a resulting thermodynamic diagram of the present invention;
fig. 5 is a block diagram showing the structure of a semiconductor abnormality analysis device according to a first embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a terminal device in a hardware operating environment according to an embodiment of the present invention.
In general, a terminal device includes: at least one processor 301, a memory 302, and a semiconductor anomaly analysis program stored on the memory and executable on the processor, the semiconductor anomaly analysis program being configured to implement the steps of the semiconductor anomaly analysis method as described above.
The processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so on. The processor 301 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor, where the main processor is a processor for processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. The processor 301 may further include an AI (Artificial Intelligence) processor for processing an abnormality analysis method operation with respect to the semiconductor, so that an abnormality analysis method model of the semiconductor can be trained and learned autonomously, improving efficiency and accuracy.
In some embodiments, the terminal may further include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected by a bus or signal lines. Various peripheral devices may be connected to communication interface 303 via a bus, signal line, or circuit board. Specifically, the peripheral device includes: at least one of radio frequency circuitry 304, a display screen 305, and a power source 306.
The communication interface 303 may be used to connect at least one peripheral device related to I/O (Input/Output) to the processor 301 and the memory 302. In some embodiments, processor 301, memory 302, and communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302 and the communication interface 303 may be implemented on a single chip or circuit board, which is not limited in this embodiment.
The Radio Frequency circuit 304 is used for receiving and transmitting RF (Radio Frequency) signals, also called electromagnetic signals. The radio frequency circuitry 304 communicates with communication networks and other communication devices via electromagnetic signals. The rf circuit 304 converts an electrical signal into an electromagnetic signal to transmit, or converts a received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 304 comprises: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a subscriber identity module card, and so forth. The radio frequency circuitry 304 may communicate with other terminals via at least one wireless communication protocol. The wireless communication protocols include, but are not limited to: metropolitan area networks, various generation mobile communication networks (2G, 3G, 4G, and 5G), Wireless local area networks, and/or WiFi (Wireless Fidelity) networks. In some embodiments, the rf circuit 304 may further include NFC (Near Field Communication) related circuits, which are not limited in this application.
The display screen 305 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof. When the display screen 305 is a touch display screen, the display screen 305 also has the ability to capture touch signals on or over the surface of the display screen 305. The touch signal may be input to the processor 301 as a control signal for processing. At this point, the display screen 305 may also be used to provide virtual buttons and/or a virtual keyboard, also referred to as soft buttons and/or a soft keyboard. In some embodiments, the display screen 305 may be one, the front panel of the electronic device; in other embodiments, the display screens 305 may be at least two, respectively disposed on different surfaces of the electronic device or in a folded design; in still other embodiments, the display screen 305 may be a flexible display screen disposed on a curved surface or a folded surface of the electronic device. Even further, the display screen 305 may be arranged in a non-rectangular irregular figure, i.e. a shaped screen. The Display screen 305 may be made of LCD (liquid crystal Display), OLED (Organic Light-Emitting Diode), and the like.
The power supply 306 is used to power various components in the electronic device. The power source 306 may be alternating current, direct current, disposable or rechargeable. When the power source 306 includes a rechargeable battery, the rechargeable battery may support wired or wireless charging. The rechargeable battery may also be used to support fast charge technology.
Those skilled in the art will appreciate that the configuration shown in fig. 1 does not constitute a limitation of the terminal device and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
Furthermore, an embodiment of the present invention also provides a storage medium, on which an abnormality analysis program of a semiconductor is stored, which implements the steps of the abnormality analysis method of a semiconductor as described above when executed by a processor. Therefore, a detailed description thereof will be omitted. In addition, the beneficial effects of the same method are not described in detail. For technical details not disclosed in the embodiments of the storage medium referred to in the present application, reference is made to the description of the embodiments of the method of the present application. It is determined that the program instructions may be deployed to be executed on one terminal device, or on multiple terminal devices located at one site, or distributed across multiple sites and interconnected by a communication network, as examples.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a storage medium and can include the processes of the embodiments of the methods described above when executed. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
Based on the above hardware structure, an embodiment of the semiconductor abnormality analysis method of the present invention is provided.
Referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of a semiconductor abnormality analysis method of the present invention, the method including the steps of:
step S11: and acquiring a binary thermodynamic diagram of the semiconductor to be analyzed.
The main execution unit of the present invention is a terminal device, the terminal device is equipped with a semiconductor abnormality analysis program, and the terminal device executes the semiconductor abnormality analysis program to realize the semiconductor abnormality analysis method of the present invention.
In the present invention, the semiconductor to be analyzed means a semiconductor to be subjected to abnormality analysis, and particularly means a semiconductor such as a PCB, an IC, and a MEMS which is used when assembling and manufacturing a microphone. Generally, when the semiconductor to be analyzed is a PCB, the corresponding binarization thermodynamic diagram is in a rectangular shape, and when the semiconductor is an IC or MEMS, the corresponding binarization thermodynamic diagram is in a circular shape. In the present invention, the PCB is taken as an example for explanation, and the other two are performed identically, except for the shape.
Further, the semiconductor to be analyzed includes a plurality of; before the step of obtaining the binary thermodynamic diagram corresponding to the semiconductor to be analyzed, the method further includes: acquiring a plurality of initial thermodynamic diagrams corresponding to a plurality of semiconductors to be analyzed; performing a superposition operation on the plurality of initial thermodynamic diagrams to obtain a superposition thermodynamic diagram, wherein the superposition thermodynamic diagram comprises a plurality of unit areas, and each unit area corresponds to a plurality of heat force values; obtaining a unit yield of each unit area according to the plurality of heat values of each unit area; obtaining a mean value and a standard deviation of the unit yield rates according to the unit yield rates; obtaining a binarization threshold value according to the mean value and the standard deviation; and carrying out binarization processing on the superimposed thermodynamic diagram by using the binarization threshold value to obtain the binarization thermodynamic diagram.
In the present invention, the initial thermodynamic diagram of the semiconductor to be analyzed may be obtained by a technician or other electronic equipment when the technician or other electronic equipment assembles the semiconductor to be analyzed, based on the state information (normal state or abnormal state, where the normal state indicates that a unit is operable normally and there is no fault, and the abnormal state indicates that a unit is not operable normally and there is a fault) of each unit (for example, one unit is a raw material constituting a microphone, and one unit may be a PCB unit, an IC unit or an MEMS) in the semiconductor to be analyzed; in the initial thermodynamic diagram, state information corresponding to each cell in the semiconductor to be analyzed is included, and generally, in the initial thermodynamic diagram, each cell corresponds to a small rectangle (or square area) -one cell area, and the state information of one cell corresponding to each cell area is represented by setting different colors for each cell area: dark colors (shaded fill indicates dark colors in the present invention) indicate abnormal states, and light colors (no fill indicates light colors in the present invention) indicate normal states.
Referring to fig. 3, fig. 3 is a schematic view of an initial thermodynamic diagram of the present invention. The light areas (green in the color image) represented by no fill represent the areas corresponding to the cells in the normal state, and the dark areas (red in the color image) represented by fill represent the areas corresponding to the cells in the abnormal state. In which each cell corresponds to a small square area, but the cell areas of the respective cells do not have a boundary, and are connected to each other to form a relatively large area, i.e., the areas corresponding to the respective cells in fig. 3 do not show a boundary, and thus appear to be a large area.
In some embodiments, when there is one semiconductor to be analyzed, the semiconductor to be analyzed corresponds to an initial thermodynamic diagram, which is the thermodynamic diagram obtained by binarizing in step S11, and the binarization process is not required.
Only when the semiconductor to be analyzed comprises a plurality of initial thermodynamic diagrams, the initial thermodynamic diagrams correspond to the plurality of initial thermodynamic diagrams, and the plurality of initial thermodynamic diagrams are not binarized after being superposed, so that binarization processing is required, wherein one semiconductor to be analyzed corresponds to one initial thermodynamic diagram.
Generally, for one analysis process corresponding to the method of the present invention, a plurality of semiconductors to be analyzed need to be semiconductors of the same type and the same size, and the arrangement distribution of the cells in each semiconductor to be analyzed is the same, except for the state information of each cell, so that the sizes of the corresponding initial thermodynamic diagrams are the same, and meanwhile, each initial thermodynamic diagram includes the same cell area (including the same column number, the same row number and the same total number of cell areas), and one cell area corresponds to one cell. For example, the plurality of semiconductors to be analyzed are PCBs each including 20 × 30 cells, and the initial thermodynamic diagrams corresponding to the PCBs include 20 × 30 cell regions, and the positions of the cell regions in the initial thermodynamic diagrams are the same.
A plurality of initial thermodynamic diagrams of a plurality of semiconductors to be analyzed are subjected to a stacking operation (stacking together) to obtain a stacked thermodynamic diagram. The size of the superimposed thermodynamic diagram is the same as the initial thermodynamic diagram, the superimposed thermodynamic diagram includes the same total number of cell areas as each of the initial thermodynamic diagrams, and the same total number of each row and each column.
In the superimposed thermodynamic diagram, one unit region corresponds to the state information of each unit of the plurality of semiconductors to be analyzed, for example, the number of the plurality of semiconductors to be analyzed is 4, and the eighth unit region from the left of the first row of the superimposed thermodynamic diagram corresponds to 4 state information corresponding to 4 initial thermodynamic diagrams of four semiconductors to be analyzed in the unit region. And for one unit area in the superposed thermodynamic diagram, the ratio of the number of the normal states to the total number of the initial thermodynamic diagrams is the unit yield. And then, according to the unit yield of all the unit areas in the superimposed thermodynamic diagram, obtaining the mean value and the standard deviation corresponding to all the unit areas in the superimposed thermodynamic diagram.
Then, continuing to use the 2 sigma principle to obtain a binary threshold value: threshold is mean +2 std, where threshold is the binarization threshold, mean is the mean, std is the standard deviation. In the invention, the 2 σ principle is a method for obtaining the binary threshold, and a user can set other solving methods based on requirements.
And then marking the unit areas with the unit yield of each unit area in the superimposed thermodynamic diagram larger than the threshold as 1 (marked as light color) and marking the coordinates smaller than the threshold as 0 (marked as dark color) to obtain the final binary thermodynamic diagram. In the present invention, the binary thermodynamic diagrams of a plurality of semiconductors to be analyzed are similar to those in fig. 3, and the details of the present invention are not repeated.
And step 12, framing out the target area in the binary thermodynamic diagram by using a preset detection frame.
In the invention, the preset detection frame is set based on the requirement of a user, and for the binary thermodynamic diagram, the preset detection frame also comprises a plurality of unit areas, and each unit area can represent the position of the unit area in the binary thermodynamic diagram by using two-dimensional coordinates. For the PCB, the binarization thermodynamic diagram is rectangular, the set preset detection frame is also rectangular, for the IC and the MEMS, the binarization thermodynamic diagram is circular, and the corresponding preset detection frame is circular.
In general, when the preset detection frame is a rectangle, the representation format is (x, y, l, w), x and y are respectively the abscissa and ordinate of the marker point (which may be a vertex or a midpoint of a certain side, etc.) in the preset detection frame, and l and w are the length and width of the preset detection frame (generally, the length of a unit side of a unit area is taken as a unit length, for example, l is 4, the representation length is 4, and the length includes four unit areas). When the preset detection frame is circular, the representation form is (x, y, r), r is the radius of the circle, and x and y are respectively the abscissa and the ordinate of the center of the circle in the preset detection frame.
The area of the preset detection frame at the frame in the binary thermodynamic diagram is the target area, and one preset detection frame corresponds to one target area.
And step S13, determining a fitness function value corresponding to the target area.
A fitness function value needs to be obtained for a target area, and generally, one target area corresponds to one fitness function value.
Specifically, the step of determining the fitness function value corresponding to the target area includes: determining the total area of the target region, the abnormal area of the abnormal region in the target region and the total abnormal area of the abnormal region in the binary thermodynamic diagram; obtaining a first area ratio according to the abnormal area and the total area; obtaining a second area ratio according to the abnormal area and the total abnormal area; and obtaining a fitness function value corresponding to the target region by using the first area ratio and the second area ratio.
The first area ratio is the ratio of the abnormal area to the total area, the second area ratio is the ratio of the abnormal area to the total abnormal area, and then the fitness function value corresponding to the target area is obtained according to a formula I, wherein the formula I is as follows:
Fit＝α*Rc+(1-α)*R
wherein Fit is a fitness function value of the target area, RcR is a second area ratio.
In the invention, the formula is a function formula corresponding to a genetic algorithm, Fit is an iterative function value corresponding to the genetic algorithm, and multiple iterative operations are required according to the formula I. α is a weight of the abnormal region proportion, and when the weight is 1, it means that the child with the largest abnormal region proportion is preferentially selected, and when the weight is 0, it means that the child with the largest area of the frame target region is preferentially selected, so that the weights of the two are balanced so that the selected child local region has a higher defect and can contain as many abnormal regions as possible.
To this end, the fitness function value of the target region is obtained in the above manner.
And step S14, determining a result area in the binary thermodynamic diagram according to the fitness function value.
In the invention, a plurality of preset detection frames need to be set, a plurality of target areas are obtained, and a plurality of fitness function values corresponding to the plurality of target areas are obtained.
Specifically, the target area includes a plurality of target areas corresponding to a plurality of preset detection frames, and the fitness function value includes a plurality of fitness function values corresponding to a plurality of target areas; before the step of determining a result region in the binary thermodynamic diagram according to the fitness function value, the method further includes: determining a plurality of initial selection fitness function values in the fitness function values; when the iterated times do not reach the preset times, updating the iterated times; carrying out inheritance, intersection or variation operation on the plurality of preset detection frames to obtain a plurality of new preset detection frames; adjusting a plurality of primary selection target areas corresponding to the plurality of primary selection fitness function values by using a plurality of new detection frames to obtain a plurality of new target areas; updating a plurality of target areas by using a plurality of new target areas, and returning to execute the step of obtaining the fitness function value corresponding to the target area according to the target areas until the iteration times reach the preset times to obtain a plurality of selected fitness function values; the step of determining a result area in the binary thermodynamic diagram according to the fitness function value comprises the following steps: and determining a result area in the binary thermodynamic diagram according to the selected fitness function values.
The user can set the iteration times, namely the preset times, according to the requirement, and the iteration times are used for carrying out the preset times of iterative operation on the fitness function value. Each iteration operation corresponds to a plurality of fitness function values, and then a plurality of initially selected fitness function values with larger fitness (the first fitness function values are usually the largest, and the specific number is not limited) are determined from the plurality of corresponding fitness function values. And determining a plurality of initially selected fitness function values determined for the last time as a plurality of selected fitness function values until the number of iterations reaches a preset number. And obtaining an abnormal analysis result of the semiconductor to be analyzed according to the selected fitness function values.
For a new preset detection frame corresponding to one preset detection frame, the size of the new preset detection frame is changed only after the inheritance, intersection or mutation operation is performed, and the corresponding setting position is unchanged (for example, the coordinates of the mark point or the circle center are unchanged). Meanwhile, the preset detection frame is adjusted only by the target area corresponding to the plurality of initially selected fitness function values corresponding to the last iteration operation: and (4) inheritance, crossing or mutation operation, wherein other preset detection frames do not need to be adjusted, and target areas except the target areas corresponding to the plurality of initially selected fitness function values do not need to be continued.
Specifically, the step of determining a result region in the binarization thermodynamic diagram according to the plurality of selected fitness function values includes: determining a plurality of selected areas corresponding to the selected fitness function values in the binary thermodynamic diagram; and combining the selected areas to obtain a result area.
Wherein the step of combining the plurality of selected regions to obtain a result region includes: determining a coincidence area and a combination area for any two selected areas in the plurality of selected areas to obtain a plurality of coincidence areas and a plurality of combination areas; obtaining the coincidence degree corresponding to each coincidence area according to each coincidence area and the combination area corresponding to each coincidence area; and carrying out merging operation on the two selected areas with the contact ratio larger than a preset contact ratio threshold value to obtain the result area.
The preset contact ratio threshold may be set based on a requirement, and the present invention is not limited thereto. For the last iteration operation, the multiple new target areas and the multiple initial fitness function values correspond to the multiple selected fitness function values determined from the multiple initial fitness function values, the multiple selected new target areas correspond to the multiple selected new target areas, the multiple corresponding selected new target areas are selected areas, and the selected areas generally include multiple selected areas.
For any two of the plurality of selected regions: the area of the overlapped part of the area A and the area B, namely the overlapped area, is calculated, and the total area of the area A and the area B, namely the combined area, is calculated; for the a region and the B region, the degree of coincidence, which can also be said to correspond to the overlapping area of the a region and the B region, is calculated. If the coincidence degree is larger than the preset coincidence degree threshold value, the two regions are combined into one region, otherwise, the combination processing is not carried out, and the independent structures are still kept.
The merging operation is performed on all the selected areas, that is, the result after the merging operation, namely the result area, can be obtained, and the selected areas can be merged into one result area or multiple result areas.
Step S15: and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area.
And determining an abnormal analysis result of the semiconductor to be analyzed according to the result area. In the present invention, the abnormal analysis result of the semiconductor to be analyzed is also usually in the form of a thermodynamic diagram, i.e., a resultant thermodynamic diagram, where the resultant thermodynamic diagram includes an abnormal frame selection region, which indicates that the semiconductor to be analyzed has a concentrated thermal force region, and the abnormal frame selection region is a concentrated thermal force region, and the resultant thermodynamic diagram does not include the abnormal frame selection region, which indicates that the semiconductor to be analyzed does not have a concentrated thermal force region.
Specifically, before the step of obtaining the abnormal analysis result of the semiconductor to be analyzed according to the result region, the method further includes: obtaining the area reject ratio of the result area; the step of obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area includes: and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the area reject ratio and a preset area reject ratio threshold value.
For each result region, the yield of the result region (the average of the cell yields of the respective cell regions in the result region) is obtained in the manner described above for obtaining the cell yield, and then the defective rate of the result region, i.e., the above-described region defective rate, is determined, and then the above-obtained binarization threshold is determined as the defective rate threshold. And if the reject ratio of the result area is greater than the reject ratio threshold value, the result area is an abnormal frame selection area, otherwise, the result area is not the abnormal frame selection area.
Referring to fig. 4, fig. 4 is a schematic diagram of a result thermodynamic diagram of the present invention, and fig. 4 is a result thermodynamic diagram obtained by taking the binary thermodynamic diagram of fig. 3 as an input, in which a region framed by a dotted line is an abnormal framing region. It can be seen that the semiconductor to be analyzed corresponding to the binary thermodynamic diagram has a phenomenon of thermal concentration, and two abnormal frame selection areas selected by two dotted frames, i.e., two thermal concentration areas, are involved.
The abnormal analysis result of the semiconductor to be analyzed may include whether the semiconductor to be analyzed includes a phenomenon of heat concentration, and then whether the semiconductor to be analyzed is qualified in installation, manufacturing or other process.
The technical scheme of the invention provides an anomaly analysis method of a semiconductor, which is used for terminal equipment and is used for obtaining a binary thermodynamic diagram of the semiconductor to be analyzed; framing out a target area in the binary thermodynamic diagram by using a preset detection frame; determining a fitness function value corresponding to the target area; determining a result area in the binary thermodynamic diagram according to the fitness function value; and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area.
In the prior art, a technician manually performs anomaly analysis on the binary thermodynamic diagram to obtain an anomaly analysis result of a semiconductor to be analyzed, and the technician has low manual analysis speed, so that the analysis time is long and the analysis efficiency is low. By using the method, the terminal equipment automatically utilizes the binary thermodynamic diagram to obtain the fitness function value corresponding to the target area, so that the corresponding result area is determined according to the fitness function value, the abnormal analysis result of the semiconductor to be analyzed is further obtained according to the result area, manual analysis is not needed, the analysis time is greatly shortened, and the analysis efficiency is improved.
Referring to fig. 5, fig. 5 is a block diagram showing a first embodiment of an abnormality analysis apparatus for a semiconductor of the present invention, which is used for a terminal device, and which includes, based on the same inventive concept as the previous embodiment:
the acquisition module 10 is used for acquiring a binary thermodynamic diagram of a semiconductor to be analyzed;
a framing module 20, configured to frame out a target area in the binary thermodynamic diagram by using a preset detection frame;
a first determining module 30, configured to determine a fitness function value corresponding to the target area;
a second determining module 40, configured to determine a result region in the binarization thermodynamic diagram according to the fitness function value;
an obtaining module 50, configured to obtain an abnormal analysis result of the semiconductor to be analyzed according to the result area.
It should be noted that, since the steps executed by the apparatus of this embodiment are the same as the steps of the foregoing method embodiment, the specific implementation and the achievable technical effects thereof can refer to the foregoing embodiment, and are not described herein again.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. An abnormality analysis method of a semiconductor, characterized by being used for a terminal device, the method comprising the steps of:
acquiring a binary thermodynamic diagram of a semiconductor to be analyzed;
framing out a target area in the binary thermodynamic diagram by using a preset detection frame;
determining a fitness function value corresponding to the target area;
determining a result area in the binary thermodynamic diagram according to the fitness function value;
and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area.
2. The method of claim 1, wherein the semiconductor to be analyzed comprises a plurality; before the step of obtaining the binary thermodynamic diagram corresponding to the semiconductor to be analyzed, the method further includes:
acquiring a plurality of initial thermodynamic diagrams corresponding to a plurality of semiconductors to be analyzed;
performing a superposition operation on the plurality of initial thermodynamic diagrams to obtain a superposition thermodynamic diagram, wherein the superposition thermodynamic diagram comprises a plurality of unit areas, and each unit area corresponds to a plurality of heat force values;
obtaining a unit yield of each unit area according to the plurality of heat values of each unit area;
obtaining a mean value and a standard deviation of the unit yield rates according to the unit yield rates;
obtaining a binarization threshold value according to the mean value and the standard deviation;
and carrying out binarization processing on the superimposed thermodynamic diagram by using the binarization threshold value to obtain the binarization thermodynamic diagram.
3. The method of claim 1, wherein the step of determining the fitness function value for the target region comprises:
determining the total area of the target region, the abnormal area of the abnormal region in the target region and the total abnormal area of the abnormal region in the binary thermodynamic diagram;
obtaining a first area ratio according to the abnormal area and the total area;
obtaining a second area ratio according to the abnormal area and the total abnormal area;
and obtaining a fitness function value corresponding to the target region by using the first area ratio and the second area ratio.
4. The method of claim 1, wherein the target area comprises a plurality of target areas corresponding to a plurality of preset test frames, and the fitness function value comprises a plurality of fitness function values corresponding to a plurality of the target areas; before the step of determining a result region in the binary thermodynamic diagram according to the fitness function value, the method further includes:
determining a plurality of initial selection fitness function values in the fitness function values;
when the iterated times do not reach the preset times, updating the iterated times;
carrying out inheritance, intersection or variation operation on the plurality of preset detection frames to obtain a plurality of new preset detection frames;
adjusting a plurality of primary selection target areas corresponding to the plurality of primary selection fitness function values by using a plurality of new detection frames to obtain a plurality of new target areas;
updating a plurality of target areas by using a plurality of new target areas, and returning to execute the step of obtaining the fitness function value corresponding to the target area according to the target areas until the iteration times reach the preset times to obtain a plurality of selected fitness function values;
the step of determining a result area in the binary thermodynamic diagram according to the fitness function value comprises the following steps:
and determining a result area in the binary thermodynamic diagram according to the selected fitness function values.
5. The method as claimed in claim 4, wherein said step of determining a result region in said binary thermodynamic diagram based on a plurality of said selected fitness function values comprises:
determining a plurality of selected areas corresponding to the selected fitness function values in the binary thermodynamic diagram;
and combining the selected areas to obtain a result area.
6. The method of claim 5, wherein said step of combining a plurality of said selected regions to obtain a result region comprises:
determining a coincidence area and a combination area for any two selected areas in the plurality of selected areas to obtain a plurality of coincidence areas and a plurality of combination areas;
obtaining the coincidence degree corresponding to each coincidence area according to each coincidence area and the combination area corresponding to each coincidence area;
and carrying out merging operation on the two selected areas with the contact ratio larger than a preset contact ratio threshold value to obtain the result area.
7. The method according to any one of claims 1 to 6, wherein the step of obtaining an abnormality analysis result of the semiconductor to be analyzed based on the result area is preceded by the method further comprising:
obtaining the area reject ratio of the result area;
the step of obtaining an abnormal analysis result of the semiconductor to be analyzed according to the result area includes:
and obtaining an abnormal analysis result of the semiconductor to be analyzed according to the area reject ratio and a preset area reject ratio threshold value.
8. An abnormality analysis apparatus for a semiconductor, characterized by being used for a terminal device, the apparatus comprising:
the acquisition module is used for acquiring a binary thermodynamic diagram of a semiconductor to be analyzed;
the frame selection module is used for selecting a target area in the binary thermodynamic diagram by using a preset detection frame;
the first determining module is used for determining a fitness function value corresponding to the target area;
the second determining module is used for determining a result area in the binary thermodynamic diagram according to the fitness function value;
and the obtaining module is used for obtaining the abnormal analysis result of the semiconductor to be analyzed according to the result area.
9. A terminal device, characterized in that the terminal device comprises: a memory, a processor, and an abnormality analysis program of a semiconductor stored on the memory and running on the processor, the abnormality analysis program of a semiconductor implementing the steps of the abnormality analysis method of a semiconductor according to any one of claims 1 to 7 when executed by the processor.
10. A storage medium having stored thereon a semiconductor abnormality analysis program that realizes the steps of the semiconductor abnormality analysis method according to any one of claims 1 to 7 when executed by a processor.
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