CN114236922A - Reflective array substrate, manufacturing method thereof and reflective display panel - Google Patents

Reflective array substrate, manufacturing method thereof and reflective display panel Download PDF

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Publication number
CN114236922A
CN114236922A CN202111480132.5A CN202111480132A CN114236922A CN 114236922 A CN114236922 A CN 114236922A CN 202111480132 A CN202111480132 A CN 202111480132A CN 114236922 A CN114236922 A CN 114236922A
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layer
electrode
insulating layer
metal layer
reflective
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CN202111480132.5A
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CN114236922B (en
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李红侠
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InfoVision Optoelectronics Kunshan Co Ltd
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InfoVision Optoelectronics Kunshan Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

The invention discloses a reflective array substrate, a manufacturing method thereof and a reflective display panel, wherein the reflective array substrate comprises: a substrate; a gate electrode provided on the substrate; a gate insulating layer covering the first metal layer; a source electrode, a drain electrode and an active layer arranged on the gate insulating layer; the first insulating layer is arranged on the upper side of the grid insulating layer, and the source electrode, the drain electrode and the active layer are arranged between the grid insulating layer and the first insulating layer; the partition cushion block is arranged on the first insulating layer, and the projections of the partition cushion block and the drain electrode on the substrate are completely staggered; a reflective metal layer covering the spacer block; the pixel electrode is arranged on the reflecting metal layer and is electrically connected with the drain electrode; and a flat layer disposed on the upper side of the transparent electrode layer. Through locating the downside of planarization layer with the pixel electrode to need not to carry out the opening in drain electrode department to the planarization layer, avoid toasting the unidentified material oxidation that appears and corroding the drain electrode when solidifying to the planarization layer, reduce the climbing difference in height of pixel electrode, avoid the pixel electrode fracture to appear, the conductivity is better.

Description

Reflective array substrate, manufacturing method thereof and reflective display panel
Technical Field
The invention relates to the technical field of displays, in particular to a reflective array substrate, a manufacturing method of the reflective array substrate and a reflective display panel.
Background
The display panel has the advantages of lightness, thinness, durability, low power consumption and the like which accord with energy conservation and environmental protection, the electronic paper display becomes a display which accords with the public demand, the electronic paper display can display images by utilizing an external light source, and the backlight source is not needed by a liquid crystal display, so that information on the electronic paper can still be clearly seen under the environment of strong outdoor sunlight without the problem of viewing angle, and the electronic paper display is widely applied to electronic readers (such as electronic books and electronic newspapers) or other electronic elements (such as price labels) due to the advantages of power saving, high reflectivity, contrast ratio and the like.
Among the existing products, the array substrate of the electronic paper display is usually provided with a reflection layer, the reflection layer reflects ambient light to realize picture display, and in order to realize a better reflection effect, the reflection layer is made into an uneven structure to realize diffuse reflection. In the prior art, the rugged spacer block is manufactured on the lower side of the reflecting layer, and the spacer block is usually made of the same material as the flat layer and is thicker. The array substrate needs to arrange a pixel electrode above the reflective layer, so a flat layer needs to be arranged, and due to the fact that the plurality of flat layers are arranged, the depth of the contact hole is too deep, the pixel electrode is prone to being broken at the contact hole, and the pixel electrode and the drain electrode cannot be conducted or are not conducted well. Furthermore, when the flat layer is opened and cured by heating, an unknown substance is precipitated, and because the unknown substance is not protected by the insulating layer (PV), the unknown substance falls on the surface of the drain electrode at the contact hole, so that the drain electrode is oxidized and corroded, and the pixel electrode and the drain electrode cannot be conducted or are not conducted well.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the present invention provides a reflective array substrate, a manufacturing method thereof, and a reflective display panel, so as to solve the problem that the pixel electrode and the drain electrode of the reflective display panel in the prior art cannot be conducted or are not conducted well.
The purpose of the invention is realized by the following technical scheme:
the invention provides a reflective array substrate, comprising:
a substrate;
the first metal layer is arranged on the upper surface of the substrate and comprises a scanning line and a grid, and the grid is in conductive connection with the scanning line;
a gate insulating layer covering the first metal layer;
the semiconductor layer and the second metal layer are arranged on the upper side of the grid electrode insulating layer, the second metal layer comprises a data line, a source electrode and a drain electrode, the source electrode is in conductive connection with the data line, and the semiconductor layer comprises an active layer which is connected with the source electrode and the drain electrode;
the first insulating layer is arranged on the upper side of the grid insulating layer, and the semiconductor layer and the second metal layer are arranged between the grid insulating layer and the first insulating layer;
the spacer layer is arranged on the upper surface of the first insulating layer and comprises spacer blocks, projections of the spacer blocks and the drain electrode on the substrate are completely staggered, and the surface of the spacer block, which is far away from the first insulating layer, is of an uneven structure;
the reflecting metal layer covers the spacer block and comprises reflecting blocks, and the reflecting blocks are of an uneven structure;
the transparent electrode layer is arranged on the upper side of the reflecting metal layer and comprises a pixel electrode, and the pixel electrode is in conductive connection with the drain electrode;
and the flat layer is arranged on the upper side of the transparent electrode layer.
Further, the first metal layer further comprises a first capacitor plate, the second metal layer further comprises a second capacitor plate matched with the first capacitor plate, the second capacitor plate is in conductive connection with the drain electrode, and the first capacitor plate and the second capacitor plate jointly form a storage capacitor.
Further, a second insulating layer is arranged between the reflective metal layer and the transparent electrode layer, the second insulating layer separates the reflective block from the pixel electrode, the first insulating layer and the second insulating layer are provided with a first contact hole, the first contact hole penetrates through the first insulating layer and the second insulating layer, the first contact hole corresponds to the drain electrode, and the pixel electrode is in conductive contact with the drain electrode through the first contact hole.
Further, the second metal layer further includes a peripheral trace located in the non-display area, the transparent electrode layer further includes a bridge electrode corresponding to the peripheral trace, and the bridge electrode is electrically connected to the peripheral trace.
Furthermore, the first insulating layer and the second insulating layer are provided with second contact holes, the second contact holes penetrate through the first insulating layer and the second insulating layer and correspond to the peripheral wires, and the bridging electrodes are in conductive contact with the peripheral wires through the second contact holes; the flat layer is provided with a third contact hole, the third contact hole corresponds to the bridging electrode, and the bridging electrode is exposed from the third contact hole.
The invention also provides a manufacturing method of the reflective array substrate, which is used for manufacturing the reflective array substrate, and the manufacturing method comprises the following steps:
providing a substrate;
forming a first metal layer on the substrate, etching the first metal layer and forming a patterned scanning line and a grid, wherein the grid is in conductive connection with the scanning line;
forming a gate insulating layer covering the first metal layer on the substrate;
forming a semiconductor layer and a second metal layer on the upper side of the gate insulating layer, etching the second metal layer and forming a patterned data line, a source electrode and a drain electrode, wherein the source electrode is conductively connected with the data line, the semiconductor layer is etched and a patterned active layer is formed, and the active layer is connected with the source electrode and the drain electrode;
forming a first insulating layer on an upper side of the gate insulating layer, the semiconductor layer and the second metal layer being provided between the gate insulating layer and the first insulating layer;
forming a spacer layer on the first insulating layer, etching the spacer layer and forming a patterned spacer block, wherein projections of the spacer block and the drain electrode on the substrate are completely staggered, and the surface of the spacer block, which is far away from the first insulating layer, is of an uneven structure;
forming a reflection metal layer on the spacer block, etching the reflection metal layer and forming a patterned reflection block, wherein the reflection block is of an uneven structure;
etching the first insulating layer and forming a first contact hole corresponding to the drain electrode, wherein the drain electrode is exposed from the first contact hole;
forming a transparent electrode layer on the upper side of the reflective metal layer, etching the transparent electrode layer and forming a patterned pixel electrode, wherein the pixel electrode is in conductive connection with the drain electrode through the first contact hole;
and forming a flat layer on the upper side of the transparent electrode layer.
Further, when the first metal layer is etched, a first capacitor plate is formed, and when the second metal layer is etched, a second capacitor plate matched with the first capacitor plate is formed, the second capacitor plate is in conductive connection with the drain electrode, and the first capacitor plate and the second capacitor plate form a storage capacitor together.
Further, when the second metal layer is etched, a peripheral trace located in a non-display area is also formed, and when the transparent electrode layer is etched, a bridging electrode corresponding to the peripheral trace is also formed, and the bridging electrode is in conductive connection with the peripheral trace.
Further, before etching the first insulating layer, the manufacturing method further includes:
forming a second insulating layer on the reflective metal layer;
etching the first insulating layer and the second insulating layer to form a first contact hole and a second contact hole, wherein the first contact hole and the second contact hole both penetrate through the first insulating layer and the second insulating layer, the second contact hole corresponds to the peripheral wiring, and the bridging electrode is in conductive connection with the peripheral wiring through the second contact hole;
and etching the planarization layer and forming a third contact hole corresponding to the bridge electrode, the bridge electrode being exposed from the third contact hole.
The invention also provides a reflective display panel, which comprises the reflective array substrate.
The invention has the beneficial effects that: the pixel electrode is arranged on the lower side of the flat layer, so that the flat layer does not need to be opened at the drain electrode, and the situation that unknown substances separated out when the flat layer is baked and solidified fall on the surface of the drain electrode to cause the surface of the drain electrode to be oxidized and corroded so that the pixel electrode and the drain electrode cannot be conducted or are not conducted well is avoided; the pixel electrode is arranged on the lower side of the flat layer, so that the climbing height difference of the connection part of the pixel electrode and the drain electrode can be reduced, the pixel electrode is prevented from being broken, the connection between the pixel electrode and the drain electrode is smoother, and the conductivity is better; and the upper surface of the reflective array substrate has better smoothness, so that the alignment of liquid crystal molecules is facilitated. In addition, the spacer block and the drain electrode are completely staggered, so that the situation that unknown substances precipitated during baking and curing of the spacer block fall on the surface of the drain electrode to cause the surface of the drain electrode to be oxidized and corroded is avoided, and the conductivity of a pixel electrode and the drain electrode is further increased.
Drawings
FIG. 1 is a schematic cross-sectional view of a reflective array substrate according to the present invention;
FIGS. 2a-2g are schematic diagrams illustrating a manufacturing process of a reflective array substrate according to the present invention;
fig. 3 is a schematic cross-sectional view of a display panel according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be made on the reflective array substrate and the manufacturing method thereof, and the embodiments, structures, features and effects of the reflective display panel according to the present invention with reference to the accompanying drawings and preferred embodiments as follows:
fig. 1 is a schematic cross-sectional view of a reflective array substrate of the present invention, fig. 2a-2g are schematic manufacturing flow diagrams of a method for manufacturing a reflective array substrate of the present invention, and fig. 3 is a schematic cross-sectional structure of a display panel of the present invention.
As shown in fig. 1, the present invention provides a reflective array substrate, which includes:
substrate 10. substrate 10 may be made of glass, quartz, acrylic, or polycarbonate, among other materials.
A first metal layer 11 (fig. 2a) disposed on the upper surface of the substrate 10, wherein the first metal layer 11 includes a scan line (not shown) and a gate 111, and the gate 111 is electrically connected to the scan line. The first metal layer 11 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al), or the like.
The gate insulating layer 101 covers the first metal layer 11, the entire surface of the gate insulating layer 101 is disposed on the substrate 10 and covers the gate electrode 111 and the scan line, and the gate insulating layer 101 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like.
A semiconductor layer 12 (fig. 2b) and a second metal layer 13 (fig. 2c) disposed on an upper side of the gate insulating layer 101, the second metal layer 13 including a data line 131, a source electrode 132 and a drain electrode 133, the source electrode 132 being electrically connected to the data line 131, the source electrode 132 and the drain electrode 133 being disconnected from each other and forming a channel, the semiconductor layer 12 including an active layer 121 connecting the source electrode 132 and the drain electrode 133. Wherein the scan lines and the data lines 131 cross each other in an insulated manner and define a plurality of pixel units. The semiconductor layer 12 is made of a metal Oxide such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), LnIZO, or ITZO, and the semiconductor layer 12 may be made of amorphous silicon (a-Si) or polycrystalline silicon (p-Si). The second metal layer 13 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al), or the like. In this embodiment, the semiconductor layer 12 covers the upper surface of the gate insulating layer 101, and the second metal layer 13 covers the upper surface of the semiconductor layer 12. Of course, in other embodiments, the second metal layer 13 may cover the upper surface of the gate insulating layer 101, and the semiconductor layer 12 may cover the upper surface of the second metal layer 13.
A first insulating layer 102 provided on the upper side of the gate insulating layer 101, and a semiconductor layer 12 and a second metal layer 13 are provided between the gate insulating layer 101 and the first insulating layer 102. In this embodiment, the first insulating layer 102 covers the data line 131, the source electrode 132 and the drain electrode 133. The first insulating layer 102 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like.
And the spacer layer 14 is arranged on the upper surface of the first insulating layer 102 (fig. 2d), the spacer layer 14 comprises spacer blocks 141, projections of the spacer blocks 141 and the drain electrode 133 on the substrate 10 are completely staggered, and the surface of the spacer blocks 141, which is far away from the first insulating layer 102, is in an uneven structure. In this embodiment, there are a plurality of spacer blocks 141, and each spacer block 141 corresponds to one pixel unit. The spacer block 141 is provided with a plurality of protruding structures 141a, so that the surface of the spacer block 141 away from the first insulating layer 102 is uneven, and the cross section of the protruding structures 141a may be semicircular, triangular, trapezoidal, and the like. Of course, in other embodiments, the spacer blocks 141 may correspond to a plurality of pixel units. Further, a plurality of groove structures may be disposed on the spacer block 141, so that the surface of the spacer block 141 away from the first insulating layer 102 is uneven, and the cross section of the groove structures may be semicircular, triangular, inverted trapezoid, and the like.
Cover spacer block 141's reflection metal layer 15 (fig. 2e), reflection metal layer 15 includes reflection piece 151, and reflection piece 151 is unevenness's structure, comes for reflection piece 151 to stereotype through spacer block 141 to make reflection piece 151 be unevenness's structure, in order to realize the diffuse reflection. The reflective blocks 151 are provided in plurality, and the reflective blocks 151 correspond to the spacer blocks 141 one to one. The reflective metal layer 15 may be made of Al, Ag, or other materials with high reflectivity.
And a transparent electrode layer 16 (fig. 2f) disposed on the upper side of the reflective metal layer 15, wherein the transparent electrode layer 16 includes pixel electrodes 161, the pixel electrodes 161 correspond to the pixel units one by one, and the pixel electrodes 161 are electrically connected to the drain electrodes 133. The transparent electrode layer 16 may be made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
And a planarization layer 104 provided on the upper side of the transparent electrode layer 16. The planarization layer 104 and the spacer layer 14 are made of the same material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (sion).
According to the invention, the pixel electrode 161 is arranged at the lower side of the flat layer 104, so that the flat layer 104 does not need to be opened at the drain electrode 133, and the situation that an unknown substance precipitated when the flat layer 104 is baked and solidified falls on the surface of the drain electrode 133 to cause the surface of the drain electrode 133 to be oxidized and corroded, and the pixel electrode 161 and the drain electrode 133 cannot be conducted or are not conducted well is avoided. The pixel electrode 161 is arranged at the lower side of the flat layer 104, so that the climbing height difference of the pixel electrode 161 at the connection part of the pixel electrode 161 and the drain electrode 133 can be reduced, the pixel electrode 161 is prevented from being broken, the connection between the pixel electrode 161 and the drain electrode 133 is smoother, and the conductivity is better. And the flatness of the upper surface of the reflective array substrate can be better, so that the alignment of liquid crystal molecules is facilitated. In addition, the spacers 141 and the drain electrode 133 are completely staggered, so that the unknown substances precipitated during baking and curing of the spacers 141 are prevented from falling on the surface of the drain electrode 133, and the surface of the drain electrode 133 is prevented from being oxidized and corroded, thereby further increasing the conductivity between the pixel electrode 161 and the drain electrode 133.
Further, the first metal layer 11 further includes a first capacitor plate 112, the second metal layer 13 further includes a second capacitor plate 134 matched with the first capacitor plate 112, the second capacitor plate 134 is electrically connected to the drain 133, and the first capacitor plate 112 and the second capacitor plate 134 together form a storage capacitor. Thereby increasing the storage capacitance of the pixel electrode 161 and the pixel electrode 161 is more stable in charging and maintaining the voltage. In this embodiment, the first capacitor plate 112 and the second capacitor plate 134 are both block electrodes covering one pixel unit. Of course, in other embodiments, the first capacitor plate 112 may also be a stripe and extend along the scan line direction, and the first capacitor plate 112 may cover an entire row of pixel units. The first capacitor plate 112 is similar to the common electrode, and the second capacitor plate 134 serves as an extension electrode of the pixel electrode 161. Of course, the first capacitor plate 112 may also be "square" and correspond to the outer periphery of the second capacitor plate 134, and in practical applications, the overlapping area of the first capacitor plate 112 and the second capacitor plate 134 may be adjusted according to the required storage capacitor size.
Further, a second insulating layer 103 is disposed between the reflective metal layer 15 and the transparent electrode layer 16, the second insulating layer 103 separates the reflective block 151 from the pixel electrode 161, and the reflective block 151 and the spacer block 141, which are separated from each other, may correspond to a plurality of pixel units, respectively. If the reflective blocks 151 and the pixel electrodes 161 are in contact with each other, when the reflective blocks 151 correspond to two pixel units, gray-scale voltages of the two pixel units are interfered, and thus, when the second insulating layer 103 is not provided, the reflective blocks 151 need to correspond to the pixel electrodes 161 one by one. The first and second insulating layers 102 and 103 are provided with a first contact hole 105, the first contact hole 105 penetrates the first and second insulating layers 102 and 103, the first contact hole 105 corresponds to the drain electrode 133, and the pixel electrode 161 is in conductive contact with the drain electrode 133 through the first contact hole 105. The second insulating layer 103 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like. Since the first insulating layer 102 and the second insulating layer 103 are thin, they do not need to be heated and cured, so that no unknown substance is precipitated, which can avoid the problem of influencing the conductivity when the planar layer is perforated in the prior art. The planarization layer 104 and the spacer layer 14 are usually thicker, and in order to speed up the manufacturing process, it is necessary to heat to speed up the curing of the planarization layer 104 and the spacer layer 14, during the heating and curing process, an unidentified substance is precipitated, and when the unidentified substance falls on the drain electrode 133, the surface of the drain electrode 133 is oxidized and corroded, which affects the conductivity between the pixel electrode 161 and the drain electrode 133.
Further, the second metal layer 13 further includes a peripheral trace 135 located in the non-display region, the transparent electrode layer 16 further includes a bridge electrode 162 corresponding to the peripheral trace 135, and the bridge electrode 162 is electrically connected to the peripheral trace 135. The peripheral trace 135 may be, for example, some metal wires (signal input lines) of the bonding area.
Further, the first insulating layer 102 and the second insulating layer 103 are provided with a second contact hole 106, the second contact holes 106 both penetrate through the first insulating layer 102 and the second insulating layer 103, the second contact hole 106 corresponds to the peripheral trace 135, and the bridging electrode 162 is in conductive contact with the peripheral trace 135 through the second contact hole 106; the planarization layer 104 has a third contact hole 107, the third contact hole 107 corresponds to the bridge electrode 162, and the bridge electrode 162 is exposed from the third contact hole 107. The bridging electrode 162 covers the peripheral trace 135 in the second contact hole 106, so that when the planarization layer 104 is heated and cured, an unknown substance precipitated from the planarization layer 104 is prevented from falling on the surface of the peripheral trace 135, which causes the surface of the peripheral trace 135 to be oxidized and corroded, thereby affecting the binding effect. Since the bridge electrode 162 is made of the transparent electrode layer 16, it is not oxidized and corroded by the unknown substance precipitated from the planarization layer 104.
The embodiment also provides a manufacturing method of the reflective array substrate, which is used for manufacturing the reflective array substrate. As shown in fig. 2a-2g, the manufacturing method comprises:
as shown in fig. 2a, a substrate 10 is provided, and the substrate 10 may be made of glass, quartz, acrylic or polycarbonate.
A first metal layer 11 is formed on a substrate 10, the first metal layer 11 is etched to form a patterned scan line (not shown) and a gate electrode 111, and the gate electrode 111 is electrically connected to the scan line. The first metal layer 11 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al), or the like.
A gate insulating layer 101 covering the first metal layer 11 is formed on the substrate 10, the entire surface of the gate insulating layer 101 is disposed on the substrate 10 and covers the gate electrode 111 and the scan line, and the gate insulating layer 101 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like.
Forming a semiconductor layer 12 and a second metal layer 13 on an upper side of the gate insulating layer 101, etching the second metal layer 13 and forming a patterned data line 131, a source electrode 132 and a drain electrode 133, the source electrode 132 being electrically connected to the data line 131, the source electrode 132 and the drain electrode 133 being disconnected from each other and forming a channel, etching the semiconductor layer 12 and forming a patterned active layer 121, the active layer 121 connecting the source electrode 132 and the drain electrode 133. Wherein the scan lines and the data lines 131 cross each other in an insulated manner and define a plurality of pixel units. The semiconductor layer 12 is made of a metal Oxide such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), LnIZO, or ITZO, and the semiconductor layer 12 may be made of amorphous silicon (a-Si) or polycrystalline silicon (p-Si). The second metal layer 13 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al), or the like.
In this embodiment, as shown in fig. 2b, a semiconductor layer 12 is formed on the upper surface of the gate insulating layer 101, and the semiconductor layer 12 is etched to form a patterned active layer 121; as shown in fig. 2c, a second metal layer 13 is formed on the upper surface of the gate insulating layer 101, the second metal layer 13 covers the active layer 121, the second metal layer 13 is etched to form a patterned data line 131, a source electrode 132 and a drain electrode 133, the source electrode 132 is electrically connected to the data line 131, and the source electrode 132 and the drain electrode 133 are electrically connected through the active layer 121. Of course, in other embodiments, the second metal layer 13 may be formed on the gate insulating layer 101, the second metal layer 13 is etched to form the patterned data line 131, the source electrode 132 and the drain electrode 133, and the source electrode 132 is electrically connected to the data line 131; then, the semiconductor layer 12 is formed on the upper surface of the gate insulating layer 101, the semiconductor layer 12 covers the data line 131, the source electrode 132 and the drain electrode 133, the semiconductor layer 12 is etched to form the patterned active layer 121, and the active layer 121 connects the source electrode 132 and the drain electrode 133, that is, the active layer 121 may be disposed on the upper sides of the source electrode 132 and the drain electrode 133.
As shown in fig. 2c, a first insulating layer 102 is formed on the upper side of the gate insulating layer 101, and the semiconductor layer 12 and the second metal layer 13 are provided between the gate insulating layer 101 and the first insulating layer 102. In this embodiment, the first insulating layer 102 covers the data line 131, the source electrode 132 and the drain electrode 133. The first insulating layer 102 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like.
As shown in fig. 2d, the spacer layer 14 is formed on the first insulating layer 102, the spacer layer 14 is etched to form a patterned spacer 141, projections of the spacer 141 and the drain 133 on the substrate 10 are completely staggered, and a surface of the spacer 141 away from the first insulating layer 102 has an uneven structure. In this embodiment, there are a plurality of spacer blocks 141, and each spacer block 141 corresponds to one pixel unit. The spacer block 141 is provided with a plurality of protruding structures 141a, so that the surface of the spacer block 141 away from the first insulating layer 102 is uneven, and the cross section of the protruding structures 141a may be semicircular, triangular, trapezoidal, and the like. Of course, in other embodiments, the spacer blocks 141 may correspond to a plurality of pixel units. Further, a plurality of groove structures may be disposed on the spacer block 141, so that the surface of the spacer block 141 away from the first insulating layer 102 is uneven, and the cross section of the groove structures may be semicircular, triangular, inverted trapezoid, and the like.
As shown in fig. 2e, a reflective metal layer 15 is formed on the spacer block 141, the reflective metal layer 15 is etched to form a patterned reflective block 151, the reflective block 151 has an uneven structure, and the reflective block 151 is patterned by the spacer block 141, so that the reflective block 151 has an uneven structure to implement diffuse reflection. The reflective blocks 151 are provided in plurality, and the reflective blocks 151 correspond to the spacer blocks 141 one to one. The reflective metal layer 15 may be made of Al, Ag, or other materials with high reflectivity.
As shown in fig. 2e, the first insulating layer 102 is etched and a first contact hole 105 corresponding to the drain electrode 133 is formed, and the drain electrode 133 is exposed from the first contact hole 105.
As shown in fig. 2f, a transparent electrode layer 16 is formed on the upper side of the reflective metal layer 15, the transparent electrode layer 16 is etched to form patterned pixel electrodes 161, the pixel electrodes 161 correspond to the pixel units one by one, and the pixel electrodes 161 are electrically connected to the drain electrodes 133 through the first contact holes 105. The transparent electrode layer 16 may be made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
As shown in fig. 2g, a planarization layer 104 is formed on the upper side of the transparent electrode layer 16. The planarization layer 104 and the spacer layer 14 are made of the same material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (sion).
Further, as shown in fig. 2b and 2c, when the first metal layer 11 is etched, the first capacitor plate 112 is further formed, and when the second metal layer 13 is etched, the second capacitor plate 134 matched with the first capacitor plate 112 is further formed, the second capacitor plate 134 is electrically connected to the drain 133, and the first capacitor plate 112 and the second capacitor plate 134 together form a storage capacitor. Thereby increasing the storage capacitance of the pixel electrode 161 and making the pixel electrode 161 more stable in charging and maintaining the voltage. In this embodiment, the first capacitor plate 112 and the second capacitor plate 134 are both block electrodes covering one pixel unit. Of course, in other embodiments, the first capacitor plate 112 may also be a stripe and extend along the scan line direction, and the first capacitor plate 112 may cover an entire row of pixel units. The first capacitor plate 112 is similar to the common electrode, and the second capacitor plate 134 serves as an extension electrode of the pixel electrode 161. Of course, the first capacitor plate 112 may also be "square" and correspond to the outer periphery of the second capacitor plate 134, and in practical applications, the overlapping area of the first capacitor plate 112 and the second capacitor plate 134 may be adjusted according to the required storage capacitor size.
Further, as shown in fig. 2c and 2f, when the second metal layer 13 is etched, a peripheral trace 135 located in the non-display region is further formed, and when the transparent electrode layer 16 is etched, a bridge electrode 162 corresponding to the peripheral trace 135 is further formed, and the bridge electrode 162 is electrically connected to the peripheral trace 135. The peripheral trace 135 may be, for example, some metal wires (signal input lines) of the bonding area.
Further, before etching the first insulating layer 102, the manufacturing method further includes:
as shown in fig. 2e, a second insulating layer 103 is formed on the reflective metal layer 15, and the second insulating layer 103 spaces the reflective block 151 and the pixel electrode 161 apart, so that the reflective block 151 and the spacer block 141 may correspond to a plurality of pixel units.
The first insulating layer 102 and the second insulating layer 103 are etched to form a first contact hole 105 and a second contact hole 106, the first contact hole 105 and the second contact hole 106 both penetrate through the first insulating layer 102 and the second insulating layer 103, the second contact hole 106 corresponds to the peripheral trace 135, and the bridge electrode 162 is electrically connected to the peripheral trace 135 through the second contact hole 106. The second insulating layer 103 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or the like. Since the first insulating layer 102 and the second insulating layer 103 are thin, they do not need to be heated and cured, so that no unknown substance is precipitated, which can avoid the problem of influencing the conductivity when the planar layer is perforated in the prior art. The planarization layer 104 and the spacer layer 14 are usually thicker, and in order to speed up the manufacturing process, it is necessary to heat to speed up the curing of the planarization layer 104 and the spacer layer 14, during the heating and curing process, an unidentified substance is precipitated, and when the unidentified substance falls on the drain electrode 133, the surface of the drain electrode 133 is oxidized and corroded, which affects the conductivity between the pixel electrode 161 and the drain electrode 133.
As shown in fig. 2g, the planarization layer 104 is etched to form a third contact hole 107 corresponding to the bridge electrode 162, and the bridge electrode 162 is exposed from the third contact hole 107. The bridging electrode 162 covers the peripheral trace 135 in the second contact hole 106, so that when the planarization layer 104 is heated and cured, an unknown substance precipitated from the planarization layer 104 is prevented from falling on the surface of the peripheral trace 135, which causes the surface of the peripheral trace 135 to be oxidized and corroded, thereby affecting the binding effect. Since the bridge electrode 162 is made of the transparent electrode layer 16, it is not oxidized and corroded by the unknown substance precipitated from the planarization layer 104.
The embodiment also provides a reflective display panel, which comprises the reflective array substrate. The reflective display panel further includes a counter substrate 20 disposed opposite to the reflective array substrate, and a liquid crystal layer 30 disposed between the reflective array substrate and the counter substrate 20, wherein the counter substrate 20 is disposed on an upper side of the reflective array substrate. The opposite substrate 20 is provided with an upper polarizer 41, the reflective array substrate is provided with a lower polarizer 42, and a transmission axis of the upper polarizer 41 is perpendicular to a transmission axis of the lower polarizer 42.
In this embodiment, the counter substrate 20 is further provided with the common electrode 22 matched with the pixel electrode 161, the liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy), and in an initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is perpendicular to the alignment direction of the positive liquid crystal molecules close to the reflective array substrate, so that the reflective display panel forms a TN type display device. It is understood that the reflective array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30. Of course, In other embodiments, the common electrode 22 may be disposed on the reflective array substrate, and the alignment direction of the positive liquid crystal molecules near the opposite substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules near the reflective array substrate, so as to form a Fringe Field Switching (FFS) mode or an In-Plane Switching (IPS) mode.
The opposite substrate 20 is further provided with a black matrix 21, and the black matrix 21 corresponds to the scan line 111, the data line 131, the thin film transistor, and the peripheral non-display region. In this embodiment, the region of the opposite substrate 20 corresponding to the pixel unit is in a transparent state, that is, the region of the opposite substrate 20 corresponding to the pixel unit is filled with the flat layer, so that the reflective display panel realizes black and white display to be used as electronic paper. Of course, in other embodiments, a color resist layer may be disposed on the opposite substrate 20, and the black matrix 21 separates a plurality of color resist layers, and the color resist layer includes color resist materials of three colors of red (R), green (G), and blue (B), and correspondingly forms sub-pixels of the three colors of red (R), green (G), and blue (B).
In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A reflective array substrate, comprising:
a substrate (10);
the first metal layer (11) is arranged on the upper surface of the substrate (10), the first metal layer (11) comprises a scanning line and a grid electrode (111), and the grid electrode (111) is in conductive connection with the scanning line;
a gate insulating layer (101) covering the first metal layer (11);
a semiconductor layer (12) and a second metal layer (13) disposed on an upper side of the gate insulating layer (101), the second metal layer (13) including a data line (131), a source electrode (132), and a drain electrode (133), the source electrode (132) being conductively connected to the data line (131), the semiconductor layer (12) including an active layer (121) connecting the source electrode (132) and the drain electrode (133);
a first insulating layer (102) provided on an upper side of the gate insulating layer (101), the semiconductor layer (12) and the second metal layer (13) being provided between the gate insulating layer (101) and the first insulating layer (102);
the isolation pad layer (14) is arranged on the upper surface of the first insulating layer (102), the isolation pad layer (14) comprises an isolation pad block (141), projections of the isolation pad block (141) and the drain electrode (133) on the substrate (10) are completely staggered, and the surface, away from the first insulating layer (102), of the isolation pad block (141) is of an uneven structure;
the reflecting metal layer (15) covers the spacer block (141), the reflecting metal layer (15) comprises reflecting blocks (151), and the reflecting blocks (151) are of an uneven structure;
a transparent electrode layer (16) disposed on the upper side of the reflective metal layer (15), wherein the transparent electrode layer (16) comprises a pixel electrode (161), and the pixel electrode (161) is electrically connected with the drain electrode (133);
and a flat layer (104) provided on the upper side of the transparent electrode layer (16).
2. The reflective array substrate of claim 1, wherein the first metal layer (11) further comprises a first capacitor plate (112), the second metal layer (13) further comprises a second capacitor plate (134) mated with the first capacitor plate (112), the second capacitor plate (134) is conductively connected to the drain (133), and the first capacitor plate (112) and the second capacitor plate (134) together form a storage capacitor.
3. The reflective array substrate of claim 1, wherein a second insulating layer (103) is disposed between the reflective metal layer (15) and the transparent electrode layer (16), the second insulating layer (103) separates the reflective block (151) from the pixel electrode (161), the first insulating layer (102) and the second insulating layer (103) are provided with a first contact hole (105), the first contact hole (105) penetrates the first insulating layer (102) and the second insulating layer (103), the first contact hole (105) corresponds to the drain electrode (133), and the pixel electrode (161) is in conductive contact with the drain electrode (133) through the first contact hole (105).
4. The reflective array substrate of claim 3, wherein the second metal layer (13) further comprises a peripheral trace (135) located in a non-display region, the transparent electrode layer (16) further comprises a bridge electrode (162) corresponding to the peripheral trace (135), and the bridge electrode (162) is electrically connected to the peripheral trace (135).
5. The reflective array substrate of claim 4, wherein the first insulating layer (102) and the second insulating layer (103) are provided with second contact holes (106), the second contact holes (106) both penetrate through the first insulating layer (102) and the second insulating layer (103), the second contact holes (106) correspond to the peripheral traces (135), and the bridge electrodes (162) are in conductive contact with the peripheral traces (135) through the second contact holes (106); the flat layer (104) is provided with a third contact hole (107), the third contact hole (107) corresponds to the bridging electrode (162), and the bridging electrode (162) is exposed from the third contact hole (107).
6. A method for manufacturing a reflective array substrate, the method being used for manufacturing the reflective array substrate according to any one of claims 1 to 5, the method comprising:
providing a substrate (10);
forming a first metal layer (11) on the substrate (10), etching the first metal layer (11) and forming a patterned scanning line and a grid electrode (111), wherein the grid electrode (111) is electrically connected with the scanning line;
forming a gate insulating layer (101) on the substrate (10) covering the first metal layer (11);
forming a semiconductor layer (12) and a second metal layer (13) on the upper side of the gate insulating layer (101), etching the second metal layer (13) and forming a patterned data line (131), a source electrode (132) and a drain electrode (133), the source electrode (132) being electrically connected to the data line (131), etching the semiconductor layer (12) and forming a patterned active layer (121), the active layer (121) connecting the source electrode (132) and the drain electrode (133);
forming a first insulating layer (102) on an upper side of the gate insulating layer (101), the semiconductor layer (12) and the second metal layer (13) being provided between the gate insulating layer (101) and the first insulating layer (102);
forming a spacer layer (14) on the first insulating layer (102), etching the spacer layer (14) and forming a patterned spacer block (141), wherein the projections of the spacer block (141) and the drain electrode (133) on the substrate (10) are completely staggered, and the surface of the spacer block (141) far away from the first insulating layer (102) is of an uneven structure;
forming a reflective metal layer (15) on the spacer block (141), etching the reflective metal layer (15) and forming a patterned reflective block (151), wherein the reflective block (151) is of an uneven structure;
etching the first insulating layer (102) and forming a first contact hole (105) corresponding to the drain electrode (133), the drain electrode (133) being exposed from the first contact hole (105);
forming a transparent electrode layer (16) on the upper side of the reflective metal layer (15), etching the transparent electrode layer (16) and forming a patterned pixel electrode (161), wherein the pixel electrode (161) is electrically connected with the drain electrode (133) through the first contact hole (105);
a planarization layer (104) is formed on the upper side of the transparent electrode layer (16).
7. The method for manufacturing the reflective array substrate according to claim 6, wherein a first capacitor plate (112) is further formed when the first metal layer (11) is etched, a second capacitor plate (134) matched with the first capacitor plate (112) is further formed when the second metal layer (13) is etched, the second capacitor plate (134) is electrically connected with the drain electrode (133), and the first capacitor plate (112) and the second capacitor plate (134) together form a storage capacitor.
8. The method for manufacturing the reflective array substrate according to claim 6, wherein when the second metal layer (13) is etched, a peripheral trace (135) located in a non-display region is further formed, and when the transparent electrode layer (16) is etched, a bridge electrode (162) corresponding to the peripheral trace (135) is further formed, and the bridge electrode (162) is electrically connected to the peripheral trace (135).
9. The method of claim 8, wherein before etching the first insulating layer (102), the method further comprises:
forming a second insulating layer (103) on the reflective metal layer (15);
etching the first insulating layer (102) and the second insulating layer (103) to form a first contact hole (105) and a second contact hole (106), wherein the first contact hole (105) and the second contact hole (106) both penetrate through the first insulating layer (102) and the second insulating layer (103), the second contact hole (106) corresponds to the peripheral wiring (135), and the bridging electrode (162) is in conductive connection with the peripheral wiring (135) through the second contact hole (106);
and etching the flat layer (104) and forming a third contact hole (107) corresponding to the bridging electrode (162), wherein the bridging electrode (162) is exposed from the third contact hole (107).
10. A reflective display panel comprising the reflective array substrate according to any one of claims 1 to 5.
CN202111480132.5A 2021-12-06 2021-12-06 Reflective array substrate, manufacturing method thereof and reflective display panel Active CN114236922B (en)

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