CN114221668B - Adaptive power gain control method and receiver - Google Patents
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
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Abstract
The invention provides a gain control method of self-adaptive power, which comprises the following steps: s1, obtaining first signal power according to an output voltage value of a detector; s2, the modulation and demodulation module calculates the power of a second signal according to the demodulation signal; s3, when the receiver is judged to be locked, comparing whether the difference value of the first signal power and the second signal power is larger than a threshold value, and using the second signal power as a third signal power when the difference value is larger than the first threshold value; when the first signal power is not greater than the threshold value, using the first signal power as a third signal power; s4, calculating the attenuation amount according to the third signal power; and S5, controlling an attenuator according to the attenuation amount. When the receiving is locked, the first signal power of the detector is compared with the second signal power calculated by the modulation and demodulation module according to the demodulation signal to obtain the third signal power, the attenuator is controlled according to the attenuation calculated by the third signal power, and the stability of the output signal power of the receiving link is enhanced.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method for gain control of adaptive power and a receiver.
Background
As communication technologies develop and electromagnetic environments become increasingly complex, multipath effects and interfering signals cause the received signal power of the receiver to fluctuate within an uncertain or large dynamic range. The existing solution is to use an Automatic Gain Control (AGC) system to control the gain of the receiving channel in real time, so as to ensure that the communication system can receive signals well.
The receiving stability of the receiver is affected by multiple factors, and particularly under the condition of instantaneous change of signal power, the receiving channel is saturated or the signal power cannot reach the acquisition range of the analog-digital collector ADC, so that the tracking loop of the receiver is unlocked, the signal cannot be correctly tracked, and correct data cannot be demodulated. Mainly caused by the inability of the receiving chain to respond transiently to changes in signal power.
The receiving chain of the existing receiver uses a traditional analog AGC or a digital AGC to adapt to the signal fluctuation situation. However, the analog AGC is easily affected by temperature and working environment conditions and is relatively complex to realize; the digital AGC has the problems of insufficient control range and insufficient precision.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the material described in this section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section.
Disclosure of Invention
In order to solve the above technical problems in the related art, the present invention provides an adaptive power gain control receiver, which includes the following modules:
a filter: the filter is used for receiving the intermediate frequency signal and filtering the intermediate frequency signal;
the program-controlled attenuator: the intermediate frequency signal is attenuated;
an amplifier: the amplifier is used for amplifying signals, the output signal of the amplifier is divided into two paths, one path is sent to the detector, and the other path is sent to the first ADC;
a detector: the detector detects the output power of the amplifier and outputs a first power of the signal;
a first ADC: the analog-to-digital conversion is used for carrying out analog-to-digital conversion on the signal output by the amplifier;
the modulation and demodulation module receives the signal sampled by the first ADC, demodulates the signal to output a demodulated signal and calculates second signal power according to the demodulated signal; the modem module is further configured to compare whether a difference between the first signal power and the second signal power is greater than a threshold when it is determined that the receiver is locked, and use the second signal power as a third signal power when the difference is greater than the first threshold; when the first signal power is not larger than the threshold value, the first signal power is used as a third signal power; calculating the attenuation amount according to the power of the third signal; and controlling the attenuator according to the attenuation amount.
Specifically, in the receiver, the obtaining of the first signal power according to the output voltage value of the detector specifically includes: and according to the output voltage of the detector, performing n-time accumulation and then averaging, and then obtaining the first power of the signal according to the average voltage value. The calculation method is as follows: obtaining the accumulated value Y of the output voltage signals of the detectors for n times,
then, the average voltage is obtained by averaging
Wherein Xi (i =1,2, \8230; n, n is a positive integer) is the output voltage value of the detector. According to the average voltage
And searching the corresponding relation between the voltage and the power to obtain the first signal power.
Specifically, in the receiver, the modulation and demodulation module calculates the second signal power according to the demodulated signal, and the modulation and demodulation module performs signal power estimation according to the I-path signal energy to calculate the second signal power.
Specifically, in the receiver, the modulation and adjustment module stores a corresponding table of the second signal power and the estimated signal power demodulated by the modulation and adjustment module, and the second signal power can be obtained by a table look-up method after the estimated signal power demodulated by the modulation and adjustment module is obtained.
Specifically, in the receiver, the modem module further includes: the first signal power estimated by the detector is used directly as the third signal power when the receiver is not locked.
In a second aspect, another embodiment of the present invention provides a method for adaptive power gain control, which includes the following steps:
s1, obtaining first signal power according to an output voltage value of a detector;
s2, the modulation and demodulation module calculates the power of a second signal according to the demodulation signal;
s3, when the receiver is judged to be locked, comparing whether the difference value of the first signal power and the second signal power is larger than a threshold value, and using the second signal power as a third signal power when the difference value is larger than the first threshold value; when the first signal power is not greater than the threshold value, using the first signal power as a third signal power;
s4, calculating the attenuation amount according to the third signal power;
and S5, controlling an attenuator according to the attenuation amount.
Specifically, the obtaining of the first signal power according to the output voltage value of the detector specifically includes: and according to the output voltage of the detector, performing n-time accumulation and then averaging, and then obtaining the first power of the signal according to the average voltage value. The calculation method is as follows: obtaining the accumulated value Y of the output voltage signals of the detectors for n times,
then, the average voltage is obtained by averaging
Wherein Xi (i =1,2, \8230; n, n is a positive integer) is the output voltage value of the detector. According to average voltage
And searching the corresponding relation between the voltage and the power to obtain the first signal power.
Specifically, the modulation and demodulation module calculates the second signal power according to the demodulation signal, and the modulation and demodulation module performs signal power estimation according to the I-path signal energy so as to calculate the second signal power.
Specifically, the modulation and regulation module stores a corresponding table of the second signal power and the estimated signal power demodulated by the modulation and regulation module, and the second signal power can be obtained by a table look-up method after the estimated signal power demodulated by the modulation and regulation module is obtained.
Specifically, step S3 further includes: the first signal power estimated by the detector is used directly as the third signal power when the receiver is not locked.
When receiving and locking, the invention compares the first signal power output by the detector with the second signal power calculated by the FPGA according to the demodulation signal in real time to obtain the actual signal power, namely the third signal power, calculates the attenuation according to the third signal power, and controls the attenuator according to the attenuation, thereby effectively reducing the influence of accidental interference signals on the output power of the receiving link and enhancing the stability of the output signal power of the receiving link.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a receiver structure for adaptive power gain control according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of adaptive power gain control provided in accordance with an embodiment of the present invention;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived from the embodiments of the present invention by a person skilled in the art, are within the scope of the present invention.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a receiver for adaptive power gain control according to this embodiment, where the receiver for adaptive power gain control according to this embodiment includes:
a filter: the filter is used for receiving the intermediate frequency signal, filtering the intermediate frequency signal and removing clutter signals outside the signal. In this embodiment, two filters are used, and the two filters can receive two paths of intermediate frequency signals simultaneously and perform filtering processing on the two paths of intermediate frequency signals.
Program-controlled attenuator: for attenuating the intermediate frequency signal.
An amplifier: for amplifying a signal, the amplifier is a fixed gain method, and the fixed gain may be selected according to actual circuit requirements, which is not further limited in this embodiment. The output signal of the amplifier is divided into two paths, one path is sent to the detector, and the other path is sent to the first ADC.
A detector: the detector detects the output power of the amplifier and outputs a first power of the signal, wherein the first power represents the power of the intermediate frequency signal actually measured in a hardware mode. The detector is a power detection device, outputs different voltage values according to different signal powers, and then obtains the power of the signal after obtaining the voltage value. The detector stores the corresponding relation between the voltage and the power in advance, the corresponding relation between the voltage and the power can be built in a manufacturer for producing the detector when the detector is on the spot, and the detector only needs to search the corresponding relation between the voltage and the power according to the obtained voltage and output the corresponding power. In addition, the detector does not need to store the corresponding relation between the voltage and the power in advance, the detector only needs to output the voltage, and the circuit with the execution function is used for executing the conversion between the voltage and the power in the circuit design.
The first power of the output signal of the detector is specifically: and according to the output voltage of the detector, performing n times of accumulation and then averaging, and then obtaining the first power of the signal according to the average voltage value. The calculation method is as follows: obtaining the accumulated value Y of the output voltage signals of the detectors for n times,
then, the average voltage is obtained by averaging
Wherein Xi (i =1,2, \8230; n, n is a positive integer) is the output voltage value of the detector. According to average voltage
And searching the corresponding relation between the voltage and the power to obtain the first signal power.
A first ADC: the digital signal processing circuit is used for converting an analog signal into a digital signal, the output data of the ADC is an LVDS interface, and the output data is used for signal processing of the FPGA.
And the modulation and demodulation module is an FPGA and also comprises an ADC module. The detection voltage is acquired by an ADC in the FPGA to be converted into digital quantity, adaptive gain control calculation is carried out, a control signal is given out, and the attenuation of the programmable attenuator is controlled to ensure the stability of the output power of the amplifier. The modulation and demodulation module also receives the signal sampled by the first ADC, demodulates the signal and outputs a demodulated signal.
Specifically, the FPGA calculates the second signal power in real time according to the demodulation signal. The specific FPGA carries out signal power estimation according to the I-path signal energy so as to calculate the second signal power.
Specifically, the second signal power estimated according to the I-path signal energy sometimes cannot represent the real power of the signal, and in order to enable the second signal power to reflect the real power of the signal, the FPGA in this embodiment stores a correspondence table between the second signal power and the estimated signal power demodulated by the FPGA, and when the estimated signal power demodulated by the FPGA is obtained, the second signal power can be obtained through a table look-up method.
And the FPGA obtains a third signal power according to the first signal power, the second signal power and the locking state of the receiver, wherein the third signal power represents the actual signal power.
The received locking state comprises two states of locking and unlocking. The receiver lock is a state quantity of baseband demodulation, and can determine whether to lock to a correct signal.
The first signal power estimated by the detector is used directly as the third signal power when the receiver is not locked.
When the receiver is locked, comparing whether the difference value of the first signal power and the second signal power is larger than a threshold value, and when the difference value is larger than the first threshold value, using the second signal power as a third signal power; and when the first signal power is not larger than the threshold value, using the first signal power as the third signal power.
The attenuation is calculated according to the third signal power, and one calculation method of the embodiment is to subtract the third signal power from-10 dBFS of the ADC full scale power to obtain the attenuation. The second signal power in this embodiment is an output power passing through the amplifier, and the FPGA calculates the second signal power in real time according to the demodulated signal, where the second signal power is a signal power actually required to be acquired by the ADC of the receiver.
The FPGA controls the attenuator according to the attenuation amount, and the control of the attenuator only needs to refer to an attenuator manual. After the attenuation is obtained, corresponding attenuation is directly carried out through the FPGA control attenuator, and closed-loop control of link gain is completed, so that self-adaptive control of a receiving link is completed, and the output power of the receiving link is kept stable.
In the embodiment, when the receiving is locked, the first signal power output by the detector is compared with the second signal power calculated by the FPGA according to the demodulation signal in real time to obtain the actual signal power, that is, the third signal power, the attenuation is calculated according to the third signal power, and the attenuator is controlled according to the attenuation, so that the influence of accidental interference signals on the output power of the receiving link can be effectively reduced, and the stability of the output signal power of the receiving link is enhanced.
Example two
Referring to fig. 2, fig. 2 is a flowchart of the present embodiment further disclosing a method for controlling a gain of adaptive power, where the method for controlling a gain of adaptive power disclosed in the present embodiment operates in a receiver for controlling a gain of adaptive power in the first embodiment, and specifically the following steps are executed by the modem module:
s1, obtaining first signal power according to an output voltage value of a detector;
the detector is a power detection device, outputs different voltage values according to different signal powers, and then obtains the power of the signal after obtaining the voltage value. The detector stores the corresponding relation between the voltage and the power in advance, the corresponding relation between the voltage and the power can be built in a manufacturer for producing the detector when the detector is on the spot, and the detector only needs to search the corresponding relation between the voltage and the power according to the obtained voltage and output the corresponding power. In addition, the detector does not need to store the corresponding relation between the voltage and the power in advance, the detector only needs to output the voltage, and the circuit with the execution function is used for executing the conversion between the voltage and the power in the circuit design.
The first power of the output signal of the detector is specifically: and according to the output voltage of the detector, performing n times of accumulation and then averaging, and then obtaining the first power of the signal according to the average voltage value. The calculation method is as follows: acquiring the accumulated value Y of the output voltage signals of the detectors for n times,
then, the average voltage is obtained by averaging
Wherein Xi (i =1,2, \8230; n, n is a positive integer) is the output voltage value of the detector. According to average voltage
And searching the corresponding relation between the voltage and the power to obtain the first signal power.
S2, the modulation and demodulation module calculates the power of a second signal according to the demodulation signal;
the modulation and demodulation module is an FPGA and also comprises an ADC module. The detection voltage is acquired by an ADC in the FPGA to be converted into digital quantity, adaptive gain control calculation is carried out, a control signal is given out, and the attenuation of the programmable attenuator is controlled to ensure the stability of the output power of the amplifier. The modulation and demodulation module also receives the signal sampled by the first ADC, demodulates the signal and outputs a demodulated signal.
Specifically, the FPGA calculates the second signal power in real time according to the demodulation signal. The specific FPGA carries out signal power estimation according to the I-path signal energy so as to calculate the second signal power.
Specifically, the second signal power estimated according to the I-path signal energy sometimes cannot represent the real power of the signal, and in order to enable the second signal power to reflect the real power of the signal, the FPGA in this embodiment stores a correspondence table between the second signal power and the estimated signal power demodulated by the FPGA, and when the estimated signal power demodulated by the FPGA is obtained, the second signal power can be obtained by a table lookup method.
S3, when the receiver is judged to be locked, comparing whether the difference value of the first signal power and the second signal power is larger than a threshold value, and using the second signal power as a third signal power when the difference value is larger than the first threshold value; when the first signal power is not larger than the threshold value, the first signal power is used as a third signal power;
the received locking state comprises a locking state and an unlocking state. The receiver lock is a state quantity of baseband demodulation, and can determine whether to lock to a correct signal.
The first signal power estimated by the detector is used directly as the third signal power when the receiver is not locked.
And S4, calculating the attenuation amount according to the third signal power.
One way to calculate this embodiment is to subtract the third signal power from-10 dBFS of the ADC full scale power to obtain the attenuation. The second signal power in this embodiment is an output power passing through the amplifier, and the FPGA calculates the second signal power in real time according to the demodulated signal, where the second signal power is a signal power actually required to be acquired by the ADC of the receiver.
And S5, controlling the attenuator according to the attenuation amount. The FPGA controls the attenuator according to the attenuation amount, and the control of the attenuator only needs to refer to an attenuator manual. After the attenuation quantity is obtained, the FPGA control attenuator directly performs corresponding attenuation to complete link gain closed-loop control, thereby completing the self-adaptive control of the receiving link and keeping the output power of the receiving link stable.
In the embodiment, when the receiving is locked, the first signal power output by the detector is compared with the second signal power calculated by the FPGA according to the demodulation signal in real time to obtain the actual signal power, that is, the third signal power, the attenuation is calculated according to the third signal power, and the attenuator is controlled according to the attenuation, so that the influence of accidental interference signals on the output power of the receiving link can be effectively reduced, and the stability of the output signal power of the receiving link is enhanced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. An adaptive power gain control receiver, comprising the following modules:
a filter: the filter is used for receiving the intermediate frequency signal and filtering the intermediate frequency signal;
program-controlled attenuator: the filter is used for attenuating the signal output by the filter;
an amplifier: the amplifier is used for amplifying the signal output by the programmable attenuator, the output signal of the amplifier is divided into two paths, one path is sent to the detector, and the other path is sent to the first ADC;
a detector: the detector detects the output power of the amplifier and outputs a first signal power;
a first ADC: the analog-to-digital conversion is used for carrying out analog-to-digital conversion on the signal output by the amplifier;
the modulation and demodulation module receives the signal sampled by the first ADC, demodulates the signal to output a demodulated signal and calculates second signal power according to the demodulated signal; the modulation and demodulation module is further configured to compare whether a difference between the first signal power and the second signal power is greater than a threshold value when it is determined that the receiver is locked, and use the second signal power as a third signal power when the difference is greater than the threshold value; when the first signal power is not greater than the threshold value, using the first signal power as a third signal power; calculating the attenuation amount according to the power of the third signal; and controlling the programmable attenuator according to the attenuation amount.
2. The receiver of claim 1, wherein: the power of the first signal output by the detector is specifically as follows: according to the output voltage of the detector, after n times of accumulation, averaging is carried out to obtain an average voltage value, then the first signal power of the signal is obtained according to the average voltage value, and the calculation mode is as follows: acquiring the accumulated value Y of the output voltage of the detector for n times,
then, the average voltage is obtained by averaging
Wherein Xi (i =1,2, \8230; n, n is a positive integer) is the output voltage value of the detector; according to average voltage
And searching the corresponding relation between the voltage and the power to obtain the first signal power.
3. The receiver of claim 1, wherein: the modulation and demodulation module calculates the power of a second signal according to the demodulation signal, and the modulation and demodulation module carries out signal power estimation according to the energy of the I-path signal so as to calculate the power of the second signal.
4. The receiver of claim 3, wherein: the modulation and demodulation module stores a corresponding table of the second signal power and the demodulated signal power demodulated by the modulation and demodulation module, and the second signal power can be obtained by a table look-up method after the demodulated signal power demodulated by the modulation and demodulation module is obtained.
5. The receiver of claim 1, the modem module further to: when the receiver is not locked, the first signal power obtained by the detector is directly used as the third signal power.
6. A method for controlling gain of adaptive power, applied in the adaptive power gain control receiver according to any one of claims 1-5, wherein: the method comprises the following steps:
s1, obtaining first signal power according to an output voltage value of a detector;
s2, the modulation and demodulation module calculates the power of a second signal according to the demodulation signal;
s3, when the receiver is judged to be locked, comparing whether the difference value of the first signal power and the second signal power is larger than a threshold value, and using the second signal power as a third signal power when the difference value is larger than the threshold value; when the first signal power is not greater than the threshold value, using the first signal power as a third signal power;
s4, calculating the attenuation amount according to the third signal power;
and S5, controlling the programmable attenuator according to the attenuation amount.
7. The method of claim 6, wherein: obtaining the first signal power according to the output voltage value of the detector specifically comprises: according to the output voltage of the detector, after n times of accumulation, averaging is carried out to obtain an average voltage value, then the first signal power of the signal is obtained according to the average voltage value, and the calculation mode is as follows: acquiring the accumulated value Y of the output voltage of the detector for n times,
then, the average voltage is obtained by averaging
Wherein Xi (i =1,2, \8230; n, n is a positive integer) is the output voltage value of the detector; according to average voltage
And searching the corresponding relation between the voltage and the power to obtain the first signal power.
8. The method of claim 6, wherein: the modulation and demodulation module calculates the power of a second signal according to the demodulation signal, and the modulation and demodulation module carries out signal power estimation according to the energy of the I-path signal so as to calculate the power of the second signal.
9. The method of claim 8, wherein: the modulation and demodulation module stores a corresponding table of the second signal power and the demodulated signal power demodulated by the modulation and demodulation module, and the second signal power can be obtained by a table look-up method after the demodulated signal power demodulated by the modulation and demodulation module is obtained.
10. The method of claim 6, wherein: wherein step S3 further comprises: when the receiver is not locked, the first signal power obtained by the detector is directly used as the third signal power.
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