CN114220379A

CN114220379A - Control circuit, display panel and pixel circuit driving method

Info

Publication number: CN114220379A
Application number: CN202210049713.1A
Authority: CN
Inventors: 奚鹏博
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-09-07
Filing date: 2022-01-17
Publication date: 2022-03-22
Anticipated expiration: 2042-01-17
Also published as: CN114220379B; TW202311824A; TWI795902B

Abstract

A pixel circuit driving method includes the following steps: in a first frame period, conducting a control node of the pixel circuit to a first voltage source through a first conversion circuit, wherein the voltage of the first voltage source is reduced along with time; driving, by the pixel circuit, the light emitting element according to a supply power and a first data signal until a drive switch in the pixel circuit is turned off according to a voltage of a first voltage source; in a second frame period, the control node is switched to be conducted to a second voltage source through a second conversion circuit, wherein the voltage of the second voltage source is reduced along with time; and driving, by the pixel circuit, the light emitting element according to the supply power and the second data signal until the driving switch in the pixel circuit is turned off according to the voltage of the second voltage source. The disclosure also relates to a control circuit and a display panel.

Description

Control circuit, display panel and pixel circuit driving method

Technical Field

The present disclosure relates to a display panel, a control circuit and a driving method of a pixel circuit, and more particularly, to a technique capable of controlling a driving time of a light emitting element according to a power supply and a data signal.

Background

With the rapid development of electronic technology, display devices have been widely used in people's lives, such as smart phones or computers. Taking a liquid crystal display as an example, each pixel on the display is connected to a data line and a scan line, so as to perform the actions of resetting, compensating voltage, emitting light and the like one by one according to the signal sent by the controller, thereby presenting the corresponding picture. The controller must precisely control the level of each signal to ensure the display quality of the display device. Meanwhile, the driving method of the display device among a plurality of frames will also affect the design of the internal circuit and the quality of the displayed image.

Disclosure of Invention

The present disclosure relates to a pixel circuit driving method, comprising the following steps: in a first frame period, conducting a control node of the pixel circuit to a first voltage source through a first conversion circuit, wherein the voltage of the first voltage source is reduced along with time; driving, by the pixel circuit, the light emitting element according to a supply power and a first data signal until a drive switch in the pixel circuit is turned off according to a voltage of a first voltage source; in a second frame period, the control node is switched to be conducted to a second voltage source through a second conversion circuit, wherein the voltage of the second voltage source is reduced along with time; and driving, by the pixel circuit, the light emitting element according to the supply power and the second data signal until the driving switch in the pixel circuit is turned off according to the voltage of the second voltage source.

The disclosure also relates to a control circuit comprising a first conversion circuit and a second conversion circuit. The first conversion circuit comprises a first conversion switch and is electrically connected to a control node of the control switch in the pixel circuit. The control node is electrically connected with a first voltage source through a first change-over switch, and the voltage of the first voltage source is reduced along with time. The second converting circuit comprises a second converting switch and is electrically connected to the control node of the control switch. The control node is electrically connected with a second voltage source through a second transfer switch, and the voltage of the second voltage source is reduced along with time. During a first frame period, the first switch is turned on, the second switch is turned off to turn on the control node to the first voltage source, and the pixel circuit drives the light emitting element according to the power supply and the first data signal. In a second frame period, the first switch is turned off, the second switch is turned on to turn on the control node to the second voltage source, and the pixel circuit drives the light emitting element according to the power supply and the second data signal.

The disclosure also relates to a display panel including at least one pixel circuit and at least one control circuit. The pixel circuit is used for driving the light-emitting element and comprises a control switch. The control circuit comprises a first conversion circuit and a second conversion circuit. The first conversion circuit comprises a first conversion capacitor and a first conversion switch. The first end of the first conversion capacitor is electrically connected to a first voltage source, the second end of the first conversion capacitor is electrically connected to the control node of the control switch through the first conversion switch, and the voltage of the first voltage source is reduced along with time. The second conversion circuit comprises a second conversion capacitor and a second conversion switch. The first end of the second conversion capacitor is electrically connected to the second voltage source, the second end of the second conversion capacitor is electrically connected to the control node through the second conversion switch, and the voltage of the second voltage source is reduced along with time.

Accordingly, the pixel circuit controls the driving switch according to the two voltage sources in different frame periods to control the time for driving the light emitting element. Therefore, when applied to a display panel, a plurality of pixel circuits in the display panel can share the two voltage sources without independently configuring a corresponding voltage source for each pixel circuit.

Drawings

Fig. 1A is a schematic diagram of a display panel.

Fig. 1B is a schematic diagram of a pixel circuit.

FIG. 2 is a schematic diagram of a display panel according to some embodiments of the present disclosure.

FIG. 3 is a waveform diagram of various signals according to some embodiments of the present disclosure.

FIG. 4 is a schematic diagram of a pixel circuit and control circuitry according to some embodiments of the present disclosure.

Fig. 5 is a flow chart of a driving method according to some embodiments of the present disclosure.

Fig. 6 is a waveform diagram of a pull-up control signal, a pull-down control signal, a first control signal, and a second control signal according to some embodiments of the present disclosure.

FIGS. 7A and 7B are waveform diagrams of a simulation test performed according to a portion of an embodiment of a control circuit according to the present disclosure.

Fig. 8A to 8C are schematic views of a display panel according to some embodiments of the disclosure. Wherein the reference numerals are as follows:

PA: display panel

100: pixel circuit

200: control circuit

210: first conversion circuit

220: second conversion circuit

230: voltage setting circuit

810-830: display panel

811: pixel circuit

812: control circuit

821: pixel circuit

822: control circuit

831: pixel circuit

832: pixel circuit

833: control circuit

834: control circuit

T1: driving switch

T2: driving switch

T3: current switch

Tc: control switch

t1-t 10: point in time

Na: control terminal

Nb: control node

Nc: setting a node

Ca-Cc: capacitor with a capacitor element

W1: first change-over switch

W2: second change-over switch

C1: first conversion capacitor

C2: second conversion capacitor

Vdd: supply voltage

Vp: clamping voltage

Vdata: data signal

Vdh: DC voltage source

Vdl: reference voltage source

f 1: first frame period

f 2: second frame period

S1-S4: control signal

Sa: a first voltage source

Sb: second voltage source

Sg: scanning signal

Sg 1: scanning signal

Sg 2: scanning signal

Sx: mixing control signals

L: light emitting element

And Vn: voltage of

P100: display panel

P110: pixel circuit

P120: control circuit

P130: light emitting element

G1-G2: scanning signal

SL: scanning line

DL: data line

Vt: control signal

Ta: driving switch

Tb: control switch

Nx: control node

Detailed Description

In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.

When an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also be used to indicate that two or more elements are in a coordinated operation or interaction with each other. Moreover, although the terms first, second, …, etc. may be used herein to describe various elements, these terms are only used to distinguish one element or operation from another element or operation described by the same technical terms. Unless the context clearly dictates otherwise, the terms do not specifically refer or imply an order or sequence nor are they intended to limit the invention.

Fig. 1A and 1B are schematic diagrams illustrating an embodiment of a display panel P100. As shown in fig. 1A, the display panel P100 includes a plurality of pixel circuits P110 and a plurality of control circuits P120. The pixel circuit P110 is configured to be turned on one by one according to the scan signals (G1, G2) of the scan line SL and the voltage on the data line DL to drive the light emitting element P130.

The control circuit P120 is used for providing a control signal Vt to each pixel circuit P110 to control the time for each pixel circuit P110 to drive the light emitting device P130. In other words, the higher the luminance the light emitting element P130 needs to exhibit, the longer the driving time of the pixel circuit P110 will be. In one embodiment, the control signal Vt is formed according to a Pulse Width Modulation (PWM) signal, and its waveform may be decreasing with time. Since the generation of the control signal Vt is well understood by those skilled in the art, it is not described herein.

As shown in fig. 1B, in an embodiment, the pixel circuit P110 has a control switch Ta, and a control node Nx of the control switch Ta is electrically connected to a control signal source through a capacitor to receive a control signal Vt. The voltage of the control signal Vt may vary periodically with time (e.g., gradually decrease from a high level in one frame period). When the voltage at the control node Nx is smaller than a threshold value (e.g., the turn-on voltage of the control switch Ta), the control switch Ta is turned on, so that the clamping voltage Vh turns off the driving switch Tb in the pixel circuit P110, and the pixel circuit P110 stops driving the light emitting element.

In other words, the control circuit P120 is used for receiving the control signal Vt and controlling the time for the pixel circuit P110 to drive the light emitting device P130 according to the control signal Vt. The control method can be called "Progressive analog scan" (Progressive analog scan).

The circuits shown in fig. 1A and 1B can still be improved. For example, when the resolution of the display panel P100 is high (i.e., the number of the pixel circuits P110 is very high), since the display panel P100 needs to set a corresponding signal source for each pixel circuit P110 to independently generate the control signal Vt, too many signal sources will cause driving difficulties, occupy too much space, and have too high cost.

Fig. 2 is a schematic diagram of a display panel PA according to some embodiments of the present disclosure. The display panel PA includes a plurality of pixel circuits 100 and a plurality of control circuits 200 (only one pixel circuit 100 and one control circuit 200 are drawn in fig. 2). The pixel circuit 100 is activated according to the data signal Vdata transmitted from the data line and the scan signal Sg transmitted from the scan line, and performs operations such as reset, write, compensation, and driving.

In one embodiment, the pixel circuit 100 includes a current switch T3, a first driving switch T1, a second driving switch T2, and a control switch Tc. The current switch T3 is used to control the driving current provided by the power supply Vdd to the pixel circuit 100, and its control terminal is connected to the capacitor Cc. The first driving switch T1 and the second driving switch T2 are used to control the time length of the driving current provided to the light emitting element L (i.e. the light emitting time of the light emitting element L). The control terminal of the first driving switch T1 is electrically connected to the data line to receive the corresponding data signal Vdata, so that the data signal Vdata can be written into the capacitor Ca.

The control switch Tc is electrically connected between the control terminal Na of the first driving switch T1 and the clamping voltage Vp, and is turned on or off according to the control node Nb. When the control switch Tc is turned on, the clamping voltage Vp is inputted to the control terminal Na of the first driving switch T1 through the control switch Tc. The clamping voltage Vp is used to turn off the first driving switch T1, so that the pixel circuit 100 stops driving the light emitting element L.

In one embodiment, the pixel circuit 100 further includes a writing circuit (not shown) for writing the data signal Vdata provided by the data line into the capacitor Ca. The present disclosure does not limit the composition of the detailed components of the write circuit. Since the data writing principle of the pixel circuit can be understood by those skilled in the art, it is not described one by one herein. The subsequent paragraphs will focus on the way in which the control circuit 200 controls the control switch Tc.

In one embodiment, the control circuit 200 includes a first converting circuit 210 and a second converting circuit 220. The first converting circuit 210 includes a first converting switch W1 and is electrically connected to the control node Nb of the control switch Tc (in the embodiment, the control circuit 200 is connected to the control node Nb through a capacitor Cb). In other words, the control node Nb is electrically connected to the first voltage source Sa through the first transfer switch W1. The first switch W1 is controlled by a first control signal S1. The voltage supplied by the first voltage source Sa is a periodic variation with time, i.e. a waveform of a Progressive analog scan (Progressive analog Sweep). For example: the voltage of the first voltage source Sa is gradually decreased from a high level to a low level during odd frame periods (e.g., displaying

frames

1, 3, and 5) of the display panel PA, and is restored to the high level during even frame periods (e.g., displaying frames 2, 4, and 6).

Similarly, the second converting circuit 220 includes a second converting switch W2 electrically connected to the control node Nb of the control switch Tc. The control node Tc is electrically connected to the second voltage source Sb through the second switch W2. The second switch W2 off is controlled by the second control signal S2. The voltage provided by the second voltage source Sb is periodically varied with time, for example: the voltage of the second voltage source Sb is gradually decreased from a high level to a low level in an even frame period (e.g., when displaying frames 2, 4, and 6) of the display panel PA, and is restored to the high level in an odd frame period (e.g., when displaying

frames

1, 3, and 5).

The control circuit 200 sequentially receives different voltage sources in different frame periods, so that the display panel PA can normally drive all the pixel circuits 100 even if only two signal sources (i.e., the first voltage source Sa and the second voltage source Sb) are disposed. For example, in odd-numbered frame periods (e.g., the first frame period), the first switch W1 is turned on and the second switch W2 is turned off to turn on the control node Nb to the first voltage source Sa. At this time, the pixel circuit 100 drives the light emitting element L according to the power supply Vdd and the first data signal written in advance by the data line. On the other hand, in an even-numbered frame period (e.g., the second frame period), the first transfer switch W1 is turned off and the second transfer switch W2 is turned on to turn on the control node Nb to the second voltage source Sb. At this time, the pixel circuit 100 drives the light emitting element L according to the power supply Vdd and the second data signal.

Specifically, when the control node Nb is turned on by the first voltage source Sa (or the second voltage source Sb), the voltage of the first voltage source Sa (or the second voltage source Sb) gradually decreases from a high level to a low level in one frame period, and the voltage of the control node Nb also changes accordingly. When the voltage of the control node Nb is greater than the threshold value (i.e., the on-voltage of the control switch Tc), the control switch Tc is maintained in the off state, and the pixel circuit 100 drives the light emitting element L according to the first data signal (or the second data signal). In contrast, when the voltage at the control node Nb is smaller than the threshold value, the control switch Tc will be turned on, resulting in the clamping voltage Vp being written into the control terminal Na of the first driving switch T1, such that the first driving switch T1 is turned off and the pixel circuit 100 stops driving the light emitting element L.

As shown in fig. 2, in some embodiments, the first converting circuit 210 further includes a first converting capacitor C1. A first terminal of the first converting capacitor C1 is electrically connected to the first voltage source Sa, and a second terminal of the first converting capacitor C1 is electrically connected to the control node Nb through the first switch W1. Since the two ends of the first conversion capacitor C1 are the first voltage source Sa and the control node Nb, respectively, when the voltage of the first voltage source Sa changes, the voltage of the control node Nb also changes according to the capacitive coupling effect.

Similarly, the second converting circuit 220 further includes a second converting capacitor C2. The first terminal of the second converting capacitor C2 is electrically connected to the second voltage source Sb, and the second terminal of the second converting capacitor C2 is electrically connected to the control node Nb through the second switch W2. When the voltage of the second voltage source Sb changes, the voltage of the control node Nb also changes accordingly according to the capacitive coupling effect.

In addition, in the same frame period, each pixel circuit 100 on the display panel PA controls the time for driving the light emitting device L by the same voltage source. For example, in the first frame period, each pixel circuit 100 controls the voltage of the control node Nb according to the first voltage source Sa to turn on or off the first driving switch T1. In the second frame period, each pixel circuit 100 controls the voltage of the control node Nb according to the second voltage source Sb instead.

FIG. 3 is a waveform diagram illustrating various signals on a display panel according to some embodiments of the present disclosure. The scan signals Sg1 and Sg2 are used to trigger the pixel circuit 100 in different frame periods. The first control signal S1 and the second control signal S2 are used to trigger the corresponding converting circuits. The voltage Vn is used to represent the voltage at the control node Nb of different pixel circuits 100. In one embodiment, the voltage waveforms of the first voltage source Sa and the second voltage source Sb are the same but separated by a delay time. As shown, the first voltage source Sa is delayed with respect to the second voltage source Sb. In the first frame period f1, the first voltage source Sa gradually decreases from a high level (e.g., 10 volts), and the voltage varies inversely with time. Therefore, each pixel circuit 100 obtains a voltage difference of the first voltage source Sa for control according to the current gray-scale value.

Accordingly, when the display panel PA scans to the last row of pixel circuits 100, the pixel circuits 100 may control the first driving switch W1 to be turned on or off according to the interval of the first voltage source "6-3 volts". As can be seen from the figure, when the first voltage source Sa is lowered to 5 volts, the second frame period f2 is entered, but the remaining voltage difference (5 volts) is not enough to be driven for a new frame period, so that the display panel PA controls the pixel circuits 100 in the first row by the second voltage source Sb during the second frame period f 2. In addition, when the second frame period f2 is close to the end, the first voltage source Sa is restored to the original high level (e.g. 10 volts) for driving in the third frame period.

Fig. 4 is a detailed circuit diagram of the control circuit 200 in the display panel PA according to the present disclosure. The details of the present embodiment are described herein with reference to fig. 4 and 5. In fig. 4, similar components related to the embodiment of fig. 2 are denoted by the same reference numerals for easy understanding, and the specific principles of the similar components have been described in detail in the previous paragraphs, which are not repeated herein if necessary for description if there is a cooperative relationship between the components in fig. 4.

As shown in fig. 4, in an embodiment, the control circuit 200 further includes a voltage setting circuit 230. The voltage setting circuit 230 is used for converting a segment of absolute voltage difference provided by the first voltage source Sa and the second voltage source Sb into a relative voltage difference. In other words, in the first frame period f1, two different pixel circuits 100 capture different voltage differences (e.g., 9 volts to 5 volts, 7 volts to 3 volts), and the control circuit 200 converts the two voltage differences into the same voltage difference (e.g., 4 volts to 0 volts) to control the on-time of the first driving switch T1.

The voltage setting circuit 230 is electrically connected between the first switch W1, the second switch W2 and the control node Nb. The voltage setting circuit 230 is used to set the voltage of the control node Nb to the first high level before the pixel circuit 100 drives the light emitting element L, so as to ensure that the control switch Tc can be turned off and the first driving switch T1 can be turned on. After driving the light emitting device L, the voltage setting circuit 230 is further configured to set the voltage of the control node Nb to the first low potential to ensure that the control switch Tc is turned on, so that the first driving switch T1 is turned off by the clamping voltage Vp.

Specifically, the voltage setting circuit 230 includes a pull-up voltage switch W3 and a pull-down voltage switch W4. The pull-up voltage switch W3 is turned on according to the pull-up control signal S3 to set the voltage of the set node Nc to the first high potential. Since the setting node Nc is connected to the control node Nb via a capacitor, the voltage of the control node Nb changes as the voltage of the setting node Nc changes. That is, the voltage of the control node Nb is also set to the first high potential. Similarly, the pull-down voltage switch W4 is turned on according to the pull-down control signal S4 to set the voltages of the setting node Nc and the control node Nb to the first low level. In one embodiment, the first high voltage is generated according to the DC voltage source Vdh, and the second high voltage is the reference voltage source Vdl (e.g., ground).

Fig. 5 is a flowchart of a control method of the pixel circuit according to the disclosure. FIG. 6 is a waveform diagram of the pull-up control signal S3, the pull-down control signal S4, the first control signal S1 and the second control signal S2. The operation of the present disclosure is described herein with reference to fig. 4-6.

In step S501, at a time point t1 of the first frame period f1, the pull-up control switch W3 is turned on, and the pull-down control switch W4, the first switch W1 and the second switch W2 are turned off. At this time, the voltage of the control node Nb will be controlled to the first high potential.

In step S502, the pull-up control switch W3 and the first switch W1 are turned on, and the pull-down control switch W4 and the second switch W2 are turned off between time points t 2-t 3 of the first frame period f 1. At this time, the first terminal of the first converting capacitor receives the first voltage source Sa, and the voltage of the second terminal thereof is controlled to the first high potential through the first converting switch W1.

In step S503, the first switch W1 is turned on, and the pull-up control switch W3, the pull-down control switch W4 and the second switch W2 are turned off during a time point t 3-t 4 of the first frame period f1, so that the control node Nb is turned on to the first voltage source Sa through the first conversion circuit 210. At this time, the voltage at the control node Nb is no longer fixed at the first high potential, and the voltage variation across the first converting capacitor C1 should be kept consistent by the capacitive coupling effect. Therefore, when the first voltage source Sa decreases with time, the voltage at the control node Nb also decreases accordingly. For example: when the first voltage source drops from 10 volts to 6 volts, the voltage at the control node Nb also drops from 4 volts, which is the first high voltage, to 0 volts. In other words, even if the voltage difference interval of the first voltage source Sa used by each pixel circuit 100 is different (e.g., 10-6 volts, 8-4 volts), the voltage of each control node Nb can be controlled to gradually decrease from the same first high voltage level by the coupling effect of the first transfer capacitor C1, and the decreasing speed is the same as the variation of the first voltage source Sa.

In step S504, when the voltage at the control node Nb is higher than the threshold value, the control switch Tc is turned off, so that the pixel circuit 100 can drive the light emitting element L according to the power supply Vdd and the first data signal written in the data line in advance until the first driving switch T1 is turned off.

In step S505, when the voltage at the control node Nb decreases with the decrease of the first voltage source Sa and is lower than the threshold value, the control switch Tc is turned on, so that the clamping voltage Vp is written into the pixel circuit 100 and the first driving switch T1 is turned off. The pixel circuit 100 will stop driving the light emitting element L. In some embodiments, at the time point T5 of the first frame period f1, the pull-down control switch W4 is turned on, and the pull-up control switch W3, the first switch W1 and the second switch W2 are turned off, so that the voltage at the control node Nb is set to the first low potential, ensuring that the control switch Tc can be turned on and the first driving switch T1 can be turned off.

The aforementioned steps S501 to S505 are the operation steps of the display panel PA in the first frame period f 1. Steps S506 to S510 are used to describe the operation steps of the display panel PA in the second frame period f 2. The first frame period f1 is substantially the same as the step of the second frame period f2 and the control node will instead be switched on to the second voltage source. The voltage of the second voltage source Vb decreases with time but with a delay time difference from the first voltage source Va.

In step S506, at the time point t6 of the second frame period f2, the pull-up control switch W3 is turned on again, and the pull-down control switch W4, the first switch W1 and the second switch W2 are turned off. At this time, the voltage of the control node Nb will be controlled to the first high potential.

In step S507, the pull-up control switch W3 and the second switch W2 are turned on, and the pull-down control switch W4 and the first switch W1 are turned off between time points t 7-t 8 of the second frame period f 2. At this time, the first terminal of the second converting capacitor C2 of the second converting circuit 220 receives the second voltage source Sb, and the voltage of the second terminal thereof is controlled to the first high voltage level by the second converting switch W2.

In step S508, the second switch W2 is turned on, and the pull-up control switch W3, the pull-down control switch W4 and the first switch W1 are turned off during a time point t 8-t 9 of the second frame period f2, so that the control node Nb is turned on to the second voltage source Sb by the second switch circuit 220. At this time, the voltage at the control node Nb is no longer fixed at the first high potential, and the voltage variation across the second conversion capacitor C2 should be kept consistent according to the capacitive coupling effect. Therefore, as the second voltage source Sb decreases over time, the voltage at the control node Nb likewise decreases accordingly.

In step S509, when the voltage at the control node Nb is higher than the threshold value, the control switch Tc is turned off, so that the pixel circuit 100 can drive the light emitting element L according to the power supply Vdd and the second data signal written in advance by the data line until the first driving switch T1 is turned off.

In step S510, when the voltage at the control node Nb decreases with the decrease of the second voltage source Sb and is lower than the threshold value, the control switch Tc is turned on, so that the clamping voltage Vp is written into the pixel circuit 100 and the first driving switch T1 is turned off. In some embodiments, the pull-down control switch W4 is turned on and the pull-up control switch W3, the first switch W1 and the second switch W2 are turned off between the time point T10 of the second frame period f2, so that the voltage at the control node Nb is set to the first low potential, ensuring that the control switch Tc can be turned on and the first driving switch T1 can be turned off.

Fig. 7A and 7B are waveform diagrams of simulation tests performed according to some embodiments of the control circuit 200 of the present disclosure. The mixing control signal Sx in fig. 7A is generated by combining the first voltage source Sa and the second voltage source Sb. The high level of the mixing control signal Sx represents that the first control signal S1 or the second control signal turns on the corresponding switch, and the low level of the mixing control signal Sx represents that the first control signal S1 or the second control signal turns off the corresponding switch. Fig. 7B is a voltage waveform diagram of the pull-up control signal S3 and the control node Nb. As can be seen from the simulation result, the voltage of the control node Nb is indeed controlled between the dc voltage source Vdh and the reference voltage source Vdl, and conforms to the Progressive analog scan (Progressive analog scan), so the control circuit 200 of the present disclosure can be applied to the display panel PA and normally operate.

Fig. 8A to 8C are schematic views of a display panel according to some embodiments of the disclosure. As shown in fig. 8A, in one embodiment, the display circuit 810 includes a plurality of pixel circuits 810. The pixel circuits 810 are located on the same row of the display panel 810 and are electrically connected to the same control circuit 820.

Referring to fig. 8B, in some embodiments, the display panel 820 includes a plurality of pixel circuits 821 and a plurality of control circuits 822. Each control circuit 822 corresponds to one pixel circuit 821. In other words, each control circuit 822 is electrically connected to the control node Nb (shown in fig. 2 and 4) of the corresponding pixel circuit 821 for controlling the on/off of the control switch Tc. In some other embodiments, each control circuit 822 is electrically connected to all the pixel circuits 821 in the same area on the display panel PA. In other words, the element "821" in fig. 8B may refer to "a plurality of pixel circuits 821 in the same region", and each of the control circuits 822 is electrically connected to all the pixel circuits in different regions.

Referring to fig. 8C, in some embodiments, the display panel 830 includes a plurality of pixel circuits, such as a plurality of first pixel circuits 831 and a plurality of second pixel circuits 832. The display panel 830 further includes a plurality of control circuits, such as a first control circuit 833 and a second control circuit 834 as shown. The first pixel circuit 831 and the second pixel circuit 832 are located on the same row of the display panel 830. The first control circuit 833 is electrically connected to the first pixel circuits 831 (e.g., 4), and the second control circuit 834 is electrically connected to the second pixel circuits 832.

Various elements, method steps or technical features of the foregoing embodiments may be combined with each other without limiting the order of description or presentation in the drawings.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A pixel circuit driving method includes:

conducting a control node of a pixel circuit to a first voltage source through a first conversion circuit in a first frame period, wherein the voltage of the first voltage source is reduced along with time;

driving a light emitting element according to a supply power and a first data signal through the pixel circuit until a driving switch in the pixel circuit is turned off according to the voltage of the first voltage source;

in a second frame period, the control node is changed to be conducted to a second voltage source through a second conversion circuit, wherein the voltage of the second voltage source is reduced along with time; and

the light emitting element is driven by the pixel circuit according to the power supply and a second data signal until the driving switch in the pixel circuit is turned off according to the voltage of the second voltage source.

2. The method of claim 1, wherein turning on the control node of the pixel circuit to the first voltage source further comprises:

turning on a first transfer switch in the first transfer circuit, wherein the first transfer switch is connected to the first voltage source through a first transfer capacitor.

3. The pixel circuit driving method according to claim 2, further comprising:

before the control node of the pixel circuit is conducted to the first voltage source, the voltage of the control node is set to a first high potential.

4. The pixel circuit driving method according to claim 3, further comprising:

the voltage of the control node is set to a first low potential to turn off the driving switch in the pixel circuit.

5. The method according to claim 1, wherein the first voltage source and the second voltage source have the same voltage waveform but a delay time therebetween.

6. A control circuit, comprising:

a first conversion circuit, including a first conversion switch, and electrically connected to a control node of a control switch in a pixel circuit, wherein the control node is electrically connected to a first voltage source through the first conversion switch, and the voltage of the first voltage source is decreased with time; and

a second converting circuit, including a second converting switch, electrically connected to the control node of the control switch, wherein the control node is electrically connected to a second voltage source through the second converting switch, and the voltage of the second voltage source is decreased with time;

the first transfer switch is turned on and the second transfer switch is turned off during a first frame period to turn on the control node to the first voltage source, and the pixel circuit drives a light emitting element according to a supply power and a first data signal;

the first transfer switch is turned off and the second transfer switch is turned on during a second frame period to turn on the control node to the second voltage source, and the pixel circuit drives the light emitting element according to the power supply and a second data signal.

7. The control circuit according to claim 6, wherein the pixel circuit drives the light emitting element according to the first data signal or the second data signal when the voltage at the control node is greater than a threshold value; when the voltage of the control node is smaller than the threshold value, the pixel circuit stops driving the light-emitting element.

8. The control circuit of claim 6, wherein the first conversion circuit further comprises:

a first converting capacitor, a first end of which is electrically connected to the first voltage source, and a second end of which is electrically connected to the control node through the first converting switch.

9. The control circuit of claim 8, wherein the second conversion circuit further comprises:

and a second conversion capacitor, wherein a first end of the second conversion capacitor is electrically connected to the second voltage source, and a second end of the second conversion capacitor is electrically connected to the control node through the second conversion switch.

10. The control circuit of claim 9, further comprising:

and a voltage setting circuit electrically connected among the first transfer switch, the second transfer switch and the control node, wherein the voltage setting circuit is used for setting the voltage of the control node to a first high potential before the pixel circuit drives the light-emitting element so as to conduct a driving switch in the pixel circuit.

11. The control circuit of claim 10, wherein the voltage setting circuit is further configured to set the voltage of the control node to a first low voltage level to turn off a driving switch in the pixel circuit.

12. The control circuit of claim 11, wherein the voltage setting circuit comprises a pull-up voltage switch and a pull-down voltage switch, the pull-up voltage switch being turned on to set the voltage of the control node to the first high potential, the pull-down voltage switch being turned on to set the voltage of the control node to the first low potential.

13. A display panel, comprising:

at least one pixel circuit for driving a light emitting device and including a control switch; and

at least one control circuit, comprising:

a first converting circuit, including a first converting capacitor and a first converting switch, wherein a first end of the first converting capacitor is electrically connected to a first voltage source, a second end of the first converting capacitor is electrically connected to a control node of the control switch through the first converting switch, and a voltage of the first voltage source is decreased with time; and

and the second conversion circuit comprises a second conversion capacitor and a second conversion switch, wherein the first end of the second conversion capacitor is electrically connected to a second voltage source, the second end of the second conversion capacitor is electrically connected to the control node through the second conversion switch, and the voltage of the second voltage source is reduced along with time.

14. The display panel of claim 13, wherein the first switch is turned on and the second switch is turned off to turn on the control node to the first voltage source during a first frame period, and the pixel circuit drives the light emitting device according to a power supply and a first data signal; during a second frame period, the first transfer switch is turned off, the second transfer switch is turned on to conduct the control node to the second voltage source, and the pixel circuit drives the light emitting element according to the power supply and a second data signal.

15. The display panel of claim 14, wherein the pixel circuit drives the light emitting element according to the first data signal or the second data signal when the voltage of the control node is greater than a threshold; when the voltage of the control node is smaller than the threshold value, the pixel circuit stops driving the light-emitting element.

16. The display panel of claim 13, wherein the control circuit further comprises:

and a voltage setting circuit electrically connected among the first transfer switch, the second transfer switch and the control node, and including a pull-up voltage switch and a pull-down voltage switch, wherein when the pull-up voltage switch is turned on, the voltage setting circuit is used for setting the voltage of the control node to a first high potential.

17. The display panel of claim 16, wherein the voltage setting circuit is further configured to set the voltage of the control node to a first low potential when the pull-down voltage switch is turned on.

18. The display panel of claim 13, wherein the display panel comprises a plurality of the pixel circuits, the pixel circuits are located in a same row on the display panel, and the pixel circuits are all electrically connected to the control circuit.

19. The display panel of claim 13, wherein the display panel comprises a plurality of the pixel circuits, the pixel circuits being located in a same area of the display panel and electrically connected to the control circuit.

20. The display panel of claim 13, the pixel circuits comprising a plurality of first pixel circuits and a plurality of second pixel circuits, the control circuit comprising a first control circuit and a second control circuit; the first pixel circuit and the second pixel circuit are located in the same horizontal row on the display panel, the first control circuit is electrically connected to the first pixel circuit, and the second control circuit is electrically connected to the second pixel circuit.