CN114217561B - Control circuit device for DP interface and adaptive equalization method thereof - Google Patents
Control circuit device for DP interface and adaptive equalization method thereof Download PDFInfo
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Abstract
The invention discloses a control circuit device for a DP interface and a self-adaptive equalization method thereof, which can improve the application flexibility and reduce the error rate of a received signal. The control circuit device comprises a CTLE circuit and a CDR circuit, wherein the output of the CTLE circuit is connected with the input of the CDR circuit, the CTLE circuit comprises a two-stage cascade connection, the control end of the CTLE circuit is connected with a control unit FSM_CTLE and two paths of DAC circuits, the control unit FSM_CTLE is used for outputting a resistance value control word, and the two paths of DAC circuits are used for outputting a capacitance value control word; the DFE circuit adopts a half data rate preprocessing structure, the input of the DFE circuit is respectively connected with the output of the CTLE circuit, a clock control signal and a threshold voltage control signal, and the half data rate preprocessing structure comprises a comparator: the self-adaptive equalization method comprises the following steps of: a bias calibration stage; a CTLE circuit self-adaptive adjustment stage; a CDR circuit locking stage; the DFE circuit adapts to the conditioning phase.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a control circuit device for a DP interface and a self-adaptive equalization method for a receiving channel of the DP interface.
Background
The DP (DisplayPort) interface is a display communication port depending on the data transmission technology of data packetization, and can be used for internal display connection and external display connection. Currently, the mainstream equalization technology for DP interface receiving channels mainly has 3 main classes: (1) Only CTLE (Continuous Time Linear Equalization, continuous linear time equalization) circuits are included, and CTLE parameters are typically adjusted by detecting the steepness of the data transitions in an analog manner; (2) The system comprises two circuits, namely a CTLE circuit and a DFE circuit (Decision Feedback Equalization, decision feedback equalizer), but only the DFE circuit can carry out self-adaptive adjustment, and the control parameters of the CTLE circuit need to be manually configured; (3) The CTLE circuit and the DFE circuit are included, and the CTLE parameter needs to determine the adjustment direction by symbol statistics of the data jump edges or by counting the eye width of the output signal of the CTLE circuit, depending on the special training sequence for adaptive adjustment.
If only CTLE circuits are provided, only amplitudes of high and low frequency components can be balanced, ISI (Inter Symbol Interference ) caused by channel transmission cannot be eliminated, and the existence of ISI can cause decision errors of a data comparator (data comparator), so that the error rate is increased; although in many designs, a combined circuit structure of CTLE circuit and DFE circuit is used, since only the DFE circuit portion can be adjusted in an adaptive manner, the CTLE circuit still depends on an empirical value of external manual configuration, which is not completely adaptive equalization, and parameters required to be configured by the CTLE circuit may be greatly different for different applications, so that the CTLE circuit is not flexible in application.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a control circuit device for a DP interface and a self-adaptive equalization method thereof, which do not depend on a special training sequence, can improve the application flexibility, can realize equalization of high and low frequency components, can eliminate ISI and can reduce the error rate of a received signal.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the control circuit device for the DP interface comprises a CTLE circuit and a CDR circuit, wherein the output of the CTLE circuit is connected with the input of the CDR circuit; the DFE circuit adopts a half data rate preprocessing structure, the input of the DFE circuit is respectively connected with the output of the CTLE circuit, a clock control signal and a threshold voltage control signal, and the half data rate preprocessing structure comprises a comparator: interference comparator, data comparator, half data rate preprocessing refers to: dividing the DAC circuit into an odd circuit and an even circuit according to the phase of a sampling clock, dividing the odd circuit and the even circuit into four circuits according to different data division judgment thresholds, respectively and simultaneously working the four circuits of comparators, and selecting the corresponding comparators according to the value of the first 1bit to realize balanced regulation when the final output is performed.
It is further characterized in that,
each stage of the CTLE circuit is controlled through a resistance value output by the FSM_CTLE of the control unit and a capacitance value output by the two paths of DAC circuits, wherein a resistance value control word output by the FSM_CTLE of the control unit comprises a resistance cw_r1 and a resistance cw_r2, and capacitance value control words output by the two paths of DAC circuits are Vctrl_c1 and Vctrl_c2 respectively;
the even-numbered paths comprise a data even-numbered path and an interference even-numbered path, the DFE circuit comprises four paths of data comparators (data slicers) and two paths of interference comparators (error slicers), the four paths of data comparators comprise first to fourth data comparators, the data even-numbered path comprises a first data comparator and a second data comparator, the data odd-numbered path comprises a third data comparator and a fourth data comparator, the interference even-numbered path comprises a fifth interference comparator, and the interference odd-numbered path comprises a sixth interference comparator;
the DFE circuit further includes two data selectors: the input of the first data selector is connected with the output of the data even-numbered path, and the selection end and the output of the first data selector are respectively connected in a cross way through a first latch and a second latch;
the different threshold voltage signals include threshold voltages ve_h1m, ve_h1p, vo_h1m, vo_h1p, veeth, and Veoth, and the clock control signals include clock signals clk_0 °, and complementary clock signals clk_180 °;
the input ends of the first comparator, the second comparator and the fifth comparator are respectively connected with threshold voltages ve_h1m, ve_h1p, vo_h1m, vo_h1p, veeth and Veoth, the input ends of the first comparator, the second comparator and the fifth comparator are respectively connected with a clock signal CLK_0 DEG, and the input ends of the third comparator, the fourth comparator and the sixth comparator are respectively connected with a clock signal CLK_180 deg.
The adaptive equalization method is realized on the basis of the control circuit device and is used for carrying out adaptive equalization adjustment on the DP interface receiving channel, and is characterized by comprising the following steps of: s1, a bias calibration stage;
s2, a CTLE circuit self-adaptive adjustment stage;
s3, locking a CDR circuit;
s4, a self-adaptive adjustment stage of the DFE circuit;
the self-adaptive adjustment stage of the CTLE circuit is to actively control the CDR circuit to enable the clock to be in an unlocked state, and after the self-adaptive adjustment of the CTLE circuit is completed, the self-adaptive adjustment of the DFE circuit is carried out after the CDR circuit is locked.
It is further characterized in that,
further, the offset calibration stage calibrates an offset introduced by the comparator, the offset calibration comprising: s11, the CTIE circuit inputs a differential signal pair vin_p and vin_n to the DFE circuit, and a differential voltage signal vin=vin_p-vin_n, shorts the vin_p and the vin_n and clamps the vin_p and the vin_n to a fixed voltage value through a clamping circuit; s12, calibrating the four paths of data paths in sequence;
further, the step of finding the corresponding comparator offset value includes: a1, regulating the threshold voltage of a corresponding comparator to gradually increase the threshold voltage from a preset minimum value, namely, the input end control code of the DAC circuit is increased from 7' h 00; in the threshold voltage adjusting process, counting the output data of the comparator in the corresponding time period T of each threshold voltage; a3, in the process of regulating the threshold voltage of the corresponding comparator, when the output data of the comparator contains 0, the corresponding threshold voltage value is the offset value of the path where the comparator is positioned;
further, based on the step of searching the offset value of the corresponding comparator, performing a plurality of rounds of calibration, wherein the final offset value of the corresponding comparator is the average value of the plurality of rounds of calibration offset values;
further, a method of calibrating bias values by using four comparators in a time-sharing sequence is adopted, and when one of the comparators in the even-numbered paths is calibrated, the threshold voltages of the two comparators in the odd-numbered paths are controlled to be the maximum value or the minimum value at the same time, and when one of the comparators in the odd-numbered paths is calibrated, the threshold voltages of the two comparators in the even-numbered paths are controlled to be the maximum value or the minimum value at the same time;
further, when the CTLE circuit is adaptively adjusted, the characteristics of under-balance and over-balance are searched from the time domain waveform, when the amplitude of the low-frequency component is obviously larger than that of the high-frequency component, the signal state is judged to be under-balanced, and when the amplitude of the low-frequency component is consistent with that of the high-frequency component, but the data jump edge has an overshoot signal, the signal state is judged to be over-balanced;
further, after the self-adaptive adjustment of the CTLE circuit is started, the threshold voltage of the interference comparator is controlled by adjusting the amplitude of the expected value, the expected value of the maximum swing of the external configuration signal is set in an initial state, and the control word of the capacitance value takes the minimum value, so that the output signal of the CTLE circuit is in an unbalanced state;
further, the specific step of judging the signal state as being over-balanced includes: the first step, adjust the control word of the resistance value, realize the direct current gain control, include specifically: adjusting the amplitude of a low-frequency component in the CTLE circuit output signal, and when the output data of the interference comparator contains 1, indicating that the amplitude of the low-frequency component reaches an expected value;
step two, gradually increasing a capacitance value control word to improve the high-frequency gain, comprising the following steps: and adjusting the amplitude of the high-frequency component in the CTLE circuit output signal, and when the number of '1's in the output data of the interference comparator is more than the number of '1's in the first step, indicating that the signal state is over-balanced at the moment.
Further, during self-adaptive adjustment of the DFE circuit, a corresponding threshold voltage is selected according to code patterns, a state machine of a control unit of the DFE circuit corresponds to four code patterns, statistics is carried out on the four code patterns in a time-sharing manner, an analog voltage expected value corresponding to a current bit is obtained through calculation, analog voltage expected values dlev00, dlev01 and dlev11 corresponding to four groups of current bits are obtained corresponding to four code patterns 00, 01, 10 and 11, and the four groups of expected values correspond to threshold voltages of a time-sharing output control interference comparator in four states of the state machine;
further, the capacitance values of the two-stage cascade connection in the CTLE circuit are controlled by voltages, the control voltages are from two paths of the DAC circuits, the threshold voltages of all comparators in the DFE circuit are from the respective corresponding DAC circuits, the control words of the DAC circuits are all from the digital control unit, and the control words required to be input by the DAC circuits are gray codes.
The structure and the method can achieve the following beneficial effects: the control circuit device for the DP interface comprises a CTLE circuit and a CDR circuit, wherein the control end of the CTLE circuit is connected with a control unit FSM_CTLE and two paths of DAC circuits, each stage of the CTLE circuit is controlled by a resistance value control word output by the control unit FSM_CTLE and a capacitance value control word output by the two paths of DAC circuits, the control is independent of an external manual configuration experience value and a special training sequence, and the application flexibility is improved.
And the self-adaptive equalization adjustment is carried out on the receiving channel of the DP interface based on the half data rate preprocessing structure of the CTLE circuit and the DFE circuit, and in the adjustment process, the adjustment of the resistance value and the capacitance value of the CTLE circuit is realized through the estimation of the time domain waveform amplitude, so that the equalization of high-frequency components and low-frequency components is realized, the DFE circuit is of the half-rate preprocessing structure, the ISI is eliminated, and finally, the error rate of a received signal is smaller than 10-12.
Drawings
Fig. 1 is a circuit block diagram of a control circuit device for a DP interface according to the present invention;
FIG. 2 is a flow chart of the adaptive equalization method of the present invention;
FIG. 3 is a flowchart of a bias calibration algorithm for the bias calibration stage in the adaptive equalization method of the present invention;
fig. 4 is a time domain waveform of the received signal in the adaptive equalization method of the present invention after being undersalanced before passing through the CTLE circuit;
fig. 5 is a state control diagram of CTLE circuit in adaptive equalization method of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
The conventional CTLE circuit and the DFE circuit can realize self-adaptive adjustment, the parameter adjustment direction of the CTLE circuit is carried out by statistically judging the symbol or the eye width of the jump edge of the CTLE circuit output signal, when the symbol of the jump edge is used as the basis for statistical judgment, the phase jitter of the jump edge data sampling clock and the influence of the offset (offset) in the circuit on the jump edge amplitude can cause error of the symbol judgment of the jump edge, when the signal eye width of the CTLE circuit output signal is counted, an adaptive path is needed, the decision device clock of the path needs to obtain different phases relative to the reference path through adjusting delay control codes, and the maximum eye width is found by comparing the error rates of the adaptive path data and the reference path data when the different delay codes, but the control codes are very difficult to control the high-frequency sampling clock to obtain different phases.
The present application provides a control circuit device for a DP interface receiving channel, and provides a specific method for implementing adaptive equalization of the DP interface receiving channel by using the control circuit device, hereinafter, a block diagram of a CTLE circuit and DFE circuit combined structure and digital algorithm control logic of the control circuit device for the DP interface receiving channel is shown in fig. 1, the CTLE circuit comprises 2 stages of cascade connection, can cover equalization in a Nyquist frequency (Nyquist frequency) range of 0.81G-4.05G, each stage is divided into resistance value control and capacitance value control, the resistance value is used for adjusting direct current gain, the capacitance value is used for adjusting peak (peak) gain compensation, cw_r1 and cw_r2 are resistance value control words, and are directly from CTLE circuit algorithm control units fsm_ctle (see fig. 1), vctrl_c1 and vctrl_c2 are respectively from two DAC circuits, and the control codes of the DAC circuits are from cw2 dac2 dac2_c1 and cw_c2_c2 of the fsm_ctle. The CDR circuit generates complementary clock signals CLK_0 DEG and CLK_180 DEG, the DFE circuit adopts a half data rate preprocessing structure, the frequency is half of the DP interface serial data rate, the phase difference is 180 DEG, the comparator (comparator) of the data (data) path and the comparator (comparator) of the interference (error) path are firstly divided into an odd-numbered path (even) and an even-numbered path (odd) according to the phase of the sampling clock, wherein the data odd-numbered path (data even) and the data even-numbered path (data odd) respectively select different comparator (comparator) decision thresholds (namely threshold voltages) due to the difference of the previous 1bit, and therefore the data odd-numbered path-H1 (data even-H1), the data odd-numbered path +H2 1 (data even+H2 1), the data even-numbered path-H1 (data odd-H1) and the data odd-H1 (data odd+H2 1) are respectively divided into four paths, and the data odd-H1 are respectively selected simultaneously when the data odd-H1 and the data odd-H1 are respectively output according to the method of the previous 1bit path (data odd-H1 and the data odd-H1). The parameters to be regulated by the DFE circuit are ve_h1m, ve_h1p, vo_h1m, vo_h1p, veeth and Veoth, which are respectively decision threshold voltages of a four-way data comparator (data slot) and a two-way interference comparator (error slot), ve_h1m is a decision threshold voltage when 1bit is-1 before a data even number, ve_h1p is a decision threshold voltage when 1bit is +1 before a data even number, vo_h1m is a decision threshold voltage when 1bit is-1 before a data odd number, vo_h1p is a decision threshold voltage when 1bit is +1 before a data odd number, veeth is an error even number, and Veoth is an error odd number decision threshold voltage, and in the DFE self-adaption process, the threshold voltage control word of the 6-way comparator (slot) is from the output of the DFE circuit algorithm control unit M_DFE.
The following is a specific embodiment of a method for implementing adaptive equalization of a DP interface receiving channel by using the control circuit device, and the adaptive equalization algorithm of the present application is generally divided into four stages: 1) A bias calibration (offset calibration) phase, which is performed after the basic control register configuration is completed after the chip is powered up; 2) In the CTLE circuit adaptation (CTLE adaptation) stage, serial data on the DP interface is required to be a single-frequency signal in order to ensure that the process is performed efficiently; 3) Waiting for the clock phase locking stage, after finishing CTLE adaptation, monitoring the locking signal (i.e. lock indication signal) of the CDR circuit to become 1; 4) In the self-adaption (DFE adaptation) stage of the DFE circuit, the four code patterns 00, 01, 10 and 11 of the state machine are counted in a time-sharing mode, d-1 is the first 1bit data, d0 is the current bit number, and coefficients +H21 and-H1 of the 1 st post cursor interference (i.e. the interference behind the sampling point) are obtained through calculation. The overall state machine control flow for the four phases described above is shown in fig. 2.
In the stage of offset calibration (offset calibration), since six slers in the DFE circuit have larger voltage offset (DC offset), in order to improve circuit performance, offset calibration (offset calibration) is required to be performed on the comparator (sler) circuit, and specific steps of offset calibration include: when the state state=s_offset_cal of the total state machine in fig. 2 indicates that the state of the current top-level adaptive process enters an offset calibration stage, calibration of error slicers and data slicers is performed simultaneously, a signal sent to the DFE circuit by the CTLE circuit in the actual circuit is a pair of differential pairs vin_p and vin_n (vin=vin_p-vin_n in fig. 1), the stage shorts vin_p and vin_n and clamps the differential values of the inputs of slicers to a fixed voltage through a clamping circuit, and ideally, the differential values of the inputs of each slicers should be vin=0 at this time, but in practical situations, the differential values of the inputs of each slicers are not 0 due to mismatch of two differential lines of each slicers, but an offset value exists, and the purpose of the calibration is to calculate the magnitude of the offset value. In this stage, the threshold voltages Veeth and Veoth in fig. 1 are controlled by the OFFSET value of the even-number-path error slot output by the fsm_offset_cal algorithm control module [6:0] and the OFFSET value of the odd-number-path error slot [6:0] respectively, the initial values of the offset_ee and the offset_eo are 7' h00, and at this moment, the two paths of control signals output a smaller voltage value as the threshold of the error slot after passing through the DAC circuit, so that the digital signal is found to be always 1 after counting the output of the error slot for a period of time, the offset_ee and the offset_eo are gradually increased, and when counting the output of the error slot for a period of time until 0 appears, the OFFSET value is considered to have been found. Because the data path adopts a preprocessing structure, the final output data of the decision device is always determined by the first 1bit, so that the offset calibration of the four paths of data slicers adopts a sequential execution mode, and the specific execution steps comprise: firstly, controlling an input end of a DAC circuit to control a code ofst_do_h1m=0, wherein the output of an odd-numbered path selector is always 1, an even-numbered path always selects a decision device with a threshold of ve_h1m to output, at the moment, counting the sampling data of data even, and gradually carrying out according to the calibration process of error slicers, and finally finding out an offset value of a data even-H1 path; secondly, controlling an input end of a DAC circuit to control codes ofst_do_h1m=127, wherein the output of an odd-numbered path selector is always 0, an even-numbered path always selects a decision device with a threshold of ve_h1p to output, at the moment, counting the sampling data of data even, and gradually carrying out according to the calibration process of error slicers, and finally finding out an offset value of a data even+H2 path; thirdly, controlling the output of an even-number path selector to be always 1 when the output of the odd-number path selector is controlled to be 0 when the ofst_de_h1m=0, and always selecting a decision device with the threshold of vo_h1m for output when the odd-number path selector is used for counting the sampling data of the data odd, and gradually carrying out according to the calibration process of an error slicer to finally find the offset value of the data odd-H1 path; fourth, the input end of the DAC circuit is controlled to control the code ofst_de_h1m=127, the output of the even-number path selector is always 0, the odd-number path selector always selects the decision device with the threshold of vo_h1p to output, sampling data of the data odd are counted, the sampling data are gradually processed according to the calibration process of error slicers, and finally the offset value of the data odd+H2 path is found. After the six paths of offset calibration are completed, a round of calibration completion is marked, and due to the existence of interference, possible calibration results are inaccurate, so that multiple rounds of calibration are needed, and then the final calibration result is obtained by taking an average value of the calibration results. Calibration flow control for this step is shown in fig. 3, where "idle" in fig. 3 indicates initialization, "wait-cycle" indicates waiting for CDR lock statistics, "round_over=1? The method comprises the steps of judging whether output data of a comparator contains 1 or not, counting the number of 0 s in data output by a corresponding slotter in a period of time in a state of 'wait_cycle' when the offset calibration stage is entered, judging whether the counted number is larger than a set threshold or not, entering the state of 'para_adj', increasing a control word of a slotter threshold voltage, waiting for a new result of statistics of the state of 'wait_cycle' again after entering the DAC set.
And writing the bias value estimated in the bias calibration stage into a state register (the state register comprises a first latch and a second latch) for storage, and subtracting the corresponding bias value from a comparator threshold voltage control word in a subsequent CTLE circuit and DFE circuit self-adaptation stage.
In the adaptive adjustment stage of the CTLE circuit, the state value state=s_ctl_cal of the overall state machine in fig. 2 starts to perform adaptive adjustment of the CTLE circuit, from the time domain waveform in fig. 4, the waveform in which the high level "1" is high level "or the low level" 0 "is low level" is long, the steep degree of the jump edge shows the amplitude of the low frequency component, the waveform in which the single bits 0 and 1 alternately appear (i.e. when the high and low levels appear in the unit time interval) shows the amplitude of the high frequency component, fig. 4 is the time domain waveform in which the received signal is underequalized before passing through CTLE and overcompensated after passing through CTLE, the horizontal axis in fig. 4 shows the data sequence number index, the vertical axis shows the voltage value, the curve a shows the amplitude transformation curve before CTLE circuit adaptive equalization, and the curve B shows the amplitude transformation curve after CTLE circuit adaptive equalization. As can be seen from the waveforms in fig. 4, before equalization, when the signal is in a state of under equalization, the amplitude of the high-frequency component is smaller, the amplitude of the low-frequency component is larger, and the change of the jump edge is slower; after being equalized by the CTLE circuit, the amplitudes of the high-frequency components and the low-frequency components are not greatly different, and the jump edges become very steep, but an overshoot phenomenon (the position marked by a circle in fig. 4) exists, so that the signal is in an over-equalization state at the moment. The application provides a specific algorithm of over-equalization and under-equalization: the method comprises the steps of firstly, adjusting a resistance value and a capacitance value of a CTLE circuit, enabling a resistance value R to be an intermediate value, obtaining an intermediate value of a direct current gain, enabling a capacitance value C to be a minimum value, obtaining minimum gain compensation, enabling a received signal attenuated through a channel to be still in an under-balanced state after passing through the CTLE circuit, setting expected values of signal swing amplitude at the moment, enabling the expected values to be respectively subtracted by threshold control words corresponding to two paths of slicers after the expected values are respectively subtracted by the expected values of offset values corresponding to error even/odd slicers, counting sampled data output by error slicers in an initial state for a period of time, if the data are all 0, indicating that the current low-frequency component swing amplitude does not reach a set value, increasing the resistance value (namely the R value) to improve the direct current gain until the R value is adjusted to a certain value, enabling the quantity of 1 in the data counted under the current R value and the quantity of 1 in the data counted under the previous R value to be distributed on two sides of a set quantity threshold of 1, indicating that the amplitude of a current low-frequency component has reached the expected value of the signal swing amplitude and recording the quantity of 1 in the current R value. And step two, gradually increasing the capacitance value (C value) to adjust the signal towards the direction of equalization, wherein the amplitude of a high-frequency component in the waveform of the signal is increased along with the increase of the capacitance value, counting the number of 1 in error slider output data when the C value is adjusted once, and considering that equalization is proper when the number of counted symbols 1 is distributed on two sides of the number N0 by two adjacent adjustments, wherein the current R value and the current C value are configuration values in optimal equalization. Fig. 5 is a state control diagram in CTLE adaptive adjustment process, wait_cycle in fig. 5 is a statistical state of results, r_adj is a dc gain adjustment state, only the resistance value control word is adjusted, c_adj is a peak gain adjustment state, only the capacitance value control word is adjusted, and r_adj_over=1? I.e. determine whether the capacitance control word contains "1", c_adj_over=1? I.e., determine if the resistance control word contains a "0".
In the DFE circuit adaptive adjustment stage, when the control signal state=s_dfe_cal output by the total state machine in fig. 2 enters the DFE adaptive stage, for a 1-tap DFE circuit (i.e. DFE circuit with half data rate preprocessing structure), we consider only the influence of the previous 1bit data on the current data, the influence of the 1 st order on the current data is h1, the impulse response value of the current data is h0, when the code pattern d-1 d0=00, the amplitude dlev00= -h1-h0 of the current data, when the code pattern d-1 d0=01, the amplitude dlev01= -h1+h0 of the current data, when the code pattern d-1 d0=10, the amplitude dlev10=h1-h 0 of the current data, when the code pattern d-1 d0=11, the amplitude dlev11=h1+h0 of the current data, so-h1= (dlev00+dlev01)/dlev1+d2+dl10+h11. In combination with the calibration values of the slots obtained by the offset calibration, in the DFE circuit adaptive adjustment stage, ch2dac_de_h1m= -h1+ofst_de_h1m, ch2dac_de_h1p= +h1+ofst_de_h1p, ch2dac_do_h1m= -h1+ofst_do_h1m, ch2dac_do_h1p= +h1+ofst_do_h1p, ch2dac_ee=dlev+ofst_ee, ch2dac_eo=dlev_ofst_eo, "" indicates "0" or "1". Since the state machine in the DFE circuit is used to control the time-sharing statistics of the pattern, the threshold control words of error slicers are calculated using dlev00, dlev01, dlev10, dlev11, respectively, for different pattern statistics periods. The implementation process of the DFE self-adaptive control algorithm mainly comprises two steps: in the first step, in the initial state, cw2dac_de_h1m=0, cw2dac_de_h1p=0, cw2dac_do_h1=0, and cw2dac_do_h1p=0, where data slicer can output correctly decided data with maximum probability, mainly calculating dlev by LMS iterative algorithm, dlev (n+1) =dlev (n) +u×sign (e) |d-1d 0=, u is a set step size (step size is 1-1/1024), e is data output by error slicer decision, meaning that when the code pattern is the analog voltage amplitude expected by the current symbol, the actual voltage input by the slicer is error symbol after comparing with the value, and the error symbol is converged to a certain iteration value by a certain time. And secondly, after iterative operation for a period of time is performed and dlev is stable, calculating-h 1 and +h1 according to a formula given from the beginning of the section, and further calculating and updating the obtained threshold voltage control word required by the 4-path data slicer.
In summary, the adaptive equalization method provided by the application has clear implementation flow, the analog circuit design and the digital algorithm control of the combined structure of the CTLE circuit and the DFE circuit are convenient to implement, the configurable performance is high, the calibration precision of bias calibration and the adaptive adjustment precision of the CTLE circuit and the DFE circuit depend on the precision of the DAC circuit to the greatest extent, the control algorithm of the FSM_CTLE control unit adopts the high-frequency and low-frequency component amplitude characteristics based on the time domain waveform as the judgment basis of the equalization effect, the DFE control algorithm adopts the LMS iterative algorithm based on the error symbol, and the equalization range covers the baud rate of 1.62G to 8.1G. The circuit structure and the self-adaptive equalization algorithm are used in mass production products, 3-40 inch video cables are supported, and after equalization is completed, the control of all circuit parameters can be flexibly realized, so that the requirement of the products on self-adaptive equalization in the actual use environment is met.
The above are only preferred embodiments of the present application, and the present invention is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present invention are deemed to be included within the scope of the present invention.
Claims (5)
1. The control circuit device for the DP interface comprises a CTLE circuit and a CDR circuit, wherein the output of the CTLE circuit is connected with the input of the CDR circuit; the DFE circuit adopts a half data rate preprocessing structure, the input of the DFE circuit is respectively connected with the output of the CTLE circuit, a clock control signal and a threshold voltage control signal, and the half data rate preprocessing structure comprises a comparator: interference comparator, data comparator, half data rate preprocessing refers to: dividing the DAC circuit into an odd circuit and an even circuit according to the phase of a sampling clock, dividing the odd circuit and the even circuit into four circuits according to different data division judgment thresholds, respectively and simultaneously working the four circuits of comparators, and selecting the corresponding comparators according to the value of the first 1bit to realize balanced regulation when the final output is performed.
2. The control circuit apparatus for a DP interface according to claim 1, wherein the odd-numbered path includes a data odd-numbered path including a data even-numbered path including a third data comparator and a fourth data comparator, and an interference odd-numbered path including a fifth interference comparator, and the DFE circuit includes four-numbered data comparators (data slicers) and two-numbered interference comparators (error slicers), six of which include first to fourth data comparators, and the data even-numbered path includes a first data comparator and a second data comparator, and the data odd-numbered path includes a third data comparator and a fourth data comparator, and the interference even-numbered path includes a fifth interference comparator, and the interference odd-numbered path includes a sixth interference comparator.
3. The control circuit apparatus for a DP interface according to claim 2, wherein the DFE circuit further includes two data selectors: the input of the first data selector is connected with the output of the data even-numbered circuit, and the selection end and the output end of the first data selector and the second data selector are respectively connected in a cross mode through a first latch and a second latch.
4. An adaptive equalization method implemented based on the control circuit device of claim 1 or 3, for adaptive equalization adjustment of a reception channel of a DP interface, the adaptive equalization method comprising: s1, a bias calibration stage;
s2, a CTLE circuit self-adaptive adjustment stage;
s3, locking a CDR circuit;
s4, a self-adaptive adjustment stage of the DFE circuit;
the self-adaptive adjustment stage of the CTLE circuit is to actively control the CDR circuit to enable the clock to be in an unlocked state, and after the self-adaptive adjustment of the CTLE circuit is completed, the self-adaptive adjustment of the DFE circuit is carried out after the CDR circuit is locked;
the offset calibration stage calibrates an offset introduced by the comparator, the offset calibration comprising: s11, the CTIE circuit inputs a differential signal pair vin_p and vin_n to the DFE circuit, and a differential voltage signal vin=vin_p-vin_n, shorts the vin_p and the vin_n and clamps the vin_p and the vin_n to a fixed voltage value; s12, calibrating four paths of data paths in sequence, and searching bias values of corresponding comparators, wherein the steps comprise: a1, regulating the threshold voltage of a corresponding comparator, so that the threshold voltage is gradually increased from a preset minimum value; in the threshold voltage adjusting process, counting the output data of the comparator in the corresponding time period T of each threshold voltage; a3, in the process of regulating the threshold voltage of the corresponding comparator, when the output data of the comparator contains 0, the corresponding threshold voltage value is the offset value of the path where the comparator is positioned;
based on the step of searching the offset value of the corresponding comparator, carrying out a plurality of rounds of calibration, wherein the final offset value of the path where the corresponding comparator is positioned is the average value of the calibration offset values of a plurality of rounds; when one comparator of even number paths is calibrated, the threshold voltages of two comparators in odd number paths are controlled to be the maximum value or the minimum value at the same time; when one of the comparators of the odd-numbered paths is calibrated, the threshold voltages of the two comparators of the even-numbered paths are controlled to be the maximum value or the minimum value at the same time;
when the CTLE circuit is adaptively adjusted, the characteristics of under-balance and over-balance are searched from the time domain waveform, when the amplitude of the low-frequency component is larger than that of the high-frequency component, the signal state is judged to be under-balance, and when the amplitude of the low-frequency component is consistent with that of the high-frequency component, but the data jump edge has an overshoot signal, the signal state is judged to be over-balance;
after the self-adaptive adjustment of the CTLE circuit is started, the threshold voltage of the interference comparator is controlled by adjusting the amplitude of the expected value, the amplitude of the expected value is configured to be the maximum in an initial state, and a capacitance value control word takes the minimum value, so that the CTLE output signal is in an under-balanced state;
the step of determining whether the signal state is over-balanced comprises: the first step, the resistance value control word is adjusted to realize direct current gain control: adjusting the amplitude of a low-frequency component in the CTLE circuit output signal, and when the output data of the interference comparator contains 1, indicating that the amplitude of the low-frequency component reaches an expected value; step two, gradually increasing the capacitance value control word to improve the high-frequency gain: adjusting the amplitude of high-frequency components in the output signal of the CTLE circuit, and when the number of 1's in the output data of the interference comparator is more than the number of 1's in the first step, indicating that the signal state is over-balanced at the moment;
when the DFE circuit is adaptively adjusted, corresponding threshold voltages are selected according to code patterns, the state machine of the control unit of the DFE circuit corresponds to four code patterns, wherein the four code patterns comprise 00, 01, 10 and 11, and the corresponding threshold voltages are selected according to the code patterns: the four code patterns are counted in a time-sharing mode, the analog voltage expected value corresponding to the current bit is obtained through calculation, the analog voltage expected values corresponding to the current bit of the four code patterns 00, 01, 10 and 11 are dlev00, dlev01 and dlev11 respectively, and the four groups of expected values correspond to the threshold voltages of the time-sharing output control interference comparator in four states of the state machine.
5. The adaptive equalization method of claim 4, wherein the voltage of the DAC circuit is used to adjust a two-stage cascade of capacitance control words in the CTLE circuit, the threshold voltages of all comparators in the DFE circuit are from the respective corresponding DAC circuit, the control words of the DAC circuit are from a digital control unit, and the control words that the DAC circuit requires to input are gray codes.
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