CN114217561A - Control circuit device for DP interface and self-adaptive equalization method thereof - Google Patents
Control circuit device for DP interface and self-adaptive equalization method thereof Download PDFInfo
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Abstract
The invention discloses a control circuit device for a DP interface and a self-adaptive equalization method thereof, which can improve the application flexibility and reduce the error rate of received signals. The control circuit device comprises a CTLE circuit and a CDR circuit, the output of the CTLE circuit is connected with the input of the CDR circuit, the CTLE circuit comprises a secondary cascade, the control end of the CTLE circuit is connected with a control unit FSM _ CTLE and two DAC circuits, the control unit FSM _ CTLE is used for outputting resistance value control words, and the two DAC circuits are used for outputting capacitance value control words; the DFE circuit adopts half data rate preliminary treatment structure, and CTLE circuit output, clock control signal, threshold voltage control signal are connected respectively to DFE circuit input, and half data rate preliminary treatment structure includes the comparator: interference comparator, data comparator, the self-adaptation balanced method includes: an offset calibration stage; the CTLE circuit is in a self-adaptive adjusting stage; a CDR circuit locking stage; the DFE circuitry adapts the stage.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a control circuit device for a DP interface and a self-adaptive equalization method for a receiving channel of the DP interface.
Background
The dp (displayport) interface is a display communication port that relies on packetized data transmission technology, and can be used for internal display connections as well as for external display connections. Currently, there are 3 major categories of equalization techniques for DP interface receiving channels: (1) only contain the CTLE (Continuous Linear Equalization) circuit, and adjust the CTLE parameter by detecting the steepness of the data transition edge, usually in an analog manner; (2) the circuit comprises a CTLE circuit and a DFE circuit (Decision Feedback equalizer), but only the DFE circuit can carry out self-adaptive adjustment, and the control parameter of the CTLE circuit needs to be manually configured; (3) the CTLE parameter needs to decide the adjusting direction through symbol statistical judgment of a data jumping edge or through statistics of the eye width of an output signal of the CTLE circuit.
If only the CTLE circuit is used, the amplitude of high and low frequency components can be balanced, ISI (Inter Symbol Interference) caused by channel transmission cannot be eliminated, the existence of ISI may cause the judgment error of a data comparator (data slicer), thereby increasing the error rate, in addition, the method for adjusting the CTLE parameter by detecting the steepness of the data jumping edge in an analog mode is unreliable, and the configurability is poor during later use; although a combined circuit structure of the CTLE circuit and the DFE circuit is used in many designs, since only the DFE circuit portion can be adjusted in an adaptive manner, the CTLE circuit still depends on external manual configuration experience values, which is not adaptive equalization in a complete sense, and parameters to be configured by the CTLE circuit may be greatly different for different application occasions, so that the CTLE circuit is not flexible in application.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a control circuit device for a DP interface and a self-adaptive equalization method thereof, which do not depend on a special training sequence, can improve the application flexibility, can realize the equalization of high and low frequency components, can eliminate ISI and reduce the error rate of a received signal.
In order to achieve the purpose, the invention adopts the following technical scheme:
a control circuit device for a DP interface comprises a CTLE circuit and a CDR circuit, wherein the output of the CTLE circuit is connected with the input of the CDR circuit, the CTLE circuit comprises a two-stage cascade, the control end of the CTLE circuit is connected with a control unit FSM _ CTLE and two DAC circuits, the control unit FSM _ CTLE is used for outputting resistance value control words, and the two DAC circuits are used for outputting capacitance value control words; the DFE circuit adopts a half data rate preprocessing structure, the input of the DFE circuit is respectively connected with the output of the CTLE circuit, a clock control signal and a threshold voltage control signal, and the half data rate preprocessing structure comprises a comparator: interference comparator, data comparator, half data rate preliminary treatment indicates: and dividing the DAC circuit into an odd path and an even path according to the phase of a sampling clock, dividing the odd path and the even path into four paths according to different data division judgment thresholds, respectively working the four paths of comparators at the same time, and selecting a corresponding comparator to realize balance adjustment according to the value of the first 1bit during final output.
It is further characterized in that the method further comprises the steps of,
each stage of the CTLE circuit is controlled by a resistance value output by the control unit FSM _ CTLE and capacitance values output by the two DAC circuits, a resistance value control word output by the control unit FSM _ CTLE comprises a resistance cw _ r1 and a resistance cw _ r2, and capacitance value control words output by the two DAC circuits are Vctrl _ c1 and Vctrl _ c2 respectively;
the odd-numbered path comprises a data odd-numbered path and an interference odd-numbered path, the even-numbered path comprises a data even-numbered path and an interference even-numbered path, the DFE circuit comprises four paths of data comparators (data slicer) and two paths of interference comparators (error slicer), the four paths of data comparators comprise first to fourth data comparators, the data even-numbered path comprises a first data comparator and a second data comparator, the data odd-numbered path comprises a third data comparator and a fourth data comparator, the interference even-numbered path comprises a fifth interference comparator, and the interference odd-numbered path comprises a sixth interference comparator;
the DFE circuit further includes two data selectors: the input of the first data selector is connected with the output of the data even circuit, and the selection ends and the outputs of the first data selector and the second data selector are respectively connected in a cross mode through a first latch and a second latch;
the different threshold voltage signals include threshold voltages Ve _ h1m, Ve _ h1p, Vo _ h1m, Vo _ h1p, Veeth, and Veoth, the clock control signals include a clock signal CLK _0 °, a complementary clock signal CLK _180 °;
the input ends of the first comparator to the sixth comparator are respectively connected with threshold voltages Ve _ h1m, Ve _ h1p, Vo _ h1m, Vo _ h1p, Veeth and Veoth, the input ends of the first comparator, the second comparator and the fifth comparator are also respectively connected with a clock signal CLK _0 degree, and the input ends of the third comparator, the fourth comparator and the sixth comparator are also respectively connected with a clock signal CLK _180 degree.
An adaptive equalization method, implemented based on the control circuit device, for performing adaptive equalization adjustment on a DP interface receive channel, is characterized in that the adaptive equalization method includes: s1, an offset calibration stage;
s2, performing adaptive adjustment on the CTLE circuit;
s3, locking the CDR circuit;
s4, a DFE circuit self-adaptive adjusting phase;
and in the adaptive adjustment stage of the CTLE circuit, the CDR circuit is actively controlled to enable the clock to be in an unlocked state, and after the adaptive adjustment of the CTLE circuit is finished, the DFE circuit is subjected to the adaptive adjustment after the CDR circuit is locked.
It is further characterized in that the method further comprises the steps of,
further, the offset calibration stage calibrates an offset introduced by the comparator, and the offset calibration includes: s11, the CTIE circuit inputs differential signal pair Vin _ p and Vin _ n to the DFE circuit, the differential voltage signal Vin is Vin _ p-Vin _ n, Vin _ p and Vin _ n are shorted and clamped to a fixed voltage value by a clamping circuit; s12, sequentially calibrating the four data paths;
further, the step of finding the corresponding comparator offset value comprises: a1, adjusting the threshold voltage of the corresponding comparator to make the threshold voltage gradually rise from the preset minimum value, namely the control code of the input end of the DAC circuit is increased from 7' h 00; a2, counting the output data of the comparator in the time period T corresponding to each threshold voltage in the threshold voltage adjusting process; a3, in the process of adjusting the threshold voltage of the corresponding comparator, when the output data of the comparator contains 0, the corresponding threshold voltage value is the offset value of the path where the comparator is located;
further, based on the step of searching the offset value of the corresponding comparator, carrying out a plurality of rounds of calibration, wherein the final offset value of the corresponding comparator is the average value of the offset values of the plurality of rounds of calibration;
furthermore, a method for calibrating the offset value by four comparators in a time-sharing sequence is adopted, and when one comparator in an even path is calibrated, the threshold voltages of two comparators in an odd path are controlled to be the maximum value or the minimum value at the same time;
further, when the CTLE circuit is subjected to self-adaptive adjustment, the characteristics of under-equalization and over-equalization are searched from a time domain waveform, when the amplitude of a low-frequency component is obviously larger than that of a high-frequency component, the signal state is judged to be under-equalization, and when the amplitude of the low-frequency component is consistent with that of the high-frequency component but an overshoot signal exists at a data jumping edge, the signal state is judged to be over-equalization;
further, after the adaptive adjustment of the CTLE circuit is started, the threshold voltage of the interference comparator is controlled by adjusting the amplitude of the expected value, the expected value of the maximum swing amplitude of the external configuration signal in the initial state and the control word of the capacitance value take the minimum value, so that the output signal of the CTLE circuit is in an under-balanced state;
further, the specific step of judging the signal state as over-balanced includes: the first step, adjust resistance value control word, realize direct current gain control, specifically include: adjusting the amplitude of low-frequency components in the output signal of the CTLE circuit, and when the output data of the interference comparator contains '1', indicating that the amplitude of the low-frequency components reaches an expected value;
and step two, gradually increasing the capacitance control word to improve the high-frequency gain, which specifically comprises the following steps: and adjusting the amplitude of high-frequency components in the output signal of the CTLE circuit, and when the number of '1' in the output data of the interference comparator is more than that of '1' in the first step, indicating that the signal state at the moment is over-balanced.
Further, during adaptive adjustment of the DFE circuit, a corresponding threshold voltage is selected according to a code pattern, a state machine of a control unit of the DFE circuit corresponds to four code patterns, the four code patterns are counted in a time-sharing manner, an analog voltage expected value corresponding to a current bit is obtained through calculation, the four code patterns 00, 01, 10 and 11 correspondingly obtain four groups of analog voltage expected values dlev00, dlev01, dlev01 and dlev11 corresponding to the four groups of current bits, and the four groups of expected values correspond to the four states of the state machine and output threshold voltages of the interference comparator in a time-sharing manner;
furthermore, the capacitance value of two-stage cascade in the CTLE circuit is controlled by voltage, the control voltage is from two DAC circuits, the threshold voltage of all comparators in the DFE circuit is from the respective corresponding DAC circuit, the control word of the DAC circuit is from the digital control unit, and the DAC circuit requires the input control word to be gray code.
The structure and the method of the invention can achieve the following beneficial effects: the control circuit device for the DP interface comprises a CTLE circuit and a CDR circuit, wherein a control end of the CTLE circuit is connected with a control unit FSM _ CTLE and two DAC circuits, each stage of the CTLE circuit is controlled by resistance value control words output by the control unit FSM _ CTLE and capacitance value control words output by the two DAC circuits, the control does not depend on external manual configuration experience values or special training sequences, and the application flexibility is improved.
The receiving channel of the DP interface is subjected to self-adaptive equalization adjustment based on a half-data-rate preprocessing structure of a CTLE circuit and a DFE circuit, in the adjustment process, the resistance value and the capacitance value of the CTLE circuit are adjusted by estimating the amplitude of a time domain waveform, so that the equalization of high-frequency components and low-frequency components is realized, the DFE circuit is of the half-data-rate preprocessing structure, the ISI is favorably eliminated, and finally the error rate of a received signal is smaller than 10-12.
Drawings
FIG. 1 is a block diagram of a control circuit device for a DP interface according to the present invention;
FIG. 2 is a flow chart of the adaptive equalization method of the present invention;
FIG. 3 is a flowchart of an offset calibration algorithm in the offset calibration phase of the adaptive equalization method of the present invention;
FIG. 4 is a time domain waveform of a received signal being under-equalized before passing through a CTLE circuit and over-equalized after passing through the CTLE circuit in the adaptive equalization method of the present invention;
fig. 5 is a state control diagram of the CTLE circuit in the adaptive adjustment process in the adaptive equalization method of the present invention.
Detailed Description
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The conventional CTLE circuit and DFE circuit can be adaptive adjusted, the parameter adjusting direction of the CTLE circuit is carried out by statistically judging the sign or eye width of the jump edge of the output signal of the CTLE circuit, when the sign of the jumping edge is used as the statistical judgment basis, the sign judgment error of the jumping edge can be caused by the influence of the phase jitter of the data sampling clock of the jumping edge and the offset (offset) in the circuit on the amplitude of the jumping edge, when the eye width of the output signal of the CTLE circuit is counted, an adaptive path is needed, the arbiter clock of this path needs to be able to get a different phase with respect to the reference path by adjusting the delay control code, the maximum eye width is found by comparing the error rates of the adaptive path data and the reference path data at different delay codes, but it is very difficult to control the high frequency sampling clock by the control code to obtain different phases.
The application provides a control circuit device for a DP interface receiving channel, and provides a specific method for realizing the self-adaptive equalization of the DP interface receiving channel by using the control circuit device, the following is a specific embodiment of a control circuit device of a DP interface receiving channel, and a block diagram of a combined structure of a CTLE circuit and a DFE circuit and a digital algorithm control logic is shown in fig. 1, where the CTLE circuit includes 2 stages of cascade connection, and is capable of covering equalization in a Nyquist frequency (Nyquist frequency) range of 0.81G to 4.05G, each stage is divided into a resistance value control for adjusting a direct current gain and a capacitance value control for adjusting a peak (peak) gain compensation, cw _ r1 and cw _ r2 are resistance value control words directly from a CTLE circuit algorithm control unit FSM _ CTLE (see fig. 1), Vctrl _ c1 and Vctrl _ c2 are from two-way circuits, respectively, and control codes of the DAC circuit are from cw2DAC _ c1 and cw2DAC _ c2 of the FSM _ CTLE. The CDR circuit generates complementary clock signals CLK _0 DEG and CLK _180 DEG, the DFE circuit adopts a half data rate preprocessing structure, the frequency is half of the serial data rate of the DP interface, the phase difference is 180 DEG, a comparator (slicer) of a data (data) path and a comparator (slicer) of an interference (error) path are firstly divided into an odd number path (even) and an even number path (odd) according to the phase of a sampling clock, wherein the odd number path (data even) and the even number path (data odd) respectively select different decision thresholds (threshold voltages) of the comparator (slicer) due to the difference of a first 1bit so as to be divided into a data odd number path-H1 (data even-H1), a data odd number path + H1(data even + H1), a data even number path-H1 (odd-H1) and a data even number path + H5631 odd number path (data odd + H1), and a data even number path (data H35 1 and H35 1), the data odd-H1 and the data odd + H1 work simultaneously, respectively, and only when the data even or data odd is finally output, the path-H1 (path-H1) or the path + H1(path + H1) is selected according to the value of the first 1bit, and the method is called preprocessing. Parameters to be adjusted by the DFE circuit are Ve _ h1m, Ve _ h1p, Vo _ h1m, Vo _ h1p, Veeth and Veoth, which are respectively decision thresholds of a four-way data comparator (data slicer) and a two-way interference comparator (error slicer), Ve _ h1m is a decision threshold voltage when a first 1bit of a data even circuit is-1, Ve _ h1p is a decision threshold voltage when a first 1bit of a data even circuit is +1, Vo _ h1m is a decision threshold voltage when a first 1bit of a data odd circuit is-1, Ve is a decision threshold voltage when a first 1bit of the data odd circuit is +1, Veeth is an error even circuit decision threshold voltage, Veoth is an error odd circuit decision threshold voltage, and Vo _ h1p is a 6-way comparator (slicer voltage output by a control word control algorithm circuit.
The following is a specific embodiment of a method for implementing adaptive equalization of a DP interface receiving channel using the above control circuit device, and the adaptive equalization algorithm of the present application is generally divided into four stages: 1) an offset calibration (offset calibration) stage, which is carried out after the basic control register configuration is completed after the chip is powered on; 2) a CTLE adaptation (CTLE adaptation) stage, which requires that serial data on a DP interface cannot be a single-frequency signal in order to ensure the effective process; 3) waiting for a clock phase locking stage, and after CTLE adaptation is completed, monitoring that a locking signal (namely a lock indication signal) of a CDR circuit is changed into 1; 4) in the self-adaption (DFE adaptation) stage of the DFE circuit, the code patterns of four code patterns 00, 01, 10 and 11 of the state machine are counted in a time-sharing mode, d-1 is the first 1bit data, d0 is the current bit number, and coefficients + H1 and-H1 of 1-order post cursor interference (namely interference behind a sampling point) are calculated. The overall state machine control flow of the above four stages is shown in fig. 2.
In an offset calibration (offset calibration) stage, since there is a large voltage offset (DC offset) in six slicers in the DFE circuit, in order to improve circuit performance, offset calibration (offset calibration) needs to be performed on a comparator (slicer) circuit, and the offset calibration specifically includes the steps of: when the state of the general state machine in fig. 2 is s _ offset _ cal, it indicates that the state of the current top layer adaptive process enters an offset calibration phase, and the calibration of error slice and data slice is performed simultaneously, where the signal sent by the CTLE circuit to the DFE circuit in the actual circuit is a pair of differential pairs Vin _ p and Vin _ n (Vin is Vin _ p-Vin _ n in fig. 1), this phase shorts Vin _ p and Vin _ n and clamps them to a fixed voltage through a clamp circuit, ideally, the differential value of each slice input should be Vin ═ 0, but in the actual case, due to the mismatch of two differential lines of each slice, the differential value of the slice input is not 0, but there is an offset value, and the purpose of this step calibration is to calculate the magnitude of this offset value. At this stage, threshold voltages Veeth and Veoth in fig. 1 are respectively controlled by OFFSET value of even-numbered error slicer, i.e., OFFSET _ ee [6:0], and OFFSET value of odd-numbered error slicer, i.e., OFFSET _ eo [6:0], output by FSM _ OFFSET _ CAL algorithm control module, and initial values of OFFSET _ ee and OFFSET _ eo are 7' h00, at this time, the two control signals output a smaller voltage value as the threshold of error slicer after passing through DAC circuit, so that after counting the output of error slicer for a while, the digital signal is always 1, and then, the OFFSET _ ee and OFFSET _ eo are gradually increased, and when counting that the output of error slicer appears 0 within a while, the OFFSET value is considered to have been found. Because the data path adopts a preprocessing structure, and the final output data of the decision device is always determined by the first 1bit, the offset calibration of the four-way data slicer adopts a sequential execution mode, and the specific execution steps comprise: firstly, controlling an input end control code ofst _ do _ H1m of the DAC circuit to be 0, controlling an input end control code ofst _ do _ H1p to be 0, wherein the output of an odd-numbered path selector is always 1, and an even-numbered path always selects the output of a decision device with a threshold of Ve _ H1m, counting data even sampling data, gradually performing the data even sampling according to an error slicer calibration process, and finally finding out an offset value of a data even-H1 path; secondly, controlling an input end control code ofst _ do _ H1m of the DAC circuit to be 127, controlling an input end control code ofst _ do _ H1p to be 127, wherein the output of an odd-numbered path selector is always 0, and an even-numbered path always selects the output of a decision device with a threshold of Ve _ H1p, counting the sampling data of data even, and gradually performing the sampling according to the calibration process of error slicer, and finally finding out the offset value of a data even + H1 path; thirdly, controlling the offset _ de _ H1m to be 0, the offset _ de _ H1p to be 0, wherein the output of the even-numbered path selector is always 1, the output of the decision device with the threshold Vo _ H1m is always selected by the odd-numbered path, the sampling data of the data odd is counted, the data odd is gradually processed according to the calibration process of the error slicer, and the offset value of the data odd-H1 path is finally found; fourthly, controlling an input end control code ofst _ de _ H1m of the DAC circuit to be 127, controlling an input end control code ofst _ de _ H1p to be 127, wherein the output of an even-numbered path selector is always 0, an odd-numbered path selector always selects the output of a decision device with a threshold Vo _ H1p, counting the sampling data of the data odd at the moment, and gradually performing the calibration process according to an error slicer, and finally finding out the offset value of the data odd + H1 path. After the six paths of offset calibration are completed, one round of calibration is completed, because of the existence of interference, some calibration results are inaccurate, so that multiple rounds of calibration are required, and then the calibration results are averaged to obtain the final calibration result. The calibration flow control of this step is shown in fig. 3, where "idle" in fig. 3 denotes initialization, "wait-cycle" denotes waiting for CDR lock statistics, "Round _ over? The ' expression judges whether the output data of the comparator contains ' 1 ', the ' Para _ adj ' expression enters an offset calibration stage, the number of ' 0 ' existing in the data output by the corresponding slicer in a period of time in the ' wait _ cycle ' state is counted, whether the counted number is larger than a set threshold is judged, if not, the ' Para _ adj ' state is entered to increase the control word of the threshold voltage of the slicer, and the ' wait _ cycle ' state is entered again to count a new result after the DAC digit is received.
And writing the bias value estimated in the bias calibration stage into a state register (the state register comprises a first latch and a second latch) for storage, and deducting the corresponding bias value from the threshold voltage control word of the comparator in the subsequent adaptive stage of the CTLE circuit and the DFE circuit.
In the adaptive adjustment stage of the CTLE circuit, the adaptive adjustment of the CTLE circuit is started when the state value state of the general state machine in fig. 2 is s _ ctl _ cal, from the time domain waveform in fig. 4, a waveform in which a high level "1" is long or a low level "0" is long shows the amplitude of a low frequency component, the amplitude of a high frequency component shows the steepness of a transition edge, a waveform in which single bits 0 and 1 alternately appear (that is, when high and low levels alternately appear within a unit time interval) shows the amplitude of a high frequency component, fig. 4 shows a time domain waveform in which a received signal is under-equalized before passing through the CTLE and over-equalized after passing through the CTLE, in fig. 4, the horizontal axis shows a data number index, the vertical axis shows a voltage value, a curve a shows an amplitude conversion curve before the adaptive equalization of the CTLE circuit, and a curve B shows an amplitude conversion curve after the adaptive equalization of the CTLE circuit. As can be seen from the waveforms in fig. 4, before equalization, when the signal is in an under-equalized state, the amplitude of the high-frequency component is small, the amplitude of the low-frequency component is large, and the change of the jump edge is slow; after the CTLE circuit is equalized, the amplitude difference of the high-frequency component and the low-frequency component is not large, the jump edge becomes very steep, but an overshoot phenomenon (the circle mark in FIG. 4) exists, so that the signal is in an over-equalization state at the moment. The application provides a specific algorithm for over-equalization and under-equalization: the method comprises the steps of firstly, adjusting a resistance value and a capacitance value of a CTLE circuit to enable a value of a resistance value R to be an intermediate value, obtaining an intermediate value of a direct current gain, enabling a value of a capacitance value C to be a minimum value, obtaining minimum gain compensation, enabling a received signal attenuated by a channel to be still in an under-balanced state after passing through the CTLE circuit, setting an expected value of a signal swing amplitude at the moment, adaptively adjusting the CTLE circuit, respectively subtracting threshold value control words of two paths of slicers after respectively subtracting offset values corresponding to error even/odd slicers from the expected value, counting sampling data output by the error slicers in a period of time in an initial state, if the data are all 0, indicating that the swing amplitude of a current low-frequency component does not reach a set value, increasing the resistance value (namely the R value) to improve the direct current gain until the R value is adjusted to a certain value, and enabling the number of 1 in data counted under the current R value and the number of 1 in data counted under the previous R value to be distributed on two sides of a set number threshold of 1, indicating that the amplitude of the current low frequency component has reached the desired value for the signal swing, the number of 1's in the data at the current R value, N0, is recorded. And secondly, gradually increasing the capacitance value (C value) to adjust the signal in the direction of over-equalization, increasing the amplitude of high-frequency components in the signal waveform along with the increase of the capacitance value, counting the number of 1 s in error slicer output data every time the C value is adjusted, and when the counted number of 1 s is distributed on two sides of the number N0 by two adjacent adjustments, considering that the equalization is proper, and the current R value and the current C value are configuration values in the optimal equalization. Fig. 5 is a state control diagram during the adaptive adjustment of CTLE, where wait _ cycle in fig. 5 is a result statistic state, r _ adj is a dc gain adjustment state, and only adjusts a resistance value control word, c _ adj is a peak gain adjustment state, and only adjusts a capacitance value control word, and is r _ adj _ over? That is, it is determined whether or not "1" is included in the capacitance value control word, and c _ adj _ over is 1? That is, it is determined whether or not the resistance value control word contains "0".
During the adaptive adjustment phase of the DFE circuit, when the control signal state output by the general state machine in fig. 2 is s _ DFE _ cal, the DFE adaptive phase is entered, for a 1-tap DFE circuit (i.e., a DFE circuit of half data rate pre-processing architecture), we consider only the effect of the first 1bit of data on the current data, the effect of 1 st level of cursor on the current data is h1, the impulse response value of the current data is h0, when the pattern d-1d0 is 00, the amplitude value dlev00 of the current data is-h 1-h0, when the pattern d-1d0 is 01, the amplitude value dlev01 of the current data is-h 1+ h0, when the code pattern d-1d0 is 10, the amplitude value dlev10 of the current data is h1-h0, when the pattern d-1d0 is 11, the amplitude value dlev11 of the current data is h1+ h0, so-h 1 ═ dlev00+ dlev01)/2, + h1 ═ dlev10+ dlev 11)/2. In combination with the calibration values of the respective slicers obtained by the offset calibration, in the adaptive adjustment stage of the DFE circuit, cw2dac _ de _ h1m ═ h1+ ofst _ de _ h1m, cw2dac _ de _ h1p ═ h1+ ofst _ de _ h1p, cw2dac _ do _ h1m ═ h1+ ofst _ do _ h1m, cw2dac _ do _ h1p ═ h1+ ofst _ do _ h1p, cw2dac _ ee ═ dlev ═ ofst _ h, cw2dac _ eo ═ dlev _ ofst _ eo, "0" or "1" may be obtained. Since the state machine in the DFE circuit is used to control the timing statistics of the patterns, the threshold control words of the error slicer are calculated using dlev00, dlev01, dlev10, and dlev11, respectively, for different pattern statistics periods. The implementation process of the DFE self-adaptive control algorithm mainly comprises two steps: in the first step, in the initial state, cw2dac _ de _ h1m is 0, cw2dac _ de _ h1p is 0, cw2dac _ do _ h1m is 0, and cw2dac _ do _ h1p is 0, at which time data slicer can output correctly-determined data with the maximum probability, dlev is calculated mainly by an LMS iterative algorithm, dlev (n +1) dlev (n) + u sign (e) d-1d0 is a set step (step size is 1 to 1/1024), e is data output by error slicer decision, and dlv means that when the code type is a predetermined value, the expected analog voltage amplitude of the current symbol is obtained, the current input voltage is compared with the actual input voltage, and the convergence value is obtained by a certain iterative computation. And secondly, after a period of time of iterative operation is carried out and dlev is stabilized, calculating-h 1 and + h1 by using a formula given by the current segment, and further calculating and updating the threshold voltage control words required by the obtained 4 paths of data slicers.
In summary, the adaptive equalization method provided by the application has clear implementation flow, the analog circuit design and digital algorithm control of the CTLE circuit and DFE circuit combined structure are convenient to implement, and the adaptive equalization method has strong configurability, the calibration precision of bias calibration and the adaptive adjustment precision of the CTLE circuit and the DFE circuit in the application depend on the precision of a DAC circuit to the maximum extent, the control algorithm of the FSM _ CTLE control unit adopts the amplitude characteristics of high and low frequency components based on time domain waveforms as the judgment basis of the equalization effect, the DFE control algorithm adopts the LMS iterative algorithm based on error symbols, and the equalization range covers the baud rate of 1.62G-8.1G. The circuit structure and the self-adaptive equalization algorithm are used in mass production products, 3-40-inch video cables are supported, and after equalization is completed, control of circuit parameters can be flexibly achieved, and the requirement of the products on self-adaptive equalization in actual use environments is met.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (10)
1. A control circuit device for a DP interface comprises a CTLE circuit and a CDR circuit, wherein the output of the CTLE circuit is connected with the input of the CDR circuit, the CTLE circuit comprises a two-stage cascade, the control end of the CTLE circuit is connected with a control unit FSM _ CTLE and two DAC circuits, the control unit FSM _ CTLE is used for outputting resistance value control words, and the two DAC circuits are used for outputting capacitance value control words; the DFE circuit adopts a half data rate preprocessing structure, the input of the DFE circuit is respectively connected with the output of the CTLE circuit, a clock control signal and a threshold voltage control signal, and the half data rate preprocessing structure comprises a comparator: interference comparator, data comparator, half data rate preliminary treatment indicates: and dividing the DAC circuit into an odd path and an even path according to the phase of a sampling clock, dividing the odd path and the even path into four paths according to different data division judgment thresholds, respectively working the four paths of comparators at the same time, and selecting a corresponding comparator to realize balance adjustment according to the value of the first 1bit during final output.
2. The control circuit arrangement for a DP interface of claim 1, wherein said odd-numbered stage comprises a data odd-numbered stage and an interference odd-numbered stage, said even-numbered stage comprises a data even-numbered stage and an interference even-numbered stage, said DFE circuit comprises a four-stage data comparator (data slicer) and a two-stage interference comparator (error slicer), a six-stage data comparator comprises a first data comparator and a fourth data comparator, said data even-numbered stage comprises a first data comparator and a second data comparator, said data odd-numbered stage comprises a third data comparator and a fourth data comparator, said interference even-numbered stage comprises a fifth interference comparator, and said interference odd-numbered stage comprises a sixth interference comparator.
3. The control circuitry for a DP interface of claim 2, wherein said DFE circuit further comprises two data selectors: the input of the first data selector is connected with the output of the data even circuit, and the selection ends and the output ends of the first data selector and the second data selector are respectively connected in a cross mode through a first latch and a second latch.
4. An adaptive equalization method implemented by the control circuit device according to claim 1 or 3, for performing adaptive equalization adjustment on a receive channel of a DP interface, wherein the adaptive equalization method comprises: s1, an offset calibration stage;
s2, performing adaptive adjustment on the CTLE circuit;
s3, locking the CDR circuit;
s4, a DFE circuit self-adaptive adjusting phase;
and in the adaptive adjustment stage of the CTLE circuit, the CDR circuit is actively controlled to enable the clock to be in an unlocked state, and after the adaptive adjustment of the CTLE circuit is finished, the DFE circuit is subjected to the adaptive adjustment after the CDR circuit is locked.
5. The adaptive equalization method according to claim 4, wherein the offset calibration phase calibrates an offset introduced by the comparator, the offset calibration comprising: s11, the CTIE circuit inputting differential signal pair Vin _ p and Vin _ n to the DFE circuit, the differential voltage signal Vin being Vin _ p-Vin _ n, shorting Vin _ p and Vin _ n and by clamping to a fixed voltage value; s12, calibrating the four paths of data paths in sequence, and searching the offset value of the corresponding comparator, wherein the steps include: a1, adjusting the threshold voltage of the corresponding comparator to gradually increase the threshold voltage from the preset minimum value; a2, counting the output data of the comparator in the time period T corresponding to each threshold voltage in the threshold voltage adjusting process; a3, in the process of adjusting the threshold voltage of the corresponding comparator, when the output data of the comparator contains 0, the corresponding threshold voltage value is the offset value of the path where the comparator is located.
6. The adaptive equalization method according to claim 5, wherein a plurality of calibration rounds are performed based on the step of finding the offset value of the corresponding comparator, and the final offset value of the path where the corresponding comparator is located is an average value of the offset values of the plurality of calibration rounds; the method for calibrating the offset value by four data comparators in a time-sharing sequence is adopted, and when one comparator in an even path is calibrated, the threshold voltages of two comparators in an odd path are controlled to be the maximum value or the minimum value at the same time; when one comparator in the odd-numbered path is calibrated, the threshold voltages of the two comparators in the even-numbered path are controlled to be the maximum value or the minimum value at the same time.
7. The adaptive equalization method as claimed in claim 4, wherein the CTLE circuit adaptively adjusts the timing by searching for under-and over-equalized characteristics from the time domain waveform, and determines the signal state as under-equalized when the amplitude of the low frequency component is greater than the amplitude of the high frequency component, and determines the signal state as over-equalized when the amplitudes of the low frequency component and the high frequency component are the same but there is an overshoot signal at the data transition edge.
8. The adaptive equalization method of claim 7, wherein after the CTLE circuit starts adaptive adjustment, the desired value amplitude is adjusted to control the threshold voltage of the interference comparator, and in an initial state, the desired value amplitude is configured to be the maximum, and the capacitance control word takes the minimum value to make the CTLE output signal in an under-equalized state;
the step of judging whether the signal state is over-balanced comprises the following steps: firstly, adjusting a resistance value control word to realize direct current gain control: adjusting the amplitude of low-frequency components in the output signal of the CTLE circuit, and when the output data of the interference comparator contains '1', indicating that the amplitude of the low-frequency components reaches an expected value; and step two, gradually increasing the capacitance control word to improve the high-frequency gain: and adjusting the amplitude of high-frequency components in the output signal of the CTLE circuit, and when the number of '1' in the output data of the interference comparator is more than that of '1' in the first step, indicating that the signal state at the moment is over-balanced.
9. The adaptive equalization method as recited in claim 4, wherein the DFE circuit adaptively adjusts the timing by selecting the corresponding threshold voltage according to a pattern, wherein the state machine of the control unit of the DFE circuit corresponds to four patterns, the four patterns comprising 00, 01, 10, 11, and wherein the corresponding threshold voltage is selected according to the pattern: and counting the four code patterns in a time-sharing manner, calculating to obtain the expected values of the analog voltages corresponding to the current bits, wherein the expected values of the analog voltages corresponding to the current bits of the four code patterns 00, 01, 10 and 11 are respectively dlev00, dlev01, dlev01 and dlev11, and the four groups of expected values correspond to the threshold voltages of the four state time-sharing output control interference comparators of the state machine.
10. The adaptive equalization method as claimed in claim 4, wherein the two cascaded stages of capacitance value control words in the CTLE circuit are adjusted by the voltage of DAC circuit, the threshold voltages of all comparators in the DFE circuit are from the respective corresponding DAC circuits, the control words of the DAC circuit are from the digital control unit, and the DAC circuit requires the input control word to be gray code.
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