CN114207700A

CN114207700A - Source driver for controlling bias current

Info

Publication number: CN114207700A
Application number: CN202080054421.6A
Authority: CN
Inventors: 崔正珉; 金亨燮
Original assignee: LX Semicon Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2019-08-09
Filing date: 2020-08-07
Publication date: 2022-03-18
Also published as: KR20210018151A

Abstract

In one aspect, the present invention relates to a source driver for controlling a bias current, and more particularly, to a source driver as follows: the bias current of the buffer is controlled according to the distance between the source driver and the pixels in the data line, and the position to which the bias current is set and the intensity of the bias current are changed in each frame, so that unnecessary power consumption due to the bias current can be minimized and the block dim phenomenon can be reduced.

Description

Source driver for controlling bias current

Technical Field

The present invention relates to a source driver for controlling a bias current and a display device including the same.

Background

The display device may include a panel, a source driver for driving the panel, and a timing controller for controlling driving of the source driver. The panel may include a plurality of pixels arranged to form rows in a horizontal direction and columns in a vertical direction. The plurality of pixels are arranged in a matrix in the panel. A row formed by a plurality of pixels arranged in the horizontal direction may be referred to as a line (line).

The timing controller may transmit the driving control data and the image data to the source driver. The timing controller may control driving timing of the panel by the source driver through the driving control data. The timing controller may transmit the image data to the source driver.

The source driver may simultaneously drive a plurality of pixels in one line. The source driver may generate an image signal from the image data to drive a plurality of pixels in the panel. The source driver may include a digital-to-analog converter (DAC) and a buffer. The DAC may convert the image data into a data voltage as an analog signal. The buffer of the channel of the source driver may be connected with a plurality of data lines arranged in a vertical direction in the panel. The buffer may amplify the data voltage and output the data voltage to the pixel through the data line of each channel.

The buffer may use the bias current to adjust a slew (slew) rate of the voltage output to the data line of the channel. The buffer may receive a bias current having a high strength and adjust the slew rate high. On the other hand, the buffer may receive a bias current having a low strength and adjust the slew rate low.

Conventionally, bias currents having uniform intensities regardless of the positions of pixels on data lines have been supplied to buffers. That is, conventionally, the buffer outputs the data voltage using bias currents having the same intensity for both the pixels adjacent to the source driver on the data line and the pixels distant from the source driver. However, it is not necessary to drive neighboring pixels using a bias current having a high intensity for driving the distant pixels. If a high intensity bias current is used to drive neighboring pixels, excessive power consumption may occur in the buffer. In addition, the power consumption of the buffer accounts for a large portion of the entire power consumption of the source driver. For this reason, it is necessary to adjust the bias current differently according to the position of the pixel on the data line to reduce the power consumption of the source driver.

Disclosure of Invention

Problems to be solved by the invention

In this context, an aspect of the present invention provides a technique for distinguishing the strength of the bias current of the buffer according to the distance on the data line between the source driver and the pixel.

Another aspect of the invention provides techniques for adjusting the bias current in the buffer such that the data voltage for each pixel on the data line is saturated for a predetermined time.

Yet another aspect of the present disclosure provides techniques for setting bias currents for pixels at different locations in each frame.

Means for solving the problems

To this end, in one aspect, the present invention provides a source driver comprising: a buffer for outputting a plurality of data voltages using a bias current to drive a plurality of pixels connected to a data line; and a bias control circuit for adjusting the intensity of the bias current according to the position of each pixel connected to the data line, wherein the bias control circuit differently determines a pixel position for which the intensity of the bias current is adjusted in each frame, and differently determines the intensity of the bias current to be adjusted for the pixel of the pixel position in each frame.

In the source driver, the bias control circuit may receive a bias control signal including position data of a pixel for which the intensity of the bias current is adjusted and timing data specifying a timing for adjusting the intensity of the bias current.

In the source driver, the bias control signal may include strength data of a bias current to be adjusted.

In the source driver, the bias control signal may be generated and transmitted by the timing controller.

In the source driver, the bias control circuit may adjust the bias current to have a first intensity for a first group of pixels among the plurality of pixels and adjust the bias current to have a second intensity for a second group of pixels among the plurality of pixels in each channel.

In the source driver, the second group of pixels may be farther than the first group of pixels in the data line, and the bias control circuit may adjust the second intensity to be higher than the first intensity.

In the source driver, the second group of pixels may include a boundary pixel in which the intensity of the bias current is changed to the second intensity, and the bias control circuit may determine the boundary pixel randomly or according to a predetermined rule, adjust the intensity of the bias current for the boundary pixel to the second intensity in a first frame, and adjust the intensity of the bias current for the boundary pixel to a third intensity different from the second intensity in a second frame.

In the source driver, a difference between a time of forming the data voltage for the first group of pixels and a time of forming the data voltage for the second group of pixels may be within a predetermined range.

In the source driver, different pixels may be determined as boundary pixels in each frame, and the boundary pixels respectively in adjacent channels can be located in different lines.

In the source driver, the bias control circuit may adjust the bias current to have the highest intensity to drive the pixel farthest from the source driver and adjust the bias current to have the lowest intensity to drive the pixel located closest to the source driver.

In the source driver, a difference between a time at which a data voltage is formed for a pixel farthest from the source driver and a time at which a data voltage is formed for a pixel located closest to the source driver may be within a predetermined range.

In the source driver, the bias control circuit may divide the plurality of pixels into a plurality of groups, and adjust the intensity of the bias current to be different for each group. The bias control circuit may adjust the bias current to have the highest intensity to drive the pixel group farthest from the source driver and adjust the bias current to have the lowest intensity to drive the pixel group located closest to the source driver.

In the source driver, a difference between a time at which a data voltage for a group farthest from the source driver is formed and a time at which a data voltage for a group located closest to the source driver is formed may be within a predetermined range.

In another aspect, the present invention provides a source driver, including: a buffer for outputting an Mth data voltage for an Mth pixel connected to a data line using an Mth bias current, outputting an Nth data voltage for an Nth pixel connected to the data line using an Nth bias current having a higher intensity than that of the Mth bias current, consuming an Mth power required for the Mth bias current, and consuming an Nth power required for the Nth bias current and greater than the Mth power, M being a natural number equal to or greater than 1, N being a natural number equal to or greater than M + 1; and a bias control circuit for generating the Mth bias current and the Nth bias current and supplying the Mth bias current and the Nth bias current to the buffer, wherein the bias control circuit determines different pixels as the Mth pixel and the Nth pixel in each frame and determines the Mth bias current and the Nth bias current as different in each frame.

In the source driver, the buffer may operate in a first mode in which the buffer outputs the mth data voltage using the mth bias current and outputs the nth data voltage using the nth bias current, or in a second mode in which the buffer outputs the mth data voltage and the M +1 th data voltage using bias currents having the same strength.

In the source driver, the bias control circuit may generate the mth bias current for an mth group of pixels including the mth pixel, and generate the nth bias current for an nth group of pixels including the nth pixel.

ADVANTAGEOUS EFFECTS OF INVENTION

As described above, according to the present invention, it is possible to reduce power consumption of the entire display apparatus by minimizing unnecessary power consumption caused by a bias current.

In addition, the present invention enables dynamic and adaptive control of the bias current according to the position of the pixel on the data line of the channel.

In addition, the invention enables a more efficient and simple control of the bias current.

In addition, the present invention enables the block dim (block dim) phenomenon to be reduced.

Drawings

Fig. 1 is a structural diagram of a display device according to an embodiment.

Fig. 2 is a structural diagram of a source driver according to an embodiment.

Fig. 3 is a graph showing the slew rate over time of voltages applied to a plurality of pixels connected to one data line.

Fig. 4 is a diagram showing power consumed by bias current in a plurality of pixels connected to one data line.

Fig. 5 is a graph showing a slew rate with the passage of time of voltages applied to a plurality of pixels connected to one data line according to an embodiment.

Fig. 6 is a diagram illustrating power consumed by bias current in a plurality of pixels connected to one data line according to an embodiment.

Fig. 7 is a diagram illustrating bias currents used by a buffer according to another embodiment to drive a plurality of pixels connected to one data line.

Fig. 8 is a diagram illustrating a dimming phenomenon depending on the setting of the bias current.

Fig. 9 is a diagram showing that the position of adjusting the bias current changes in each frame according to still another embodiment.

Fig. 10 is a diagram showing that the position of adjusting the bias current changes in each frame and the intensity of the bias current at the position also changes in each frame according to still another embodiment.

Fig. 11 is a diagram illustrating generation and transmission/reception of a bias control signal according to still another embodiment.

Detailed Description

Some embodiments of the invention will be described in detail below with reference to the accompanying drawings. With respect to the reference numerals of the components of the respective drawings, it should be noted that the same reference numerals are assigned to the same components although the components are shown in different drawings. In addition, in describing the present invention, detailed descriptions of well-known structures or functions related to the present invention, which may obscure the subject matter of the present invention, will be omitted.

In addition, terms such as "first", "second", "A", "B", "a", "B", or "(B)" may be used in describing the components of the present invention. These terms are only used to distinguish the corresponding component from other components, and the nature, order, or sequence of the corresponding component is not limited to these terms. In the case where components are described as being "coupled", "combined", or "connected" to another component, it is to be understood that the respective components may be directly coupled or connected to the other component, or the respective components may also be "coupled", "combined", or "connected" to a certain component via another component disposed between the respective components and the certain component.

Fig. 1 is a structural diagram of a display device according to an embodiment.

Referring to fig. 1, a display device 10 may include a panel 11, a source driver 12, a gate driver 13, and a timing controller 14.

In the panel 11, a plurality of data lines DL and a plurality of gate lines GL may be arranged, and a plurality of pixels P may also be arranged. The plurality of pixels P may be arranged close to each other in the horizontal direction H and the vertical direction V to form a square. The square form is similar to the matrix form. A group or horizontal line formed by a plurality of pixels P arranged in the horizontal direction H may be defined as a row or a line, and a group or vertical line formed by a plurality of pixels P arranged in the vertical direction V may be defined as a column.

The gate driver 13 may supply a scan signal of an on voltage or an off voltage to the gate lines GL. The pixel P may be connected to the data line DL when a scan signal of an on voltage is supplied to the pixel P. The pixel P may be disconnected from the data line DL when a scan signal of an off voltage is supplied to the pixel P.

For example, the pixel electrode PE may be connected to the data line when the scan transistor STR of the pixel P is turned on by a scan signal of a turn-on voltage. The pixel electrode PE may be disconnected from the data line when the scan transistor STR of the pixel P is turned off by the scan signal of the off voltage.

The source driver 12 supplies a data voltage to the data lines DL. The data voltage supplied to the data line DL may be transmitted to the driving transistor of the pixel P connected to the data line DL by a scan signal. The source driver 12 may sequentially output data voltages to the driving transistors DTR of the plurality of pixels P while the driving transistors DTR of the plurality of pixels P connected to one data line DL are sequentially turned on by a scan signal of a turn-on voltage.

The timing controller 14 may supply various control signals to the gate driver 13 and the source driver 12. The timing controller 14 may generate a gate control signal GCS to initiate scanning according to the timing of each frame and transmit the gate control signal GCS to the gate driver 13. In addition, the timing controller 14 may receive image data from an external device and output the image data RGB (which is converted into a form of data used in the source driver 12) to the source driver 12. Further, the timing controller 14 may transmit a data control signal DCS to control the source driver 12 to supply the data voltage to each pixel P at an appropriate timing.

Fig. 2 is a structural diagram of a source driver according to an embodiment.

Referring to fig. 2, the source driver 12 may include a first latch circuit 210, a second latch circuit 220, a digital-to-analog converter (DAC)230, a buffer 240, a bias control circuit 250, and a driving control circuit 260.

The first latch circuit 210 may latch the image data RGB. The first latch circuit 210 may temporarily store the image data RGB and output the image data RGB to the second latch circuit 220. The first latch circuit 210 may temporarily store the image data RGB and output the image data RGB to the second latch circuit 220 according to a clock of a shift register (not shown).

The second latch circuit 220 may latch the image data RGB. The second latch circuit 220 may temporarily store the image data RGB and output the image data RGB to the DAC 230. The second latch circuit 220 may temporarily store the image data RGB and output the image data RGB to the DAC 230 according to a clock of a shift register (not shown).

The DAC 230 may receive the image data RGB from the second latch circuit 220. The DAC 230 may generate data voltages as analog signals from the image data RGB. The DAC 230 may select a gray voltage corresponding to the image data RGB transmitted from the second latch circuit 220 among a predetermined number of gray voltages generated according to gamma reference voltages input from an external device and output the gray voltage to the buffer 240.

The buffer 240 may receive the data voltage from the DAC 230. The buffer 240 may amplify the data voltage and supply the data voltage to the data line.

The buffer 240 may receive a bias current from the bias control circuit 250 and output a data voltage. The buffer 240 may output a data voltage according to the bias current. The buffer 240 may adjust the slew rate of the data voltage by the bias current.

The bias control circuit 250 may generate a bias current and supply the bias current to the buffer 240. For example, the BIAS control circuit 250 may receive the BIAS power BIAS _ PWR from an external device. The BIAS power BIAS _ PWR may include a plurality of BIAS currents. The BIAS control circuit 250 may receive a BIAS control signal BIAS _ CTR _ SIG from the driving control circuit 260. The BIAS control circuit 250 may select one of a plurality of BIAS currents included in the BIAS power BIAS _ PWR using the BIAS control signal BIAS _ CTR _ SIG and output the selected BIAS current to the buffer 240. On the other hand, the BIAS control circuit 250 may generate the BIAS current by adjusting the amount of current included in the BIAS power BIAS _ PWR using the BIAS control signal BIAS _ CTR _ SIG. On the other hand, the BIAS control circuit 250 may generate the BIAS current by increasing or decreasing the amount of current included in the BIAS power BIAS _ PWR.

In addition, the bias control circuit 250 may adjust the bias current differently according to the positions of a plurality of pixels connected to one data line. The bias control circuit 250 can distinguish the bias current for each pixel according to how far the pixel is from the source driver 12. For example, the bias control circuit 250 may adjust the bias current to have a low strength to drive the pixels adjacent to the source driver 12. On the other hand, the bias control circuit 250 may adjust the bias current to have a high strength to drive the pixels distant from the source driver 12.

The BIAS control circuit 250 may determine whether to adjust the BIAS current according to the BIAS control signal BIAS _ CTR _ SIG. On the other hand, the BIAS control circuit 250 may determine the position of the pixel for which the BIAS current is adjusted according to the BIAS control signal BIAS _ CTR _ SIG. On the other hand, the BIAs control circuit 250 may determine how high or low the BIAs current will have according to the BIAs control signal BIA _ CTR _ SIG. On the other hand, the BIAS control circuit 250 may determine a pixel (boundary pixel) in which the setting of the BIAS current is changed in each frame, and adjust the BIAS current based on the BIAS control signal BIAS _ CTR _ SIG according to the determination.

The driving control circuit 260 may receive image data RGB from the timing controller. The driving control circuit 260 may transmit the image data RGB to the first latch circuit 210. The image data RGB may be output to the pixels connected to the data lines through the buffer 240 via the second latch circuit 220 and the DAC 230.

The driving control circuit 260 may receive a data control signal DCS from the timing controller. The driving control circuit 260 may generate a clock from the data control signal DCS and provide the clock to drive the first latch circuit 210, the second latch circuit 220, the DAC 230, and the buffer 240.

The driving control circuit 260 may generate a BIAS control signal BIAS _ CTR _ SIG from the data control signal DCS. The BIAS control signal BIAS _ CTR _ SIG may determine whether to adjust the BIAS current. For example, the bias control circuit 250 may operate in a first mode in which the bias currents are differentially adjusted and supplied to the buffer 240 and a second mode in which the bias currents are not adjusted but supplied to the buffer 240 with the same intensity. The BIAS control signal BIAS _ CTR _ SIG may include information to assume one of a first mode and a second mode. On the other hand, the BIAS control signal BIAS _ CTR _ SIG may include information for making an adjustment of a BIAS current for a plurality of pixels connected to one data line. For example, the BIAS control signal BIAS _ CTR _ SIG may include information of a position of a pixel requiring an adjusted BIAS current. On the other hand, the BIAS control signal BIAS _ CTR _ SIG may include information of a current value that varies each time each pixel is driven. The BIAS control signal BIAS _ CTR _ SIG may include information of a position of a pixel (boundary pixel) where the setting of the BIAS current is changed in each frame.

The drive control circuit 260 may determine the location of the pixel that requires adjustment of the bias current.

For example, the drive control circuit 260 may receive position data of the pixels from the timing controller and determine the pixels that require adjustment of the bias current. The position data may be transmitted from the timing controller to the drive control circuit 260 in a state of being included in the data control signal DCS. The drive control circuit 260 may determine the pixels that require adjustment of the bias current based on the position data. The driving control circuit 260 may include the position data of the pixel in the BIAS control signal BIAS _ CTR _ SIG and transmit the signal to the BIAS control circuit 250. The bias control circuit 250 may adjust a bias current for a pixel determined based on the position data and supply the bias current to the buffer 240.

As another example, the drive control circuit 260 may generate timing to determine pixels that require adjustment of the bias current. The drive control circuit 260 may measure a scanning time of the pixels of one line and may control the scanning time according to the scanning timeThe passage of time determines the location of the pixel requiring adjustment of the bias current. If the scanning time of the pixels of each line is t₁The driving control circuit 260 may generate a timing for the first pixel located in the first line of the panel at the time of the start of the frame and include the timing in the BIAS control signal BIAS _ CTR _ SIG to transmit the timing to the BIAS control circuit 250. The bias control circuit 250 may adjust a bias current of the first pixel and supply the bias current to the buffer 240. Subsequently, the drive control circuit 260 may pass t₁Timing is then generated for a second pixel located in a second line of the panel and sent to the bias control circuit 250. The bias control circuit 250 may adjust a bias current of the second pixel and supply the bias current to the buffer 240. Subsequently, the drive control circuit 260 may pass 2t₁The timing is then generated for the third pixel located in the third line of the panel and sent to the bias control circuit 250. The bias control circuit 250 may adjust a bias current of the third pixel and supply the bias current to the buffer 240.

The buffer 240 may output the data voltage based on the adjusted bias current. For example, the buffer 240 may receive a first bias current and output a first data voltage corresponding to first image data to the pixels of the first line based on the first bias current. The buffer may receive the second bias current and output a second data voltage corresponding to the second image data to the pixels of the second line based on the second bias current. Here, the second bias current may be adjusted to have a higher intensity than that of the first bias current.

Preferably, the buffer 240 may use a bias current that is differently adjusted according to the positions of a plurality of pixels connected to one data line. The buffer 240 may receive the differently adjusted bias currents and output different data voltages based on the bias currents. The buffer 240 may output different data voltages according to how far the pixel is from the source driver 12. For example, the buffer may output the first data voltage to a pixel close to the source driver 12 using a bias current adjusted to have a low intensity. On the other hand, the buffer 240 may output the second data voltage to a pixel far from the source driver 12 using a bias current adjusted to have a high strength.

Fig. 3 shows a plurality of pixels connected to one data line and slew rates corresponding to the respective pixels. According to the conventional art, the buffer 340 may use a bias current having the same strength regardless of the position of the pixel connected to one data line to output the data voltage corresponding to each pixel. Accordingly, the buffer 340 may output the data voltage to the pixels near the source driver and the pixels far from the source driver using the bias currents having the same strength.

For example, the buffer 340 may output a data voltage to a plurality of pixels P _1, P _2, …, P _ N-1, P _ N connected to one data line using bias currents having the same strength.

Here, each of the plurality of pixels P _1, P _2, …, P _ N-1, P _ N may include a scan transistor STR₁、STR₂、…、STR_N-1、STR_NAnd a driving transistor DTR₁、DTR₂、…、DTR_N-1、DTR_NAnd a pixel electrode PE₁、PE₂、…、PE_N-1、PE_N. In one data line, a resistive element and a capacitive element may be present. The resistance element may be generated in the data line when the data voltage is applied to each pixel. The capacitive element may be generated by coupling between the data line and another line or electrode adjacent to the data line. The resistance elements may be referred to as resistances R corresponding to the plurality of pixels P _1, P _2, …, P _ N-1, P _ N, respectively₁、R₂、…、R_N-1、R_N. The capacitive elements may be referred to as capacitors C corresponding to the plurality of pixels P _1, P _2, …, P _ N-1, P _ N, respectively₁、C₂、…、C_N-1、C_N。

When the buffer 340 outputs the data voltages to the plurality of pixels P _1, P _2, …, P _ N-1, P _ N using the bias currents having the same strength, slew rates of the data voltages applied to the data lines for the respective pixels may be different from each other according to distances from the buffer 340 to the respective pixels. In fig. 3, the slew rates are shown as graphs each having an axis of TIME (TIME) and an axis of DATA voltage (V _ DATA).

Assuming that all the data voltages of the plurality of pixels P _1, P _2, …, P _ N-1, P _ N are obtained by changing the same input data voltage by the same change width Δ V, when the buffer 340 outputs the data voltage for each pixel, the data voltage may be output from a point of time when the pixel is connected to the data line by the scan signal of the on voltage until a point of time when the pixel is disconnected from the data line by the scan signal of the off voltage (gate-off-point GOP).

The buffer 340 outputs a first data voltage V for driving the first pixel P _1_{data_1}The input data voltage may be changed by Δ V to reach the first data voltage V_{data_1}And has a first conversion rate SR₁. The input data voltage reaches a first data voltage V_{data_1}May be referred to as a first saturation point SP₁. First saturation point SP₁May mean that from a time point when the first pixel P _1 is connected to the data line by the scan signal of the gate driver until the input data voltage reaches the first data voltage V_{data_1}Time elapsed until the time point of (2).

The second data voltage V for driving the second pixel P _2 is output at the buffer 340_{data_2}The input data voltage may be changed by Δ V to reach the second data voltage V_{data_2}And has a second slew rate SR₂. The input data voltage reaches the second data voltage V_{data_2}May be referred to as a second saturation point SP₂. Second saturation point SP₂May mean that from a time point when the second pixel P _2 is connected to the data line by the scan signal of the gate driver until the input data voltage reaches the second data voltage V_{data_2}Time elapsed until the time point of (1)。

Outputs the N-1 th data voltage V for driving the N-1 th pixel P _ N-1 at the buffer 340_{data_N-1}Then, the input data voltage may be changed by Δ V to reach the N-1 th data voltage V_{data_N-1}And has an N-1 th slew rate SR_N-1. The input data voltage reaches the N-1 th data voltage V_{data_N-1}May be referred to as an N-1 th saturation point SP_N-1. N-1 th saturation point SP_N-1May mean that from a time point when the (N-1) th pixel P _ N-1 is connected to the data line by a scan signal of the gate driver until the input data voltage reaches the (N-1) th data voltage V_{data_N}-the time elapsed until the time point of 1.

Outputting the Nth data voltage V for driving the Nth pixel P _ N at the buffer 340_{data_N}Then, the input data voltage may be changed by Δ V to reach the nth data voltage V_{data_N}And has an Nth slew rate SR_N. The input data voltage reaches the Nth data voltage V_{data_N}May be referred to as an nth saturation point SP_N. Nth saturation point SP_NMay mean that from a time point when the nth pixel P _ N is connected to the data line by a scan signal of the gate driver until the input data voltage reaches the nth data voltage V_{data_N}Time elapsed until the time point of (2).

Since the buffer 340 outputs the data voltage to the plurality of pixels P _1, P _2, …, P _ N-1, P _ N using the bias current having the same strength, the first to Nth slew rates SR₁、SR₂、…、SR_N-1、SR_NMay be different. For example, the first conversion rate SR₁Can be high, and the second slew rate SR₂May be lower than the first conversion rate SR₁. The first data voltage V supplied to the first pixel P _1_{data_1}May be greater than the second data voltage V_{data_2}Is relatively short. The delay may occur due to a resistive element and a capacitive element. The longer the delay, the lower the slew rate becomes, and the shorter the delay, the higher the slew rate becomes. First data voltage V_{data_1}Possibly through a resistor R₁And a capacitor C₁But the second data voltage V_{data_2}Possibly through two resistors R₁、R₂And two capacitors C₁、C₂. For this reason, the first data voltage V_{data_1}The associated delay may be greater than the second data voltage V_{data_2}The delay involved is short, so the first slew rate SR₁Can be compared with the second conversion rate SR₂High. The first saturation point SP due to the difference between the slew rates₁May be greater than the second saturation point SP₂Short.

For the same reason, the N-1 th slew rate SR_N-1Can compare the Nth conversion rate SR_NHigh. The first conversion rate SR when comparing all conversion rates of a plurality of pixels P _1, P _2, …, P _ N-1, P _ N₁May be the highest, and the Nth slew rate SR_NMay be the lowest. Due to the delay caused by the resistive and capacitive elements, the associated slew rate may be higher when the pixel is closer to the source driver (i.e., buffer 340) and lower when the pixel is farther from buffer 340. Due to the difference in slew rates, the associated saturation point may be shorter as the pixel is closer to buffer 340 and longer as the pixel is farther from buffer 340.

On the other hand, when the buffer 340 drives the plurality of pixels P _1, P _2, …, P _ N-1, P _ N using the bias currents having the same intensity, each data voltage may reach a desired level within the gate cut point GOP. However, generating all the data voltages using the bias currents having the same strength may unnecessarily increase power consumption due to the bias currents.

For example, since the first data voltage V for the first pixel P _1 can be reached within a predetermined time_{data_1}Accordingly, the buffer 340 may output the first data voltage V using the bias current having the low intensity_{data_1}. However, the nth data voltage V for the nth pixel P _ N may not be reached within a predetermined time_{data_N}Therefore, the buffer 340 needs to use a bias current having a high intensity. The reason for this is that the resistance elementAnd capacitive elements to cause the delay to become longer as the pixel is farther from the buffer 340. For this reason, driving both the pixel near the buffer 340 as the first pixel P _1 and the pixel far from the buffer 340 as the nth pixel P _ N with the bias current having the same strength may unnecessarily increase the power consumed by the buffer 340. If a bias current having a low intensity is used for a pixel close to the buffer 340 and a bias current having a high intensity is used for a pixel far from the buffer 340, power consumption in the buffer 340 due to the bias current can be significantly reduced.

Fig. 4 shows a plurality of pixels connected to one data line and power consumed due to a bias current for each pixel. Conventionally, the buffer 340 may output data voltages corresponding to respective pixels using bias currents having the same intensity regardless of the positions of the respective pixels in the data lines. Therefore, the buffer 340 may consume the same power when driving a pixel close to the source driver and when driving a pixel far from the source driver.

For example, the power consumed by the buffer for the bias current to drive the plurality of pixels P _1, P _2, …, P _ N-1, P _ N may be the same regardless of the position of the pixel. In other words, the buffer 340 consumes the first power P with respect to the bias current for driving the first pixel P _1₁The buffer 340 consumes the second power P with respect to the bias current for driving the second pixel P _2₂ Buffer 340 consumes N-1 power P with respect to bias current for driving N-1 pixel P _ N-1_N-1And the Nth power P consumed by the buffer 340 with respect to the bias current for driving the Nth pixel P _ N_NMay be identical.

Total power P consumed by buffer 340 in one data line for bias current_TCan be matched with the first power to the Nth power P₁、P₂、…、P_N-1、P_NThe sum of (a) and (b) is the same. In fig. 4, the total power P_TAnd first to Nth powers P₁、P₂、…、P_N-1、P_NShown as a graph with an axis of POWER (POWER) and an axis of DISTANCE (DISTANCE) relative to the DISTANCE of the buffer 340.

Fig. 5 illustrates a plurality of pixels connected to one data line and slew rates corresponding to the respective pixels according to an embodiment. According to an embodiment, the buffer 240 may output data voltages corresponding to respective pixels using bias currents having different intensities according to positions of the pixels. That is, the buffer 240 may output the data voltage to a pixel near the source driver using a bias current having a low intensity and output the data voltage to a pixel far from the source driver using a bias current having a high intensity.

For example, the buffer 240 may output the data voltage to a plurality of pixels P _1, P _2, …, P _ N-1, P _ N connected to one data line using different bias currents. Specifically, the buffer 240 may output the data voltage using a bias current whose intensity increases as the output of the data voltage progresses for the pixels P _1 to P _ N from the first pixel to the nth pixel.

When the buffer 240 outputs the data voltages to the plurality of pixels P _1, P _2, …, P _ N-1, P _ N using different bias currents, the slew rates of the data voltages corresponding to the respective pixels may be similar to each other regardless of the distance between the buffer 240 and the respective pixels. Similarity may mean that the difference between the slew rates is within a certain range, even if the slew rates are not the same, where the range may be predetermined.

For example, in the case where the buffer 240 sequentially outputs the data voltages to the respective pixels under the same condition as fig. 3, the data voltages may be output from a time point when the pixels are connected to the data lines by the scan signal of the on voltage from the gate driver until a time point when the pixels are disconnected from the data lines by the scan signal of the off voltage (gate off point (GOP)).

Outputting a first data voltage V using a first bias current at a buffer 240_{data_1}To drive the first pixel P _1, the input data voltage can be changed by Δ V to reach the first data voltage V_{data_1}And has a first conversion rate SR₁。

Then, the second data voltage V is output at the buffer 240 using the second bias current_{data_2}To drive the second pixel P _2, the input data voltage can be changed by Δ V to reach the second data voltage V_{data_2}And has a second slew rate SR₂. The strength of the second bias current may be higher than the strength of the first bias current.

Subsequently, the N-1 th data voltage V is output at the buffer 240 using the N-1 th bias current_{data_N-1}To drive the N-1 th pixel P _ N-1, the input data voltage can be changed by Δ V to reach the N-1 th data voltage V_{data_N-1}And has an N-1 th slew rate SR_N-1. The magnitude of the N-1 th bias current may be higher than the magnitude of the second bias current. Preferably, the intensity of the N-1 th bias current may be higher than that of the N-2 th bias current used for the N-2 th pixel driven before the N-1 th pixel P _ N-1.

Finally, the buffer 240 outputs the Nth data voltage V using the Nth bias current_{data_N}To drive the Nth pixel P _ N, the input data voltage can be changed by Δ V to reach the Nth data voltage V_{data_N}And has an Nth slew rate SR_N. The strength of the nth bias current may be higher than that of the N-1 th bias current.

Since the buffer 240 uses the bias current with increased intensity while the buffer 240 sequentially outputs the data voltages for the first to second pixels P _1 to P _2, the first slew rate SR₁And a second slew rate SR₂May be similar to each other. The first data voltage V supplied to the first pixel P _1_{data_1}May be more delayed than the second data voltage V_{data_2}The delay of (3) is short. However, for the first data voltage V_{data_1}Is adjusted to have a low strength and for a second data voltage V_{data_2}Second bias ofThe first conversion rate SR when the current is adjusted to have a high intensity₁And a second slew rate SR₂May be similar and the difference between the two may be within a predetermined range. That is, the first slew rate SR₁Can become slightly lower and the second slew rate SR₂May become slightly higher.

Such a variation of the slew rate may be applied to the slew rates associated with the first to nth pixels P _1 to P _ N. The first slew rate to the Nth slew rate SR when the first to Nth bias currents are changed₁、SR₂、…、SR_N-1、SR_NMay be changed accordingly. First to Nth conversion rates SR₁、SR₂、…、SR_N-1、SR_NThe difference therebetween may be within a predetermined range. As the slew rate becomes similar, the first to nth saturation points SP₁、SP₂、…、SP_N-1、SP_NMay become similar to each other.

When the buffer 240 drives the plurality of pixels P _1, P _2, …, P _ N-1, P _ N by using the data voltages obtained by the differently adjusted bias currents, the respective data voltages may reach desired levels within the gate cut point GOP. Generating the data voltage using the differentially adjusted bias current may reduce the power consumed by the bias current.

For example, the first data voltage V for the first pixel P _1_{data_1}Can be sufficiently reached within a predetermined time, and the buffer 240 can output the first data voltage V using a first bias current having a relatively low intensity_{data_1}. Since the buffer 240 uses the first bias current having a low strength, the power consumed by the buffer 240 can be reduced. Even if the buffer 240 uses a bias current having a high intensity for the nth pixel P _ N, since the buffer 240 uses a bias current having a relatively low intensity for pixels close to the buffer 240, the total power consumption of the buffer 240 can be reduced.

Fig. 6 illustrates a plurality of pixels connected to one data line, and power consumption due to bias currents corresponding to the respective pixels. The buffer may output data voltages corresponding to respective pixels using bias currents having different intensities based on positions of the respective pixels in the data line. In this way, the buffer 240 may consume less power when driving pixels near the source driver and more power when driving pixels far from the source driver.

For example, the power consumed by the buffer 240 due to the bias current for driving the plurality of pixels P _1, P _2, …, P _ N-1, P _ N may be different according to the positions of the pixels. Preferably, the power consumed by the buffer 240 may be increased as the pixels to be driven are farther from the buffer 240. The buffer 240 may consume the minimum power when driving the first pixel P _1 located at the nearest position to the buffer 240 and consume the maximum power when driving the nth pixel P _ N located at the farthest position from the buffer 240.

The buffer 240 consumes the first power P due to the bias current for driving the first pixel P _1₁The buffer 240 consumes the second power P due to the bias current for driving the second pixel P _2₂ Buffer 240 due to N-1 power P consumed for driving bias current of N-1 pixel_N-1And the Nth power P consumed by the buffer 240 due to the bias current for driving the Nth pixel P _ N_NMay be different from each other. Here, the first power P₁May be the lowest and Nth power P_NMay be the highest.

Total power P consumed by the buffer 240 in one data line due to the bias current_TCan be matched with the first power to the Nth power P₁、P₂、…、P_N-1、P_NThe sum of (a) and (b) is the same. In fig. 6, the total power P_TAnd first to Nth powers P₁、P₂、…、P_N-1、P_NShown as a graph with an axis of POWER (POWER) and an axis of DISTANCE relative to the buffer 240 (DISTANCE).

As in FIG. 4, the use of a phase in the buffer 240When the same strength of bias currents are used to output the data voltages for the plurality of pixels P _1, P _2, …, P _ N-1, and P _ N, the power consumed by the buffer 240 due to the bias currents may increase. Total power P when using bias currents of the same strength_TA rectangular shape may be represented.

In contrast, when the buffer 240 uses differently adjusted bias currents to output data voltages for a plurality of pixels P _1, P _2, …, P _ N-1, P _ N as in fig. 6, the power consumed by the buffer 240 due to these bias currents may be reduced. Total power P when using a bias current with increasing intensity based on the position of the pixel_TA right triangle can be represented. When comparing the areas of the rectangles and the right triangles, it can be noted that the total power P_TMay be reduced to about 1/2.

Referring to fig. 7, each of buffers 740-1 to 740-4 of a source driver may output a data voltage to a plurality of pixels connected to one data line using a bias current. Here, the buffers 740-1 to 740-4 may divide a plurality of pixels into groups and use different bias currents for the respective groups. In order to output data voltages for a plurality of pixels included in one group, each of the buffers 740-1 to 740-4 may use bias currents having the same strength. Also in this method, the buffers 740-1 to 740-4 may receive bias currents corresponding to the respective pixels from the bias control circuit and output data voltages to the respective pixels using the bias currents. Hereinafter, an example in which each of the four buffers 740-1 to 740-4 drives ten pixels connected to one of the four data lines DL _1 to DL _4 is explained.

Here, a region including one data line and a plurality of pixels connected to the one data line may be referred to as a channel. The channel may also include a buffer responsible for the one data line. In the figure, P may indicate a pixel, and CH1 to CH4 may indicate respective channels.

Each of the plurality of pixels may be located near or far from one of the buffers. A pixel being close to one buffer may mean that the distance of the pixel with respect to one buffer is short, while a pixel being far from one buffer may mean that the distance of the pixel with respect to one buffer is long. As a pixel becomes closer to one buffer, delay due to a resistance element and a capacitance element becomes shorter, and a slew rate of a data voltage output to the pixel becomes relatively higher. In contrast, as a pixel becomes farther from one buffer, delay due to a resistance element and a capacitance element becomes long, and the slew rate of a data voltage output to the pixel becomes relatively low. In the figure, the point closest to one buffer is indicated by NEAR (NEAR) and the point farthest from one buffer is indicated by FAR (FAR).

Each of the buffers 740-1 to 740-4 may divide a plurality of pixels connected to one data line into groups and output data voltages using different bias currents for the respective groups.

For example, the first buffer 740-1 may divide ten pixels connected to the first data line DL _1 into four groups. The first buffer 740-1 may include the nearest three pixels in the first group and make the second group to the fourth group each include two pixels based on the positions of the four groups in the first data line DL _ 1. The first buffer 740-1 may use the first to fourth BIAS currents BIAS _1 to BIAS _4 to supply the data voltages to the pixels respectively included in the first to fourth groups.

Here, the first to fourth BIAS currents BIAS _1 to BIAS _4 may have different strengths. Preferably, the intensity becomes higher as the associated group is farther from the buffer. Accordingly, the strengths of the first to fourth BIAS currents BIAS _1 to BIAS _4 may be gradually increased. In the figure, the lowest intensity is indicated by WEAK (WEAK) and the highest intensity is indicated by STRONG (STRONG).

Each of the buffers 740-1 to 740-4 may use a different bias current for each group, but use a bias current having the same strength for a plurality of pixels included in one group.

For example, when the first buffer 740-1 outputs data voltages for the first group of three pixels, the first buffer 740-1 may use the first BIAS current BIAS _ 1. The three pixels in the first group may be driven with bias currents having the same intensity. Based on the positions of the three pixels or the distances of the three pixels from the buffer, the strength of the bias current for the three pixels in the first group may be lower than the bias current for the other pixels in the other groups.

Each of the second to fourth buffers 740-2 to 740-4 may divide ten pixels connected to each of the second to fourth data lines DL _2 to DL _4, like the first buffer 740-1. Each of the second to fourth buffers 740-2 to 740-4 may output a data voltage using a bias current having a different strength for each group. Each of the second to fourth buffers 740-2 to 740-4 may use a bias current having the same intensity for a plurality of pixels included in one group.

Since a plurality of pixels connected to one data line are divided into groups and driven using bias currents having different intensities, the difference between slew rates associated with the pixels may be within a predetermined range. That is, the difference between the times of forming the data voltages for the respective pixels may be within a predetermined range.

Here, the difference between the slew rates or the difference between the data voltage formation times being within a predetermined range may mean that all the data voltages may be completely output from a time point when the pixels are connected to the data lines by the scan signal of the on voltage from the gate driver until a time point (gate off point) when the pixels are disconnected from the data lines by the scan signal of the off voltage.

On the other hand, a pixel in which the intensity of the bias current changes may be referred to as a boundary pixel. When one buffer outputs a data voltage to pixels in one data line by line, a boundary pixel may be driven by a bias current having a different intensity from that of a bias current for a previous pixel. Therefore, one boundary pixel may be included in each group. For example, the boundary pixel of the second group, which is first driven by the second BIAS current BIAS _2 in the second group, may be the fourth pixel among ten pixels in the first data line DL _ 1.

Fig. 8 illustrates a dimming phenomenon occurring when the intensity of the bias current is repeatedly changed at the same position.

In the case where the buffer of the source driver groups a plurality of pixels and bias currents having different intensities are used for the respective groups, the variation in the intensity of the bias current may be repeated at the same position, and these positions may be the positions of the boundary pixels as described above.

For example, referring to the first channel CH1, a first BIAS current BIAS _1 may be used for the first group, and then a second BIAS current BIAS _2 having a higher intensity than that of the first BIAS current BIAS _1 may be used for the boundary pixels of the second group. Subsequently, the second BIAS current BIAS _2 is used for the second group, and then, the third BIAS current BIAS _3 having a higher intensity than that of the second BIAS current BIAS _2 may be used for the boundary pixels of the third group. For the pixels of the group farthest from the buffer, the fourth BIAS current BIAS _4 may be used.

If the position of the boundary pixel where the intensity of the bias current is changed is not changed, in other words, if the position where the setting of the bias current intensity is changed is not changed, a boundary may be formed in or around the boundary pixel. In addition, if such a boundary is maintained in each frame, the boundary may form block dim. Block dims may be formed along border pixels across the panel. In the figure, the block dimming is shown as a thick solid line. Block dim is a representative case of image degradation. In addition to reducing power consumption of the source driver by maintaining the slew rate the same, there is a need to mitigate block dim.

Fig. 9 illustrates mitigation of block dim during differentially adjusting the strength of the bias current to maintain the same slew rate, in accordance with another embodiment. When the position where the setting of the bias current strength is changed in each frame, that is, when the boundary pixel is changed in each frame, block dim can be reduced.

The bias control circuit may adjust the bias current such that pixels whose intensity of the bias current changes change in each frame. The bias control circuit may generate bias currents for driving the pixels in each frame and transmit the bias currents to the buffers 940-1 to 940-4, and the buffers 940-1 to 940-4 may output data voltages to the pixels using the bias currents. Therefore, the boundary pixel in which the intensity of the bias current changes may change in each frame.

For example, referring to the figure, the bias control circuit may adjust the intensity of the bias current based on a dotted line in a first frame, and the bias control circuit may adjust the intensity of the bias current based on a solid line in a second frame.

Specifically, in the first frame, the BIAS control circuit may generate the second BIAS current BIAS _2 having a higher intensity than that of the first BIAS current BIAS _1 for the boundary pixel in the position indicated by the dotted line in the drawing, and transmit the second BIAS current BIAS _2 to the first buffer 940-1. The first buffer 940-1 may output the data voltage to the second group including the boundary pixels in the positions indicated by the dotted lines in the drawing using the second BIAS current BIAS _ 2. Subsequently, in the second frame, the BIAS control circuit may generate the second BIAS current BIAS _2 having a higher intensity than that of the first BIAS current BIAS _1 for the boundary pixels in the positions indicated by the solid lines in the drawing, and transmit the second BIAS current BIAS _2 to the first buffer 940-1. The first buffer 940-1 may output the data voltage to the second group including the boundary pixels in the positions indicated by the solid lines in the drawing using the second BIAS current BIAS _ 2.

Here, the boundary pixels may be determined randomly or according to a predetermined rule. Therefore, the position where the intensity of the bias current changes may also be changed randomly or according to a predetermined rule in each frame.

The boundary pixels of the channels adjacent to each other may be located on the same line. For example, in the second frame, the boundary pixel starting to use the second BIAS current BIAS _2 in the first channel CH1 and the boundary pixel starting to use the second BIAS current BIAS _2 in the third channel CH3 may be located on the same horizontal line. In this figure, the boundary pixels of the first channel CH1 and the boundary pixels of the third channel CH3 may be located on the same horizontal line.

The boundary pixels of the channels adjacent to each other may be located on different lines. For example, in the second frame, the boundary pixel starting to use the second BIAS current BIAS _2 in the first channel CH1 and the boundary pixel starting to use the second BIAS current BIAS _2 in the second channel CH2 may be located on different horizontal lines. In this figure, the boundary pixels of the first channel CH1 and the boundary pixels of the second channel CH2 may be located on different horizontal lines.

As described above, the positions of the boundary pixels (that is, the positions at which the settings of the bias current strengths are changed) may be different in each frame, and may also be different in the adjacent channels. When the positions of the setting changes of the bias current intensities are changed in each frame, the dimming phenomenon can be reduced as compared with the case where the positions of the setting changes are fixed.

Fig. 10 is a diagram showing that a position where a bias current is adjusted changes in each frame and the intensity of the bias current at the position also changes in each frame according to still another embodiment.

Fig. 10 illustrates further mitigation of block dim during differentially adjusting the strength of the bias current to maintain the slew rate the same, in accordance with yet another embodiment. When the position where the setting of the bias current strength is changed in each frame, that is, when the boundary pixel is changed in each frame, block dim can be reduced. Further, the intensity of the bias current may also be changed along with the change of the boundary pixels each time the boundary pixels are changed in each frame.

The bias control circuit may change the pixel in which the intensity of the bias current is changed in each frame, and may also adjust the bias current to have a different intensity in each frame. The bias control circuit may change the position of the adjustment bias current and the intensity of the bias current at the position in one channel, and also may change the position and intensity in each frame as well.

For example, the first buffer 1040-1 may change the BIAS currents BIAS _1 to BIAS _4 using some boundary pixels as change points and supply the data voltage to the first data line DL1 using the first to fourth BIAS currents BIAS _1 to BIAS _4 in the first channel CH 1. During the first to fourth FRAMEs FRAME 1(FRAME1) to FRAME 4(FRAME4), the bias current may be changed with respect to the same position (see the dotted line in the figure). However, in this case, a block dim phenomenon may occur. For this reason, according to another embodiment of the present invention, the bias current may be changed with respect to different positions (see solid lines) during the first to fourth FRAMEs FRAME1 to FRAME 4. In the first FRAME1, the bias current may be changed with respect to a position (a position closer to the first buffer 1040-1 in each bank) indicated as being slightly higher than the dotted line in the drawing. In the second FRAME2, the bias current may be changed with respect to a position represented as higher than that in the first FRAME 1. In the third FRAME3, the bias current may be changed with respect to the same position as that of the first FRAME 1. In the fourth FRAME4, the bias current may be changed with respect to a position (a position farther from the first buffer 1040-1) indicated as being lower than the dotted line.

Here, the position of one channel in which the bias current changes in one frame does not need to be the same as that in another frame. Even though the position of the first channel CH1 where the bias current in the first FRAME1 is changed is the same as that in the third FRAME3 in the above example, the position of the first channel CH1 where the bias current is changed may be different in the first to fourth FRAMEs FRAME1 to FRAME 4.

In addition, in the first to fourth FRAMEs FRAME1 to FRAME4, when the position where the bias current is changed, the intensity of the bias current may also be changed. Specifically, in the first FRAME1, the BIAS currents may vary from the first to fourth BIAS currents BIAS _1 to BIAS _4 with respect to the above-described positions, and the strengths of the first to fourth BIAS currents BIAS _1 to BIAS _4 may be 4,6,8, and 9, respectively. In the second FRAME2, the BIAS current may vary from the first to fourth BIAS currents BIAS _1 to BIAS _4 with respect to the above-described position, and the strengths of the first to fourth BIAS currents BIAS _1 to BIAS _4 may be 3,5,7, and 8, respectively. In the third FRAME3, the BIAS current may vary from the first to fourth BIAS currents BIAS _1 to BIAS _4 with respect to the above-described position, and the strengths of the first to fourth BIAS currents BIAS _1 to BIAS _4 may be 5,7,9, and 10, respectively. In the fourth FRAME4, the BIAS current may vary from the first to fourth BIAS currents BIAS _1 to BIAS _4 with respect to the above-described position, and the strengths of the first to fourth BIAS currents BIAS _1 to BIAS _4 may be 4,6,8, and 9, respectively. As described above, at the transition from the first FRAME1 to the second FRAME2, the position where the first BIAS current BIAS _1 is changed to the second BIAS current BIAS _2 becomes different, and the strengths of the first and second BIAS currents BIAS _1 and BIAS _2 are also changed from 4,6 to 3, 5.

The strengths of the first to fourth BIAS currents BIAS _1 to BIAS _4 may be variable and randomly set in each frame. However, the associated bias current needs to have a high intensity when the pixel is far from the first buffer 1040-1, and a low intensity when the pixel is close to the first buffer 1040-1. In this way, the time for forming the data voltage for a plurality of pixels in one data line can be the same. In other words, the slew rates of the plurality of pixels may be the same. This must be maintained even if the strength of the bias current changes randomly from frame to frame.

As described above, the bias control circuit can change the positions (boundary pixels) where the bias current changes in the channels, and the strength of the bias current with respect to these positions in each frame. Changing the positions at which the bias current changes and the strength of the bias current in relation to these positions in each frame enables flexible bias current control and this enables reduction of power consumption due to the bias current.

Fig. 11 illustrates another embodiment in which the BIAS control signal BIAS _ CTR-SIG may be generated by the timing controller 1114 and received by the source driver 1112.

The source driver 1112 may include a first latch circuit 1110, a second latch circuit 1120, a digital-to-analog converter DAC 1130, a buffer 1140, a bias control circuit 1150, and a drive control circuit 1160. The source driver 1112 and its subcomponents may have the same functions as the source driver (12 in fig. 2) and its subcomponents shown in fig. 2 (the first latch circuit (210 in fig. 2), the second latch circuit (220 in fig. 2), the DAC (230 in fig. 2), the buffer (240 in fig. 2), the bias control circuit (250 in fig. 2) and the drive control circuit (260 in fig. 2)). Accordingly, the BIAS control circuit 1150 may receive a BIAS control signal BIAS _ CTR _ SIG including position data of each pixel for which the BIAS current is adjusted or timing data specifying a timing for adjusting the intensity of the BIAS current.

Here, the BIAS control circuit 1150 may receive a BIAS control signal BIAS _ CTR _ SIG including strength data of the BIAS current. Referring to fig. 9, the intensity data of the bias current may include an intensity value of the bias current changed in one channel. Referring to fig. 10, the intensity data of the bias current may include an intensity value of the bias current that changes in one channel and in each frame. In the above example, the intensity data of the BIAS current may include (4,6,8,9), (3,5,7,8), (5,7,9,10), (4,6,8,9), which are intensity values of the first to fourth BIAS currents BIAS _1 to BIAS _4 in the first to fourth FRAMEs FRAME1 to FRAME 4.

Referring again to fig. 11, the timing controller 1114 may generate a BIAS control signal BIAS _ CTR _ SIG including position data, timing data, and/or intensity data of the BIAS current and transmit the BIAS control signal to the driving control circuit 1160. The drive control circuit 1160 may transmit the BIAS control signal BIAS _ CTR _ SIG to the BIAS control circuit 1150 as it is or after processing it. The BIAS control circuit 1150 may control the BIAS current of the buffer 1140 by transmitting a BIAS control signal BIAS _ CTR _ SIG to the buffer 1140.

Claims

1. A source driver, comprising:

a buffer for outputting a plurality of data voltages using a bias current to drive a plurality of pixels connected to a data line; and

a bias control circuit for adjusting the intensity of the bias current according to the position of each pixel connected to the data line,

wherein the bias control circuit determines a pixel position for which to adjust the intensity of the bias current differently in each frame, and determines the intensity of the bias current to be adjusted for the pixel of the pixel position differently in each frame.

2. The source driver of claim 1, wherein the bias control circuit receives a bias control signal including position data of a pixel for which the intensity of the bias current is adjusted and timing data specifying a timing of adjusting the intensity of the bias current.

3. The source driver of claim 2, wherein the bias control signal comprises strength data of a bias current to be adjusted.

4. The source driver of claim 3, wherein the bias control signal is generated and transmitted by a timing controller.

5. The source driver of claim 1, wherein the bias control circuit adjusts the bias current to have a first strength for a first group of pixels of the plurality of pixels and adjusts the bias current to have a second strength for a second group of pixels of the plurality of pixels in each channel.

6. The source driver of claim 5, wherein the second group of pixels is further than the first group of pixels in the data line, and the bias control circuit adjusts the second intensity to be higher than the first intensity.

7. The source driver of claim 5, wherein the second group of pixels includes a boundary pixel whose intensity of the bias current changes to the second intensity, and the bias control circuit determines the boundary pixel randomly or according to a predetermined rule, adjusts the intensity of the bias current for the boundary pixel to the second intensity in a first frame, and adjusts the intensity of the bias current for the boundary pixel to a third intensity different from the second intensity in a second frame.

8. The source driver of claim 5, wherein a difference between a time at which the data voltage is formed for the first group of pixels and a time at which the data voltage is formed for the second group of pixels is within a predetermined range.

9. The source driver of claim 7, wherein different pixels are determined as boundary pixels in each frame, and the boundary pixels respectively in adjacent channels can be located in different lines.

10. The source driver of claim 1, wherein the bias control circuit adjusts a bias current to have a highest intensity to drive a pixel farthest from the source driver and adjusts a bias current to have a lowest intensity to drive a pixel located closest to the source driver.

11. The source driver of claim 10, wherein a difference between a time at which the data voltage is formed for a pixel farthest from the source driver and a time at which the data voltage is formed for a pixel located closest to the source driver is within a predetermined range.

12. The source driver of claim 1, wherein the bias control circuit divides the plurality of pixels into a plurality of groups and adjusts the intensity of a bias current to be different for each group, wherein the bias control circuit adjusts the bias current to have the highest intensity to drive a pixel group farthest from the source driver and adjusts the bias current to have the lowest intensity to drive a pixel group located closest to the source driver.

13. The source driver of claim 12, wherein a difference between a time of forming the data voltage for the group farthest from the source driver and a time of forming the data voltage for the group located at the position closest to the source driver is within a predetermined range.

14. A source driver, comprising:

a buffer for outputting an Mth data voltage for an Mth pixel connected to a data line using an Mth bias current, outputting an Nth data voltage for an Nth pixel connected to the data line using an Nth bias current having a higher intensity than that of the Mth bias current, consuming an Mth power required for the Mth bias current, and consuming an Nth power required for the Nth bias current and greater than the Mth power, M being a natural number equal to or greater than 1, N being a natural number equal to or greater than M + 1; and

a bias control circuit for generating the Mth bias current and the Nth bias current and supplying the Mth bias current and the Nth bias current to the buffer,

wherein the bias control circuit determines different pixels as the Mth pixel and the Nth pixel in each frame, and determines the Mth bias current and the Nth bias current as different in each frame.

15. The source driver of claim 14, wherein the buffer operates in a first mode in which the buffer outputs the mth data voltage using the mth bias current and outputs the nth data voltage using the nth bias current, or in a second mode in which the buffer outputs the mth data voltage and the M +1 th data voltage using bias currents having the same strength.

16. The source driver of claim 14, wherein the bias control circuit generates the Mth bias current for an Mth group of pixels including the Mth pixel and generates the Nth bias current for an Nth group of pixels including the Nth pixel.