CN114204920B - Signal processing circuit - Google Patents
Signal processing circuit Download PDFInfo
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- CN114204920B CN114204920B CN202010910031.6A CN202010910031A CN114204920B CN 114204920 B CN114204920 B CN 114204920B CN 202010910031 A CN202010910031 A CN 202010910031A CN 114204920 B CN114204920 B CN 114204920B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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Abstract
The invention relates to the technical field of integrated circuits, and provides a signal processing circuit which is provided with a first input port, a first output port and a second output port which are connected with an external circuit, wherein the signal processing circuit is connected with an input signal from the first input port through a detection module, and sequentially generates control signals according to the amplitude change of the input signal in a plurality of sampling times before the current sampling time and the comparison result of preset reference voltage under the control of a sampling clock signal; and the control signal is subjected to edge extraction by utilizing an output module connected with the output end of the detection module, the edge extraction result of the control signal is respectively corrected according to preset reference voltage under the control of a sampling clock signal, and the generated output signal is sent out through a second output port. Therefore, the interference problem in signal detection can be effectively solved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a signal processing circuit for coherent detection.
Background
The random signal is characterized by a large difference between autocorrelation and cross-correlation, i.e., there is no similarity between the random signals of two different time slices. A pseudo-random code is an artificially constructed chip that has a low overlap with other chips and chips of the same pseudo-random code that are not time-aligned. By multiplying the pseudo-random code with the signal to be detected, which comprises one and the same pseudo-random code and comprises a large amount of interference, the largest product area (inner product), i.e. the integration of the product value within the chip duration, is obtained when the two pseudo-random signals are perfectly aligned. In other cases, the product area is small because the positive and negative distribution of the random signal is uniform. The property that these two product integrals show a large difference provides a way to extract the signal submerged in the disturbance under high disturbance conditions, i.e. coherent detection of the pseudo-random signal.
The pseudorandom code sequence may generally be generated using a shift register network. The random numbers and random codes adopted in computer and communication systems are both pseudo-random numbers and pseudo-random codes. The "random code" is a phenomenon that no cycle occurs regardless of the length of the code, and a "pseudo random code" cycles from its first bit when the code length reaches a certain level.
At present, the anti-interference capability of the signal is improved by adopting pseudorandom code transmission and reception in personal communication equipment and GPS positioning application. Because it is difficult to hold voltage or current for long periods of time with analog circuits, schemes that do coherent processing on pseudorandom signals typically require the signal to be sampled, quantized, and stored first, and then coherently detect the samples over the chip duration in the digital domain. In quantizing a sampled signal, the quantizer resolution needs to be able to resolve the signal variations within the allowable range of interference. For example, if the signal is 20mV and the range after adding the disturbance is 2V, the quantizer needs to see that a change of 20mV needs the ability to quantize 2V to a subdivision of 20mV, i.e. at least to a voltage step of 1/100 of 2V. Coherent calculations are then performed on the sample sequence subdivided by more than 100.
This solution, which is well-established in both product technology and commercial applications, can greatly improve signal-to-noise ratio and provide high-precision timing, but has the problem that it is not suitable for applications with strict requirements on size and power consumption and low overhead budget. If a filter and an amplitude discriminator are used, the small amplitude effective signal is drowned out or disturbed so that the filter is blocked, because the improvement of the filter on the pulse signal is limited.
Therefore, the effective scheme of using pseudo-random code to carry out coherent detection in a circuit system in the prior art is too huge and is not suitable for a small system, and the performance of the simple scheme is insufficient.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a signal processing circuit, which can effectively solve the interference problem in signal detection.
According to the present invention, there is provided a signal processing circuit having a first input port, a first output port, and a second output port to which an external circuit is connected, the signal processing circuit comprising:
the detection module is used for accessing an input signal from the first input port and sequentially generating a control signal according to the amplitude change of the input signal in a plurality of sampling times before the current sampling time and the comparison result of the preset reference voltage under the control of a sampling clock signal;
and the output module is connected with the output end of the detection module, carries out edge extraction on the control signal, respectively corrects the edge extraction result of the control signal according to a preset reference voltage under the control of the sampling clock signal, and sends out the generated output signal through the second output port.
Preferably, the signal processing circuit is connected to an input circuit, and the input circuit is connected between the signal receiving terminal and the first input port, and is configured to transmit the input signal received by the signal receiving terminal to the detection module.
Preferably, the input circuit includes a first resistor and a first capacitor connected in series between a signal receiving terminal and the first input port.
Preferably, a sampling time control circuit configured to supply the sampling clock signal specifying the sampling time sequence is further connected to the signal processing circuit.
Preferably, the aforementioned detection module comprises:
an amplifier having an input terminal connected to the first input port and an output terminal connected to the first output port, the amplifier being configured to amplify and output the input signal, and a parasitic capacitance being present between the first input port and the first output port;
the inverting input end of the comparator is connected with the output end of the amplifier, the non-inverting input end of the comparator is connected with the preset reference voltage through the second resistor to obtain a comparison threshold value of the comparator, and the output end of the comparator is connected with the output module;
a switch element connected between the first input port and the second resistor, the control terminal being connected to the sampling clock signal, a connection node between the switch element and the second resistor being connected to the predetermined reference voltage,
the detection module changes the comparison threshold of the comparator in the current sampling time according to the control signal generated in a plurality of sampling times before the current sampling time.
Preferably, the output module comprises:
the shift register is connected to the sampling clock signal, connected between the output end of the comparator and the second output port and connected to the non-inverting input end of the comparator through a third resistor, and is used for storing results of sampling for several times in several sampling times before the current sampling time;
a correction unit, the input end of which is connected with the non-inverting input end of the comparator through a fourth resistor, the output end of which is connected with the shift register,
the correction unit resets a register according to the aforementioned preset reference voltage and a result of a plurality of samplings in an earlier sampling time to adjust a comparison threshold of the comparator.
Preferably, the shift register includes:
a plurality of registers connected in sequence, the clock end of each register is connected with the sampling clock signal, the data end of the first register is connected with the output end of the comparator, and the output end of the first register is connected to the non-inverting input end of the comparator through the third resistor,
the reset ends of the subsequent registers are connected with the correction unit, and the output ends of the registers are used as the second output ports together to provide the output signals.
Preferably, the comparison threshold of the comparator at the current sampling time is related to the output signal of the first register at the preset reference voltage and the sampling time before the current sampling time.
Preferably, if the input signal is detected to be greater than the preset reference voltage in a sampling time before the current sampling time, determining that the comparison threshold of the comparator is a first comparison threshold at the current sampling time according to the high state of the output signal of the first register,
the first comparison threshold is greater than the predetermined reference voltage.
Preferably, if the input signal is detected to be less than or equal to the preset reference voltage in a sampling time before the current sampling time, determining that the comparison threshold of the comparator is a second comparison threshold at the current sampling time according to the output signal of the first register being in a low level state,
the second comparison threshold is smaller than the preset reference voltage.
The invention has the beneficial effects that: the invention provides a signal processing circuit, which is provided with a first input port, a first output port and a second output port which are connected with an external circuit, wherein the signal processing circuit accesses an input signal from the first input port through a detection module, and sequentially generates control signals according to the amplitude change of the input signal in a plurality of sampling times before the current sampling time and the comparison result of preset reference voltage under the control of a sampling clock signal; and the output module connected with the output end of the detection module is used for carrying out edge extraction on the control signal, under the control of a sampling clock signal, the edge extraction result of the control signal is respectively corrected according to the preset reference voltage, and the generated output signal is sent out through a second output port. Compared with the scheme in the prior art, the circuit simplifies an increase and decrease quantity discrimination circuit (the logic design of pulse detection) for voltage induction, improves the anti-blocking capability of the circuit by periodically resetting the voltage on the capacitor with the input function, and has higher integration level and low power consumption.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic block diagram of a signal processing circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram showing a detailed circuit configuration of the signal processing circuit of fig. 1;
fig. 3 shows a timing diagram of a sampling clock signal in the signal processing circuit of fig. 2.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
In communication applications, signals can be processed in a variety of different domains, the diversity of which covers the possibility of continuous and discrete nature of the time and amplitude axes. For example, the signal may be processed entirely in the following domains:
continuous-time and continuous-amplitude domains, which are often referred to as the analog domain in engineering.
Discrete-time and continuous-amplitude domains, which are commonly referred to as sampled-data domains. Here, the implementation techniques of switched capacitors, switched currents, charge coupled devices, etc. are generally applied.
Discrete-time and discrete-amplitude domains, which are commonly referred to as the digital domain.
Of course other domains like the sigma-delta domain (applied in high precision analog to digital converters) are possible, however this may be considered secondary to the following description. The signals in these domains can be represented in time as well as frequency space, connected by a pair of fourier transforms. In this case concepts like aliasing, imaging, nyquist rate etc. will appear.
The signal may be converted between the domains by interface blocks such as samplers (which discretize time), quantizers (which discretize amplitude), hold circuits (which create a continuous-time signal from a discrete-time signal), analog filters (which create or interpolate a discrete-amplitude signal to create a continuous-amplitude signal), and the like. All these interface blocks can be implemented in various forms and all correspond to a specific and well-defined signal transformation in time and frequency space. Furthermore, in the case of discrete amplitude or continuous amplitude, the signal may be processed by an interpolator or decimator in the time discrete domain.
Typically, the sampling circuit and the holding circuit operate at a fixed frequency, i.e. they are assumed to discretize or generate continuous-time signals at well-defined and constant time intervals, one of the benefits of which, for example, makes the mathematical operation of the subsequent conversion generally very simple.
When constant time intervals are not used, the signal may be distorted or, more commonly, noise will be added to the signal. However, noise is typically only correlated when sharing the same frequency band as the signal to be processed, or when its amplitude and temporal position are unknown in the time domain. If its amplitude and temporal position are known, the errors can be post-subtracted or pre-corrected, in particular if the exact time is known, an estimation procedure can be applied to remove noise in the signal.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic block diagram of a signal processing circuit according to an embodiment of the present invention, and fig. 2 shows a specific circuit structure diagram of the signal processing circuit in fig. 1.
Referring to fig. 1 and 2, an embodiment of the present invention provides a signal processing circuit 100 having a first input port a, a first output port B, and a second output port to which an external circuit is connected, the signal processing circuit 100 including: the detection module 110 accesses an input signal Vin from a first input port A, and sequentially generates a control signal VC according to the comparison result of the amplitude change of the input signal Vin and a preset reference voltage Vref in several sampling times before the current sampling time under the control of a sampling clock signal CLK; the output module 120 is connected to the output end of the detection module 110, and is configured to perform edge extraction on the control signal VC, and under the control of the sampling clock signal CLK, modify the edge extraction result of the control signal VC according to a preset reference voltage Vref, and send out a generated output signal Vout through the second output port, where the output signal Vout may be used to extract an effective amplitude variation of the input signal Vin in coherent detection, for example.
Further, the signal processing circuit 100 is connected with an input circuit 200 and a sampling time control circuit 300, wherein the input circuit 200 is connected between a signal receiving terminal and a first input port a for transmitting an input signal Vin received by the signal receiving terminal to the detection module 110 through the first input port a, and the sampling time control circuit 300 is configured to provide the sampling clock signal CLK for specifying a sampling time sequence.
Specifically, the input circuit 200 includes a resistor R1 and a capacitor C1 connected in series between the signal receiving terminal and the first input port a. And the sample time control circuit 300 may be capable of independently assigning sample times (e.g., with some variation from a predetermined sampling grid), for example, to allow for spreading interference, or to frequency sample times, so that the detection module 110 processes the sampled signal values in view of the sample times. In this embodiment, the sampling clock signal CLK is a periodic signal with a constant frequency.
It will be appreciated that the sample time control circuit 300 may be implemented, for example, by one or more circuits. A "circuit" may be understood as any kind of logic implementing entity, which may be a dedicated circuit or a processor executing software stored in a memory, firmware, or any combination thereof. For example a processor such as a DSP (digital signal processor). Thus, a "circuit" may be a hardwired logic circuit or a programmable logic circuit such as a programmable processor, e.g., a microprocessor. The "circuitry" may also be a processor executing software, e.g. any kind of computer program. Any other type of implementation of the respective functions, which will be described in more detail below, may also be understood as a "circuit".
It should be further noted that the resistor R1 and the capacitor C1 in the input circuit 200 may be a definite circuit structure, or may be equivalent devices formed by direct interaction between a signal source and a receiving circuit in a capacitively coupled transceiver system.
Further, the detection module 110 includes: the amplifier 111, the comparator 112, the switching element SW1 and the resistor R2, specifically, an input end of the amplifier 111 is connected to the first input port a, an output end of the amplifier 111 is connected to the first output port B, the amplifier 111 is configured to amplify and output an input signal Vin, and a parasitic capacitor Cab exists between the first input port a and the first output port B; the inverting input end of the comparator 112 is connected to the output end of the amplifier 111, the non-inverting input end is connected to a preset reference voltage Vref through a resistor R2 to obtain a comparison threshold Vth of the comparator 112, and the output end of the comparator 112 is connected to the output module 120; the switch device SW1 is connected between the first input port a and the resistor R2, the control terminal is connected to the sampling clock signal CLK, the connection node between the switch device SW1 and the resistor R2 is used to connect to the preset reference voltage Vref, and the detection module 110 changes the comparison threshold Vth of the comparator 112 in the current sampling time according to the control signal VC generated several times before the current sampling time. In practical applications, the output of the amplifier 111 can be used for eliminating polarization voltage in electrocardio measurement, for example.
Referring to fig. 3, in operation, when the switching element SW1 is turned on at the on-time t1 of the sampling clock signal CLK, the charge-voltage on the source coupling capacitor C1 at the first input port a and the parasitic capacitor Cab between the first input port a and the first output port B is balanced to a level consistent with the internal preset reference voltage Vref. After that, the switching element SW1 is turned off at the off time t2 of the sampling clock signal CLK, the amplifier 111 starts outputting, and then the potential of the first output port B will follow the coupled input signal Vin at the first input port a from Vref.
In the present embodiment, the amplifier 111 is an analog signal amplifier with a gain of 1, and the switching element SW1 may be, but is not limited to, one of a relay or a switch tube.
Further, the output module 120 includes: the shift register 121, the correcting unit 122, the resistor R3, and the resistor R4, wherein the shift register 121 receives a sampling clock signal CLK, is connected between the output end of the comparator 112 and the second output port, and is connected to the non-inverting input end of the comparator 112 through the resistor R3; the input terminal of the correcting unit 122 is connected to the non-inverting input terminal of the comparator 112 through a resistor R4, the output terminal is connected to the shift register 121, the shift register 121 is used for storing results of several times of sampling in several times before the current sampling time, and the correcting unit 122 resets the register according to the preset reference voltage Vref and results of multiple times of sampling quantization in earlier sampling time to adjust the comparison threshold Vth of the comparator 112.
Specifically, the shift register 120 includes, for example, a plurality of sequentially connected registers (Q1, Q2, Q3 to Qn), a clock terminal of each register is connected to the sampling clock signal CLK, a data terminal of a first register Q1 is connected to the output terminal of the comparator 112, an output terminal of the first register Q1 is connected to the non-inverting input terminal of the comparator 112 through a resistor R3, reset terminals of subsequent registers (Q2, Q3 to Qn) are connected to the correcting unit 122, and output terminals of the plurality of registers (Q1, Q2, Q3 to Qn) are used as a second output port together to provide the output signal Vout. Of course, the circuit principle and the connection structure of the shift register 120 are common knowledge and will not be described herein.
Here, the output signal Vg of the register Q1 is the latest (previous to the current sampling time) sampling quantization result, and the registers Q2 to Qn are n-time quantization results earlier. The output signal Vg of the register Q1 is used to adjust the comparison threshold Vth of the comparator 112 when an incremental change is detected at the current sampling time, which is favorable for waiting for an expected decrement change of the input signal Vin; the correcting unit 122 is used for increasing or decreasing the output to change the comparison threshold Vth of the comparator 112 when the results of the registers Q2 to Qn show that the increase or decrease is not small or large.
In the signal processing circuit 100 of the embodiment of the present invention, if the shortest duration of the expected input signal (taking a pulse signal as an example) is T, sampling the input signal with an interval of T/3, as shown in fig. 3, can ensure that the amplitude variation before and after the pulse edge is observed between two sampling points. With longer intervals the peak of the shortest pulse may be missed, while with shorter intervals more sequential samples may need to be observed to observe and judge the amplitude variation of the intended pulse because both samples do not observe sufficient amplitude variation during the pulse leading edge variation. The use of shorter sub-divisions also means more divisions of amplitude, i.e. high resolution analog to digital converters (ADCs) and high speed sampling schemes that are currently widely used, in the direction that the present invention seeks to improve.
With reference to fig. 2 and fig. 3, in a sampling time period T/3, the on-time is T1, the off-time is T2, and the shift register 121 (Q1, Q2, Q3 to Qn) is triggered at the leading edge of the pulse to complete sampling of the control signal VC output by the comparator 112 and shift the acquired state sequence by taking the sampling time period T/3 as a period time; meanwhile, a preset reference voltage Vref is transmitted to the first input port A within the on-time of t1, so that the level of the input signal Vin is forced to the preset reference voltage Vref, and the difference between the sensed level and the preset reference voltage Vref is transferred to the capacitor C1 with a time constant of τ = R1 × C1. Furthermore, the capacitance value of the integrating capacitor C1 can be changed to change the integrating time constant, so that the sampling detection precision is improved.
Further, the preset reference voltage Vref is half of the output amplitude of the shift register 121. In the present embodiment, at the current sampling time, the comparison threshold Vth of the comparator 112 is related to the preset reference voltage Vref and the output signal Vg of the first register Q1 in the previous sampling time. That is, the level change of the output signal Vg of the first register Q1 in the shift register 121 and the voltage division of the preset reference voltage Vref at the resistor R2 and the resistor R3 respectively determine the comparison threshold Vth of the comparator 112.
In this embodiment, the input signal Vin of the first input port a is output to the first output port B through the amplifier 111, and the relationship achieved by the output signal Vg of the first register Q1 is as follows:
if the level of the input signal Vin is detected to be less than or equal to the preset reference voltage Vref at the previous sampling time, determining that the comparison threshold Vth of the comparator 112 at the current sampling time is a second comparison threshold according to the low level state of the output signal Vg of the first register Q1:
at this time, the second comparison threshold Vth2 is smaller than the preset reference voltage Vref. The comparator 112 is used to discriminate the amplitude variation of the input signal Vin, i.e. the state that the first output port B (the level of the input signal Vin) is higher than the preset reference voltage Vref, and wait for a decrement if an increment is discriminated. If the decrement is not detected after the increment is detected, and since the comparison threshold Vth has been lowered to the second comparison threshold Vth2, which is lower than the preset reference voltage Vref, the control signal VC output by the comparator 112 will always output a state (high state) in which the increment is detected until the decrement is detected, and vice versa.
Similarly, if it is detected at the previous sampling time that the level of the input signal Vin is greater than the preset reference voltage Vref, the comparison threshold Vth of the comparator 112 at the current sampling time is determined to be a first comparison threshold according to the output signal Vg of the first register Q1 being in a high level state:
at this time, the first comparison threshold Vth1 is greater than the preset reference voltage Vref. The comparator 112 is used to discriminate the amplitude variation of the input signal Vin, i.e. the state that the first output port B (the level of the input signal Vin) is higher than the preset reference voltage Vref, and if the level of the input signal Vin is discriminated to be over-decreased, the increment is waited to occur. If the decrement is detected and the comparison threshold Vth is already raised to the first comparison threshold Vth1, which is higher than the preset reference voltage Vref, the control signal VC output by the comparator 112 will output the decrement-detected state (low state) until the increment is detected.
If the induced voltages are organized into V by sampling time 0 ，V -1 ，……，V -m Wherein 0 is the present, -1, \8230;, -m is the future level, the ith sample is the difference between the voltage of the first output port B (the level of the input signal Vin) and the preset reference voltage Vref, i.e., the voltage variation value between two samples; front V i-1 The value of-Vref has fallen on the capacitance C1. That is, the circuit of the comparator 112 and the amplifier 111 is not affected by the sampling voltage Vi with respect to the power supply voltage, and the voltage on the capacitor C1 with the input function is periodically reset to improve the anti-blocking capability of the circuit, thereby avoiding the situation that the amplitude of the sampling voltage Vi is too large and the circuit is blockedResulting in blockage.
In the signal processing circuit provided by the embodiment of the invention, the detection module is provided with an increment comparator which works in discrete time and is used for adjusting the comparison threshold value Vth of the detection amplitude according to the latest sampling state so as to follow the amplitude change of the input signal; when the output module is in a state of having a specific amplitude signal for a long time, the output module can eliminate the influence caused by the accumulated signal through the reset of the shift register circuit, and reset the input signal Vin of the first input port A to a state of waiting for a signal.
The signal processing circuit provided by the embodiment of the invention can judge whether no signal is in report reduction or increase for a long time according to whether the level change which appears first from no signal to the starting signal is increased or decreased. If no signal corresponds to the report decreasing, the output is abnormally increased for a long time; when the circuit is in the state of reporting increase due to interference, the continuous reporting increase can be maintained for a long time if no decrease is detected, and the circuit needs to be reset to a waiting state, namely a state of reporting decrease by a correction unit, so that the detection precision of the amplitude change of the input signal is improved.
The threshold level and reset are determined according to the design of the specific application, such as the maximum duration code length of the pseudo-random code for maintaining a specific state, and whether a return-to-zero or non-return-to-zero code is used.
The signal processing circuit provided by the embodiment of the invention utilizes the working mode that the input level is transferred to the external capacitor at a specific time before sampling, so that the subsequent circuit only processes the increment (or decrement) after processing, and simplifies the increment and decrement discrimination circuit (the logic design of pulse detection) for voltage induction;
meanwhile, the circuit utilizes the design of the historical sampling state before the current sampling time to adjust the comparison threshold used by the current sampling time, namely, the comparison threshold is adjusted to be lowered (or increased) when the expected change does not appear, and the circuit can adjust the state to wait for the opposite change from the detection change of the previous sampling time, greatly improve the signal-to-noise ratio and provide high-precision timing.
Further, in the signal processing circuit provided in the embodiment of the present invention, the shift register 121 and the sampling time control circuit 300 are both part of the coherent detection circuit, and do not need to be separately configured.
In the signal processing circuit provided by the embodiment of the invention, the signal processing circuit accesses an input signal from a first input port through a detection module, and sequentially generates a control signal according to the amplitude change of the input signal in a plurality of sampling times before the current sampling time and the comparison result of a preset reference voltage under the control of a sampling clock signal; the control signal is subjected to edge extraction by utilizing the output module connected with the output end of the detection module, under the control of a sampling clock signal, the edge extraction result of the control signal is respectively corrected according to a preset reference voltage, and the generated output signal is sent out through the second output port, so that the interference problem in signal detection is solved, coherent detection of pseudo-random codes in a small system is effectively utilized, the interference problem in signal detection is solved, and the applicability of the circuit is improved.
Compared with the scheme in the prior art, the circuit simplifies an increase and decrease discrimination circuit (the logic design of pulse detection) for voltage induction, and has higher integration level and low power consumption.
It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (8)
1. A signal processing circuit having a first input port to which an external input circuit for supplying an input signal received by a signal receiving terminal is connected, and a first output port and a second output port, wherein the signal processing circuit comprises:
the detection module is used for accessing the input signal from the first input port and sequentially generating control signals according to the amplitude change of the input signal in several sampling times before the current sampling time and the comparison result of preset reference voltage under the control of a sampling clock signal;
an output module, connected to the output end of the detection module, for performing edge extraction on the control signal, respectively correcting the edge extraction result of the control signal according to the preset reference voltage under the control of the sampling clock signal, and sending out the generated output signal through the second output port,
wherein the detection module comprises:
an amplifier, an input end of which is connected with the first input port, an output end of which is connected with the first output port, the amplifier is used for amplifying and outputting the input signal, and a parasitic capacitance exists between the first input port and the first output port;
the inverting input end of the comparator is connected with the output end of the amplifier, the non-inverting input end of the comparator is connected with the preset reference voltage through a second resistor to obtain a comparison threshold value of the comparator, and the output end of the comparator is connected with the output module;
a switch element connected between the first input port and the second resistor, a control terminal connected to the sampling clock signal, and a connection node between the switch element and the second resistor for connecting to the preset reference voltage,
the detection module changes the comparison threshold of the comparator in the current sampling time according to the control signal generated in the sampling time before the current sampling time.
2. The signal processing circuit of claim 1, wherein the input circuit comprises a first resistor and a first capacitor connected in series between the signal receiving terminal and the first input port.
3. The signal processing circuit of claim 1, wherein the signal processing circuit is further coupled to a sample time control circuit configured to provide the sampling clock signal specifying a sequence of sample times.
4. The signal processing circuit of claim 1, wherein the output module comprises:
the shift register is connected to the sampling clock signal, connected between the output end of the comparator and the second output port, and connected to the non-inverting input end of the comparator through a third resistor, and is used for storing results of sampling and quantization for several times in several sampling times before the current sampling time;
a correction unit, the input end of which is connected with the non-inverting input end of the comparator through a fourth resistor, the output end of which is connected with the shift register,
the correction unit resets a register according to the preset reference voltage and a result of a plurality of times of sampling in an earlier sampling time to adjust a comparison threshold of the comparator.
5. The signal processing circuit of claim 4, wherein the shift register comprises:
a plurality of registers which are connected in sequence, the clock end of each register is connected with the sampling clock signal, the data end of the first register is connected with the output end of the comparator, and the output end of the first register is connected to the non-inverting input end of the comparator through the third resistor,
the reset ends of the subsequent registers are connected with the correction unit, and the output ends of the registers are used as the second output port together to provide the output signals.
6. The signal processing circuit of claim 5, wherein the comparison threshold of the comparator at the current sampling time is related to the preset reference voltage and the output signal of the leading register at the sampling time prior to the current sampling time.
7. The signal processing circuit of claim 6, wherein if it is detected that the input signal is greater than the preset reference voltage in a sampling time before a current sampling time, it is determined that the comparison threshold of the comparator is a first comparison threshold at the current sampling time according to the output signal of the leading register being in a high state,
the first comparison threshold is greater than the preset reference voltage.
8. The signal processing circuit of claim 6, wherein if it is detected that the input signal is less than or equal to the preset reference voltage in a sampling time before a current sampling time, it is determined that the comparison threshold of the comparator is a second comparison threshold at the current sampling time according to the output signal of the leading register being in a low state,
the second comparison threshold is smaller than the preset reference voltage.
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