CN114203784A - Display substrate and display device - Google Patents

Display substrate and display device Download PDF

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Publication number
CN114203784A
CN114203784A CN202111498970.5A CN202111498970A CN114203784A CN 114203784 A CN114203784 A CN 114203784A CN 202111498970 A CN202111498970 A CN 202111498970A CN 114203784 A CN114203784 A CN 114203784A
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power supply
metal layer
sub
substrate
display substrate
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董甜
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

A display substrate and a display device, wherein the display substrate includes: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a storage capacitor; the display substrate includes: the semiconductor layer, the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are sequentially stacked on the substrate; a power line; the power cord includes: at least one sub-power line connected with each other, the sub-power line is connected with the sub-pixel and is located in the area where the sub-pixel is located, and the at least one sub-power line at least comprises three power parts: a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply part is connected with the first power supply part and the third power supply part; the data line is arranged in parallel with the extending direction of the first power supply part and the third power supply part.

Description

Display substrate and display device
The application is a divisional application of application with application date of 2019, 11, 7 and application number of 201911082352.5, and the invention name of 'a display substrate, a manufacturing method thereof and a display device'.
Technical Field
The present disclosure relates to display technologies, and in particular, to a display substrate and a display device.
Background
An Organic Light-Emitting diode (OLED) Display substrate is a Display substrate different from a conventional Liquid Crystal Display (LCD), and has the advantages of active Light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-lightness and thinness, low cost, and the like. And thus has become one of the important developments of the new generation of display devices and receives increasing attention.
In order to realize high-frequency driving of the OLED display substrate, a dual-data-line OLED display substrate is proposed in the related art, that is, the same column of pixels is connected to two data lines. However, although the OLED display substrate in the related art can realize high-frequency driving, the resolution is generally low, and the market demand for high resolution of the display device cannot be met.
Disclosure of Invention
The application provides a display substrate and a display device, which can improve the resolution ratio of an OLED display substrate.
In a first aspect, the present disclosure provides a display substrate comprising: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a storage capacitor; the storage capacitor includes: the first electrode and the second electrode that set up relatively, the display substrates includes: the semiconductor device comprises a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked on the substrate;
the semiconductor layer includes: an active layer of transistors in at least one driver circuit;
the first metal layer includes: a first electrode of a storage capacitor;
the second metal layer includes: a second electrode of the storage capacitor;
a power line; the power cord includes: at least one sub-power line connected with each other, the sub-power line is connected with the sub-pixel and is located in the area where the sub-pixel is located, and the at least one sub-power line at least comprises three power parts: a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply part is connected with the first power supply part and the third power supply part; the data line is arranged in parallel with the extending direction of the first power supply part and the third power supply part.
In some possible implementations, the data line is located at the fourth metal layer.
In some possible implementations, for at least one of the driving circuits, the second electrode of the storage capacitor is set to a write power supply signal, which is a signal of the sub power supply line.
In some possible implementations, the display substrate further includes: a fourth insulating layer and a fifth insulating layer, the fourth insulating layer being disposed between the third metal layer and the fourth metal layer, the fifth insulating layer being disposed on a side of the fourth metal layer away from the substrate, the fourth metal layer further including: connecting the electrodes;
the fifth insulating layer is provided with a through hole exposing the connecting electrode, and the fourth insulating layer is provided with a through hole exposing the third metal layer; and the orthographic projection of the via hole exposing the third metal layer on the substrate is at least partially overlapped with the orthographic projection of the connecting electrode on the substrate.
In some possible implementations, an extending direction of the connection electrode is disposed in parallel with an extending direction of the first power supply part.
In some possible implementations, an extending direction of the via exposing the third metal layer and the dummy connection line of the via exposing the connection electrode is parallel to an extending direction of the data line.
In some possible implementations, an orthographic projection of the via exposing the connection electrode on the substrate at least partially overlaps with an orthographic projection of the via exposing the third metal layer on the substrate.
In some possible implementations, the virtual extension line of the first power supply part passes through the via hole exposing the connection electrode.
In some possible implementations, the virtual extension line of the first power supply portion passes through the via exposing the third metal layer.
In some possible implementations, the display substrate further includes: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer being disposed between a third metal layer and a semiconductor layer, the fourth insulating layer being disposed between a third metal layer and a fourth metal layer;
the fourth insulating layer is provided with a via hole exposing the third metal layer, the data line is connected with the third metal layer through the via hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.
In some possible implementations, an orthographic projection of the via exposing the third metal layer on the substrate at least partially overlaps with an orthographic projection of the via exposing the semiconductor layer on the substrate.
In some possible implementations, the virtual extension line of the third power supply part passes through the via hole exposing the semiconductor layer.
In some possible implementations, the virtual extension line of the third power supply portion passes through the via hole exposing the third metal layer.
In some possible implementations, an included angle between the first power supply part and the second power supply part is greater than or equal to 90 degrees and less than 180 degrees;
the included angle between the second power supply part and the third power supply part is larger than or equal to 90 degrees and smaller than 180 degrees.
In some possible implementations, an average width of the first power supply section is greater than or equal to an average width of the second power supply section;
the average width of the second power supply part is greater than or equal to the average width of the third power supply part;
the average width of the third power supply part is greater than or equal to the average width of the data lines.
In some possible implementations, the active layers of adjacent sub-pixels arranged along a first direction or a second direction are mirror-symmetrical, the first direction is perpendicular to the second direction, and the second direction is an extending direction of the data line.
In some possible implementations, the driving circuit includes: a second transistor, an orthographic projection of the first power supply part on the substrate and an orthographic projection of a part of the second transistor on the substrate at least partially overlap.
In some possible implementations, the driving circuit includes: a first transistor, wherein the orthographic projection of the second power supply part on the substrate at least partially overlaps with the orthographic projection of part of the first transistor on the substrate.
In some possible implementations, an orthographic projection of the second power supply portion on the substrate at least partially overlaps with an orthographic projection of a portion of the second electrode on the substrate.
In some possible implementations, the first metal layer further includes: and the orthographic projection of the second power supply part on the substrate is at least partially overlapped with the orthographic projection of the grid line on the substrate.
In some possible implementations, an orthographic projection of the third power supply portion on the substrate at least partially overlaps with an orthographic projection of a portion of the at least one transistor on the substrate.
In some possible implementations, the driving circuit includes: and an orthographic projection of the third power supply part on the substrate is at least partially overlapped with an orthographic projection of a part of the fifth transistor on the substrate.
In some possible implementations, the driving circuit includes: and an orthographic projection of the third power supply part on the substrate is at least partially overlapped with an orthographic projection of a part of the sixth transistor on the substrate.
In a second aspect, the present disclosure also provides a display device, including: the display substrate is provided.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification, claims, and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;
FIG. 2 is a side view of a sub-pixel in a display substrate according to an embodiment of the present disclosure;
FIG. 3 is a top view of a sub-pixel in a display substrate according to an embodiment of the present disclosure;
fig. 4A is an equivalent circuit diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 4B is a timing diagram of an operation of a driving circuit according to an embodiment of the present disclosure;
FIG. 5 is a top view of a plurality of sub-pixels in a display substrate according to an embodiment of the present disclosure;
FIG. 6A is a top view of a corresponding sub-pixel according to one embodiment;
FIG. 6B is another top view of a corresponding sub-pixel according to one embodiment;
FIG. 7A is a top view of a corresponding second metal layer in accordance with one embodiment;
FIG. 7B is a top view of a corresponding third metal layer in accordance with one embodiment;
FIG. 8A is a top view of a sub-pixel according to the second embodiment;
FIG. 8B is another top view of a corresponding sub-pixel in accordance with the second embodiment;
fig. 9A is a top view of a second metal layer according to a second embodiment;
FIG. 9B is a top view of a third metal layer according to the second embodiment;
FIG. 10 is another top view of a plurality of sub-pixels in a display substrate according to an embodiment of the present disclosure;
fig. 11 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure;
fig. 12 is a first schematic view illustrating a display substrate according to an embodiment of the disclosure;
fig. 13 is a second schematic view illustrating a display substrate according to an embodiment of the disclosure;
fig. 14A is a third schematic view illustrating a display substrate according to an embodiment of the disclosure;
fig. 14B is a schematic view illustrating another third fabrication of a display substrate according to the embodiment of the present application;
fig. 15A is a fourth schematic view illustrating a display substrate according to an embodiment of the disclosure;
fig. 15B is a fourth schematic view illustrating a display substrate according to an embodiment of the disclosure;
fig. 16A is a schematic diagram illustrating a fifth fabrication of a display substrate according to an embodiment of the disclosure;
fig. 16B is a schematic view illustrating another fifth manufacturing process of the display substrate according to the embodiment of the disclosure.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Unless defined otherwise, technical or scientific terms used in the disclosure of the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
An embodiment of the present disclosure provides a display substrate, including: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a storage capacitor; the storage capacitor includes: the first electrode and the second electrode that set up relatively, the display substrates includes: the semiconductor device comprises a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked on the substrate;
the semiconductor layer includes: an active layer of transistors in at least one driver circuit;
the first metal layer includes: a first electrode of a storage capacitor;
the second metal layer includes: a second electrode of the storage capacitor;
a power line; the power cord includes: at least one sub-power line connected with each other, the sub-power line is connected with the sub-pixel and is located in the area where the sub-pixel is located, and the at least one sub-power line at least comprises three power parts: a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply part is connected with the first power supply part and the third power supply part; the data line is arranged in parallel with the extending direction of the first power supply part and the third power supply part.
In one exemplary embodiment, a data line is located at the fourth metal layer.
In an exemplary embodiment, for at least one of the driving circuits, the second electrode of the storage capacitor is set to a write power supply signal, which is a signal of the sub power supply line.
In one exemplary embodiment, the display substrate further includes: a fourth insulating layer and a fifth insulating layer, the fourth insulating layer being disposed between the third metal layer and the fourth metal layer, the fifth insulating layer being disposed on a side of the fourth metal layer away from the substrate, the fourth metal layer further including: connecting the electrodes;
the fifth insulating layer is provided with a through hole exposing the connecting electrode, and the fourth insulating layer is provided with a through hole exposing the third metal layer; and the orthographic projection of the via hole exposing the third metal layer on the substrate is at least partially overlapped with the orthographic projection of the connecting electrode on the substrate.
In one exemplary embodiment, an extending direction of the connection electrode is disposed in parallel with an extending direction of the first power supply part.
In one exemplary embodiment, an extending direction of the via hole exposing the third metal layer and the dummy connection line exposing the via hole connecting the electrodes is parallel to an extending direction of the data line.
In one exemplary embodiment, an orthographic projection of the via exposing the connection electrode on the substrate at least partially overlaps with an orthographic projection of the via exposing the third metal layer on the substrate.
In an exemplary embodiment, the virtual extension line of the first power supply part passes through the via hole exposing the connection electrode.
In an exemplary embodiment, the virtual extension line of the first power supply part passes through the via hole exposing the third metal layer.
In one exemplary embodiment, the display substrate further includes: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer being disposed between a third metal layer and a semiconductor layer, the fourth insulating layer being disposed between a third metal layer and a fourth metal layer;
the fourth insulating layer is provided with a via hole exposing the third metal layer, the data line is connected with the third metal layer through the via hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.
In one exemplary embodiment, an orthographic projection of the via exposing the third metal layer on the substrate at least partially overlaps with an orthographic projection of the via exposing the semiconductor layer on the substrate.
In one exemplary embodiment, a virtual extension line of the third power supply part passes through the via hole exposing the semiconductor layer.
In an exemplary embodiment, the virtual extension line of the third power supply portion passes through the via hole exposing the third metal layer.
In an exemplary embodiment, an angle between the first power supply part and the second power supply part is greater than or equal to 90 degrees and less than 180 degrees;
the included angle between the second power supply part and the third power supply part is larger than or equal to 90 degrees and smaller than 180 degrees.
In one exemplary embodiment, an average width of the first power supply section is greater than or equal to an average width of the second power supply section;
the average width of the second power supply part is greater than or equal to the average width of the third power supply part;
the average width of the third power supply part is greater than or equal to the average width of the data lines.
In one exemplary embodiment, the active layers of adjacent sub-pixels arranged in a first direction or a second direction, the first direction being perpendicular to the second direction, the second direction being an extending direction of the data line, are mirror-symmetrical.
In one exemplary embodiment, the driving circuit includes: a second transistor, an orthographic projection of the first power supply portion on the substrate at least partially overlaps with an orthographic projection of a portion of the second transistor on the substrate.
In one exemplary embodiment, the driving circuit includes: a first transistor, wherein the orthographic projection of the second power supply part on the substrate at least partially overlaps with the orthographic projection of part of the first transistor on the substrate.
In an exemplary embodiment, an orthographic projection of the second power supply portion on the substrate at least partially overlaps with an orthographic projection of a portion of the second electrode on the substrate.
In one exemplary embodiment, the first metal layer further includes: and the orthographic projection of the second power supply part on the substrate is at least partially overlapped with the orthographic projection of the grid line on the substrate.
In an exemplary embodiment, an orthographic projection of the third power supply portion on the substrate at least partially overlaps with an orthographic projection of a portion of the at least one transistor on the substrate.
In one exemplary embodiment, the driving circuit includes: and an orthographic projection of the third power supply part on the substrate is at least partially overlapped with an orthographic projection of a part of the fifth transistor on the substrate.
In one exemplary embodiment, the driving circuit includes: and an orthographic projection of the third power supply part on the substrate is at least partially overlapped with an orthographic projection of a part of the sixth transistor on the substrate.
Some embodiments of the present application provide a display substrate, fig. 1 is a schematic structural diagram of the display substrate provided in the embodiments of the present application, fig. 2 is a side view of one sub-pixel in the display substrate provided in the embodiments of the present application, and fig. 3 is a top view of one sub-pixel in the display substrate provided in the embodiments of the present application, as shown in fig. 1 to 3, the display substrate provided in the embodiments of the present application is provided with a gate line G, a data line D, a power line VDD, a Reset signal line Reset, a light-emitting control line EM, an initial signal line Vinit, and a plurality of sub-pixels P, each sub-pixel includes: a light emitting device and a driving circuit for driving the light emitting device to emit light, the driving circuit comprising: a plurality of transistors and storage capacitors, the display substrate including: the semiconductor device includes a substrate 10, and a semiconductor layer 20, a first metal layer 30, a second metal layer 40, a third metal layer 50, a fourth metal layer 60, and a fifth metal layer 70 which are disposed on the substrate 10 and insulated from each other.
In the present embodiment, the semiconductor layer 20 includes: a plurality of active layers of transistors, the first metal layer 30 includes: a gate line G, a light emission control line EM, a Reset signal line Reset, a first electrode C1 of a storage capacitor, and gate electrodes of a plurality of transistors, the second metal layer 40 includes: an initial signal line Vinit and a second electrode C2 of the storage capacitor; the third metal layer 50 includes: source-drain electrodes of a plurality of transistors, the fourth metal layer 60 includes: data line D and power supply line VDD, and the fifth metal layer 70 includes: an anode of the light emitting device.
Specifically, as shown in fig. 1, the display substrate in this embodiment is provided with M rows and N columns of sub-pixels, N columns of data lines D1 to DN, N columns of power lines VDD1 to VDDN, M rows of gate lines G1 to GM, M-1 rows of light emission control lines EM1 to EMM-1, a Reset signal line Reset, and an initial signal line Vinit, and further includes: a data driver for supplying data signals to the data lines, a scan driver for supplying scan signals to the gate lines, a light emission driver for supplying light emission control signals to the light emission control lines, and a timing controller for supplying driving signals to the data driver, the scan driver, and the light emission driver.
Optionally, as shown in fig. 1, the ith column of sub-pixels is connected to an ith column of data lines, and each column of data lines includes: a first sub data line DO and a second sub data line DE; the first sub data line DOi and the second sub data line DEi in the ith row of data lines are respectively positioned at two sides of the ith row of sub pixels, and all sub data lines between two adjacent rows of sub pixels are only the first sub data line or the second sub data line.
Wherein i is more than or equal to 1 and less than or equal to N, and N is the total column number of the sub-pixels.
Specifically, all data lines between two adjacent columns of sub-pixels are only first sub-data lines or second sub-data lines, that is, when a first sub-data line DOi of an ith column of data lines is located on one side of the ith column of sub-pixels close to the (i + 1) th column of sub-pixels, a first sub-data line DOi +1 of the (i + 1) th column of data lines is located on one side of the (i + 1) th column of sub-pixels close to the ith column of sub-pixels, and when a second sub-data line DEi of the ith column of data lines is located on one side of the ith column of sub-pixels close to the (i + 1) th column of sub-pixels, a second sub-data line DEi +1 of the (i + 1) th column of data lines is located on one side of the (i + 1) th column of sub-pixels close to the ith column of sub-pixels.
Alternatively, the base 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal sheet; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.
Alternatively, the material of the semiconductor layer 20 may be polysilicon or metal oxide, which is not limited in this embodiment.
Optionally, the material of the first metal layer may be a metal material such as silver, aluminum, or copper, which is not limited in this application
Optionally, the material of the second metal layer may be a metal material such as silver, aluminum, or copper, which is not limited in this embodiment.
Optionally, the material of the third metal layer may be a metal material such as silver, aluminum, or copper, which is not limited in this embodiment of the application;
optionally, the material of the fourth metal layer may be a metal material such as silver, aluminum, or copper, which is not limited in this embodiment of the application.
Optionally, the manufacturing material of the fifth metal layer may be a metal material such as silver, aluminum, or copper, which is not limited in this application.
Fig. 4A is an equivalent circuit diagram of a driving circuit provided in an embodiment of the present application, fig. 4B is an operation timing diagram of the driving circuit provided in the embodiment of the present application, and as shown in fig. 4A and fig. 4B, fig. 4A illustrates a driving circuit included in an ith column of sub-pixels and an i +1 th column of sub-pixels, the driving circuit provided in the embodiment of the present application is a 7T1C structure, the driving circuit includes first to seventh transistors T1 to T7 and a storage capacitor C, wherein the storage capacitor C includes a first electrode C1 and a second electrode C2.
Specifically, the gate electrode of the first transistor T1 is connected to the Reset signal line Reset, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, the second electrode of the first transistor T1 is connected to the first electrode C1 of the storage capacitor C, the gate electrode of the second transistor T2 is connected to the gate line G, the first electrode of the second transistor T2 is connected to the first electrode C1 of the storage capacitor C, the second electrode of the second transistor T2 is connected to the second electrode of the sixth transistor T6, the gate electrode of the third transistor T3 is connected to the first electrode C1 of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, the second electrode of the third transistor T3 is connected to the second electrode of the sixth transistor T6, the gate electrode of the fourth transistor T4 is connected to the gate line G, the first electrode of the fourth transistor T4 is connected to the data line D, and the gate electrode of the fifth transistor T5 is connected to the light emitting control line EM, a first electrode of the fifth transistor T5 is connected to the power supply line VDD, a second electrode of the fifth transistor T5 is connected to a first electrode of the third transistor T3, a gate electrode of the sixth transistor T6 is connected to the emission control line EM, a second electrode of the sixth transistor T6 is connected to the anode of the light emitting device, a gate electrode of the seventh transistor T7 is connected to the Reset signal line Reset, a first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, a second electrode of the seventh transistor T7 is connected to the anode of the light emitting device, a second electrode C2 of the storage capacitor is connected to the power supply line VDD, and a cathode of the light emitting device OLED is connected to the low-level power supply terminal VSS.
The third transistor T3 is a driving transistor, and the other transistors except the third transistor T3 are all switching transistors, and the first transistor T1 to the seventh transistor T7 provided in this embodiment may all be P-type transistors or N-type transistors, which is not limited in this embodiment of the present invention.
Specifically, taking the first transistor T1 to the seventh transistor T7 as P-type transistors as an example, the working process of the driving circuit provided by the embodiment of the present application includes:
in the first stage S1, a Reset stage, the Reset signal line Reset provides an active level, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal provided by the initial signal line Vinit initializes a signal of the second pole of the sixth transistor T6 and a signal of the first electrode C1.
In the second stage S2, the writing stage, the gate line G provides an active level, the second transistor T2 and the fourth transistor T4 are turned on, the data signal provided by the data line D is written into the first electrode of the third transistor T3, and the potentials of the gate electrode of the second transistor T2 and the second electrode signal are made to be the same, so that the third transistor T3 is turned on.
The third stage S3, a light emitting stage, where the emission control line EM provides an active level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power line VDD provides a driving current to the light emitting device OLED to drive the light emitting device to emit light.
Alternatively, as shown in fig. 4A, the light emitting device in the embodiment of the present application may be an OLED.
The display substrate that this application embodiment provided is provided with grid line, data line, power cord, reset signal line, luminous control line, initial signal line and a plurality of sub-pixel in, every sub-pixel includes: a light emitting device and a driving circuit for driving the light emitting device to emit light, the driving circuit comprising: a plurality of transistors and storage capacitors; the display substrate includes: the semiconductor layer, the first metal layer, the second metal layer, the third metal layer, the fourth metal layer and the fifth metal layer are arranged on the substrate in sequence and are insulated from each other; the semiconductor layer includes: an active layer of a plurality of transistors, the first metal layer comprising: the gate line, the light emitting control line, the reset signal line, the first electrode of the storage capacitor and the gate electrodes of the plurality of transistors, the second metal layer includes: a second electrode of the initial signal line and the storage capacitor; the third metal layer includes: source drain electrodes of the plurality of transistors, the fourth metal layer includes: data line and power cord, the fifth metal layer includes: the positive pole of light emitting device, ith row of sub-pixel and ith row data link are connected, and every row of data link includes: a first sub data line and a second sub data line; the first sub data line and the second sub data line in the ith row of data lines are respectively positioned at two sides of the ith row of sub pixels, all the sub data lines between two adjacent rows of sub pixels are only the first sub data line or the second sub data line, i is more than or equal to 1 and is less than or equal to N, and N is the total row number of the sub pixels. The OLED display substrate is provided with five metal layers, and the data lines, the power lines and the source drain electrodes of the transistors are arranged in different layers, so that the occupied volume of the data lines connected with the sub-pixels can be reduced, and the resolution of the high-frequency-driven OLED display substrate is improved.
Optionally, as shown in fig. 3, each sub-pixel in the display substrate provided in the embodiment of the present application is divided into: a first region R1, a second region R2, and a third region R3.
Specifically, the storage capacitor is located in the second region R2, the first region R1 and the third region R3 are respectively located at two sides of the second region and are arranged along the extending direction of the data lines, the initial signal line Vinit, the gate line G and the Reset signal line Reset connected to the sub-pixel are located in the first region R1, and the emission control line EM connected to the sub-pixel is located in the third region R3.
Specifically, adjacent sub-pixels in the same column are connected to different sub-data lines, that is, if the sub-pixel in the ith row and the jth column is connected to the first sub-data line DOj in the jth column data line, the sub-pixel in the (i + 1) th row and the jth column is connected to the second sub-data line DEj in the jth column data line, and if the sub-pixel in the ith row and the jth column is connected to the second sub-data line DEj in the jth column data line, the sub-pixel in the (i + 1) th row and the jth column is connected to the first sub-data line DOj in the jth column data line.
Optionally, as can be seen from FIG. 1 and FIG. 3, the sub-pixel in the ith column is also connected to the power line in the ith column, and 1 ≦ i ≦ N.
The ith column power supply line VDDi is located between the first sub data line DOi and the second sub data line DEi in the ith column data line.
Fig. 5 is a top view of a plurality of sub-pixels in the display substrate according to the embodiment of the present disclosure, and as shown in fig. 5, pixel structures of adjacent sub-pixels located in the same row are mirror-symmetric to each other about a center line CL of two sub-data lines located between the adjacent sub-pixels, a pixel structure of a sub-pixel located in an ith row and a jth column is the same as a pixel structure of a sub-pixel located in an (i + 1) th row and a (j + 1) th column, and a pixel structure of a sub-pixel located in an ith row and a jth column is the same as a pixel structure of a sub-pixel located in an (i + 1) th row and a jth column.
As shown in fig. 5, the power supply lines of adjacent two columns are mirror-symmetrical with respect to a center line located between the power supply lines of adjacent two columns.
Specifically, the center line CL of two sub-data lines between the ith row and jth column sub-pixel and the ith row and jth +1 column sub-pixel is the same as the center line between the jth column power line and the jth +1 column power line.
Alternatively, as shown in fig. 5, the ith column power supply line includes: and a plurality of sub power lines respectively from S1 to SN connected to each other, the plurality of sub power lines corresponding to all the sub pixels in each column one to one. Fig. 5 illustrates an example of 8 sub-pixels in the first two rows and four columns.
Specifically, in this embodiment, the shape of the sub power line corresponding to the sub pixel in the ith row and the jth column after being inverted along the center lines of the first sub data line and the second sub data line in the jth column data line is the same as the shape of the sub power line corresponding to the sub pixel in the (i + 1) th row and the jth column.
Specifically, as shown in fig. 5, each sub power line includes: the power supply comprises a first power supply part SS1, a second power supply part SS2 and a third power supply part SS3, wherein the second power supply part SS2 is used for connecting the first power supply part SS1 and the third power supply part SS3, the first power supply part SS1 and the third power supply part SS3 are arranged in parallel with a data line, and an included angle between the second power supply part SS2 and the first power supply part SS1 is larger than 90 degrees and smaller than 180 degrees.
The first power supply unit SS1, the second power supply unit SS2, and the third power supply unit SS3 are integrally formed.
As shown in fig. 5, the width of the third power supply section SS3 is smaller than that of the first power supply section SS1, on one hand, for the layout of the pixel structure, and on the other hand, since the third power supply section SS3 is closer to the power supply line, the width of the third power supply section SS3 is smaller, which can reduce the parasitic capacitance.
Specifically, the first power supply section SS1 in the sub power supply line corresponding to the sub-pixel in the ith row and jth column is connected to the third power supply section SS3 in the sub power supply line corresponding to the sub-pixel in the ith-1 row and jth column, the third power supply section SS3 in the sub power supply line corresponding to the sub-pixel in the ith row and jth column is connected to the first power supply section SS1 in the sub power supply line corresponding to the sub-pixel in the (i + 1) th row and jth column, and the mutually connected power supply sections are arranged along the data line extending direction.
As shown in fig. 5, the power line in the embodiment of the present application is a zigzag.
In this embodiment, with reference to fig. 5, the working process of each sub-pixel includes: in a Reset stage, a Reset signal line Reset positioned in the first metal layer and an initial signal line Vinit positioned in the second metal layer provide signals to initialize the driving circuit, in a write-in stage, a grid line G positioned in the first metal layer and a data line D positioned in the fourth metal layer provide signals to write a data signal provided by the data line D into the driving circuit; in the light emitting phase, the light emitting control line EM located in the first metal layer provides a signal, and the power line VDD provides a power signal, so that the driving circuit provides a driving current to the light emitting device OLED to drive the light emitting device to emit light.
The pixels in the same row are displayed simultaneously, and the pixels in adjacent rows are sequentially displayed.
Optionally, as shown in fig. 2, the display substrate provided in the present application further includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14.
Specifically, the first insulating layer 11 is disposed between the semiconductor layer 20 and the first metal layer 30, the second insulating layer 12 is disposed between the first metal layer 30 and the second metal layer 40, the third insulating layer 13 is disposed between the second metal layer 40 and the third metal layer 50, and the fourth insulating layer 14 is disposed between the third metal layer 50 and the fourth metal layer 60.
Alternatively, the material of the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 may be silicon oxide, silicon nitride, or a composite of silicon oxide and silicon nitride, which is not limited in this embodiment of the present invention.
In the present embodiment, as shown in fig. 4A, the plurality of transistors includes, for each sub-pixel: first to seventh transistors, and a first electrode of the fifth transistor are connected to the power supply line VDD and the second electrode C2 of the storage capacitor, respectively.
In the embodiment of the present application, for each sub-pixel, the power supply line in each sub-pixel is connected to the second electrode of the storage capacitor through the first electrode of the fifth transistor.
Specifically, the second electrodes of the storage capacitors of the adjacent sub-pixels located in the second metal layer are also multiplexed as power signal lines, so as to ensure that the power signals provided by the power lines of the adjacent sub-pixels are the same, avoid poor display of the display substrate, and ensure the display effect of the display substrate.
In this embodiment, every four continuous sub-pixels form a pixel, and in the jth pixel, the four continuous sub-pixels are sequentially an ith sub-pixel, an (i + 1) th sub-pixel, an (i + 2) th sub-pixel and an (i + 3) th sub-pixel along the gate line arrangement direction, where i can be sequentially valued as 4j-3, and j is a positive integer.
Specifically, the second electrodes of the storage capacitors of the plurality of sub-pixels are connected with various embodiments, as one embodiment, fig. 6A is a top view of a sub-pixel corresponding to the first embodiment, and fig. 6B is another top view of a sub-pixel corresponding to the first embodiment, wherein, as shown in fig. 6A, the fourth insulating layer is provided with a first via V1 exposing a portion of the first electrode 51 of the fifth transistor, and the power line is connected to the first electrode 51 of the fifth transistor through the first via V1; as shown in fig. 6B, the third insulating layer is provided with a second via hole V2 exposing a portion of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor is connected to the second electrode of the storage capacitor through the second via hole V2. Fig. 3 and 5 are described taking the first embodiment as an example.
Wherein, the orthographic projection of the power line connected with the sub-pixel on the substrate covers the orthographic projection of the first via hole V1 on the substrate 10, and the orthographic projection of the second electrode of the storage capacitor on the substrate covers the orthographic projection of the second via hole on the substrate.
Optionally, the number of the first vias V1 is one.
Optionally, the number of the second vias V2 is at least one, and since the width of the first pole of the fifth transistor is narrower, when the number of the second vias V2 is multiple, multiple second vias are disposed along the extending direction of the data line, where multiple second vias are disposed along the extending direction of the data line, multiple vias may be disposed, and the greater the number of the vias, the better the conductivity of the components connected by the vias is, fig. 6A is one first via V1, fig. 6B is illustrated by taking two second vias V2 as an example, which is not limited in this embodiment of the present application.
Specifically, as shown in fig. 6A, the fourth insulating layer further includes a via hole exposing a first pole of the fourth transistor T4 through which the data line is connected with the first pole of the fourth transistor T4, and the fourth insulating layer further includes a second pole exposing the sixth transistor T6 through which the anode of the light emitting device is connected with the second pole of the sixth transistor T6.
Specifically, as shown in fig. 6B, the first insulating layer, the second insulating layer, and the third insulating layer further include: and exposing the via holes of part of the active layer, so that the source and drain electrodes of the transistor are connected with the active layer through the via holes.
Specifically, the first pole of the fifth transistor is further connected with the active layer through via holes in the first insulating layer, the second insulating layer and the third insulating layer.
In the present embodiment, each pixel includes: specifically, fig. 7A is a top view of a second metal layer corresponding to the first embodiment, and fig. 7B is a top view of a third metal layer corresponding to the first embodiment, and in order to more clearly illustrate the structure of the display substrate, fig. 7A and 7B illustrate two pixels arranged in the column direction as an example.
As shown in fig. 7A, the second electrodes of the storage capacitors in the adjacent sub-pixels in the same row are in direct contact, and as shown in fig. 7B, the first electrodes 51 of the fifth transistors of the adjacent sub-pixels in the same row are spaced apart.
In the first embodiment, the second electrodes of the storage capacitors of the plurality of sub-pixels disposed on the second metal layer are in contact with each other, so that power signals provided by power lines of adjacent sub-pixels are the same, display defects of the display substrate are avoided, and display effects of the display substrate are ensured.
As another embodiment, fig. 8A is a top view of a sub-pixel corresponding to the second embodiment, and fig. 8B is another top view of a plurality of sub-pixels corresponding to the second embodiment, wherein as shown in fig. 8A, the fourth insulating layer is provided with a first via V1 exposing a portion of the first pole 51 of the fifth transistor, and the power line is connected to the first pole 51 of the fifth transistor through the first via V1; as shown in fig. 8B, the third insulating layer is provided with a second via hole V2 exposing a portion of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor is connected to the second electrode of the storage capacitor through the second via hole V2.
As shown in fig. 8A and 8B, the area occupied by the second electrode of the storage capacitor of each sub-pixel is different from that provided in the first embodiment, and the shape of the first electrode 51 of the fifth transistor is also different.
Specifically, as shown in fig. 8A, the fourth insulating layer further includes a via hole exposing a first pole of the fourth transistor T4 through which the data line is connected with the first pole of the fourth transistor T4, and the fourth insulating layer further includes a second pole exposing the sixth transistor T6 through which the anode of the light emitting device is connected with the second pole of the sixth transistor T6.
Specifically, as shown in fig. 3 and 8B, the first insulating layer, the second insulating layer, and the third insulating layer further include: and exposing the via holes of part of the active layer, so that the source and drain electrodes of the transistor are connected with the active layer through the via holes. Specifically, the first pole of the fifth transistor is further connected with the active layer through via holes in the first insulating layer, the second insulating layer and the third insulating layer.
Wherein, the orthographic projection of the power line connected with the sub-pixel on the substrate covers the orthographic projection of the first via hole V1 on the substrate 10, and the orthographic projection of the second electrode of the storage capacitor on the substrate covers the orthographic projection of the second via hole on the substrate.
Optionally, the number of the first vias V1 is one.
Optionally, the number of the second vias V2 is at least one, and since the width of the first pole of the fifth transistor is narrower, the number of vias provided along the extending direction of the data line by the plurality of second vias can be ensured, the greater the number of vias, the better the conductivity of the components connected by the vias, fig. 8A is a first via V1, fig. 8B is an example of two second vias V2, which is not limited in this embodiment of the present invention.
Specifically, fig. 9A is a top view of a second metal layer corresponding to the second embodiment, fig. 9B is a top view of a third metal layer corresponding to the second embodiment, fig. 10 is another top view of a plurality of sub-pixels in a display substrate provided in an example of the present application, in order to more clearly illustrate the structure of the display substrate, fig. 9A and 9B are illustrated by taking two pixels arranged in a column direction as an example, fig. 10 includes other film layers except an anode of a light emitting device, and the plurality of sub-pixels included in fig. 10 are sub-pixels corresponding to the second embodiment.
As shown in fig. 9A and 9B, the second electrode of the storage capacitor of the ith sub-pixel in each pixel in one of two adjacent rows of pixels is in direct contact with the second electrode of the storage capacitor of the (i + 1) th sub-pixel, the second electrode of the storage capacitor of the (i + 1) th sub-pixel and the second electrode of the storage capacitor of the (i + 2) th sub-pixel are arranged at intervals, and the second electrode of the storage capacitor of the (i + 2) th sub-pixel is in direct contact with the second electrode of the storage capacitor of the (i + 3) th sub-pixel; the second electrode of the storage capacitor of the ith sub-pixel in each pixel of the other row in the two adjacent rows of pixels is arranged at an interval with the second electrode of the storage capacitor of the (i + 1) th sub-pixel, the second electrode of the storage capacitor of the (i + 1) th sub-pixel is directly contacted with the second electrode of the storage capacitor of the (i + 2) th sub-pixel, and the second electrode of the storage capacitor of the (i + 2) th sub-pixel is arranged at an interval with the second electrode of the storage capacitor of the (i + 3) th sub-pixel.
In addition, fig. 9A illustrates an example in which the second electrode of the storage capacitor of the i-th sub-pixel in the first row of pixels is in direct contact with the second electrode of the storage capacitor of the i + 1-th sub-pixel, and the second electrode of the storage capacitor of the i + 2-th sub-pixel in the second row of pixels is in direct contact with the second electrode of the storage capacitor of the i + 3-th sub-pixel.
Alternatively, as shown in fig. 10, for each sub-pixel, there is an overlapping region of the orthographic projection of the first electrode of the fifth transistor on the substrate and the orthographic projection of the data line connected to the sub-pixel on the substrate.
In the present embodiment, in conjunction with fig. 9A, 9B, and 10, for the j-th pixel, in a state where the second electrode C2 of the storage capacitance of the i-th sub-pixel is in direct contact with the second electrode C2 of the storage capacitance of the i + 1-th sub-pixel, the first electrode 51 of the fifth transistor in the i + 1-th sub-pixel is in direct contact with the first electrode 51 of the fifth transistor in the i + 2-th sub-pixel; wherein the second electrode C2 of the storage capacitor located in the ith sub-pixel in the second metal layer is connected to the second electrode C2 of the storage capacitor located in the ith +3 sub-pixel in the second metal layer through the first electrode 51 of the fifth transistor located in the ith +1 sub-pixel in the third metal layer and the first electrode 51 of the fifth transistor in the ith +2 sub-pixel.
In the present embodiment, for the jth pixel, in a condition where the second electrode C2 of the storage capacitance of the (i + 1) th sub-pixel is in direct contact with the second electrode C2 of the storage capacitance of the (i + 2) th sub-pixel, the first electrode 51 of the fifth transistor in the (i) th sub-pixel is in direct contact with the first electrode 51 of the fifth transistor in the (i + 1) th sub-pixel, and the first electrode 51 of the fifth transistor in the (i + 2) th sub-pixel is in direct contact with the first electrode 51 of the fifth transistor in the (i + 3) th sub-pixel; wherein the second electrode C2 of the storage capacitor of the ith sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the (i + 1) th sub-pixel located in the second metal layer through the first electrode 51 of the fifth transistor located in the ith sub-pixel located in the third metal layer and the first electrode 51 of the fifth transistor in the (i + 1) th sub-pixel, and the second electrode C2 of the storage capacitor of the (i + 2) th sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the (i + 3) th sub-pixel located in the second metal layer through the first electrode 51 of the fifth transistor located in the (i + 2) th sub-pixel located in the third metal layer and the first electrode 51 of the fifth transistor in the (i + 3) th sub-pixel located in the second metal layer.
In the second embodiment, the second metal layer and the third metal layer jointly complete the transverse cross-over connection to realize the function of the power connection line, so that the power signals provided to each sub-pixel are the same, and the display effect of the display substrate is ensured.
In addition, since the resistivity of the third metal layer is smaller than that of the second metal layer, the display substrate according to the second embodiment can further reduce the dynamic crosstalk compared to the display substrate according to the first embodiment.
Optionally, as shown in fig. 2, the display substrate provided in the embodiment of the present application further includes: a fifth insulating layer 15 and a planarization layer 16 arranged between the fourth metal layer 60 and the fifth metal layer 70, and an organic material layer and a cathode (not shown in the figure) of the light emitting device arranged on the side of the fifth metal layer 70 facing away from the substrate 10.
Specifically, the fifth insulating layer 15 is disposed on one side of the planarization layer 16 close to the substrate 10; the cathode is disposed on a side of the organic material layer remote from the substrate 10.
As shown in fig. 3, the fourth metal layer provided in the embodiment of the present application further includes: and a connection electrode 61, wherein the connection electrode is connected to the second pole of the sixth transistor.
The fifth insulating layer and the flat layer are provided with through holes exposing the connecting electrodes, the fifth metal layer is connected with the connecting electrodes through the through holes exposing the connecting electrodes, the fourth insulating layer is provided with through holes exposing the second pole of the sixth transistor, and the connecting electrodes are connected with the second pole of the sixth transistor through the through holes exposing the second pole of the sixth transistor.
Based on the same inventive concept, an embodiment of the present application further provides a manufacturing method of a display substrate, which is used for manufacturing the display substrate provided in the foregoing embodiment, and fig. 11 is a flowchart of the manufacturing method of the display substrate provided in the embodiment of the present application, as shown in fig. 11, the manufacturing method of the display substrate provided in the embodiment of the present application specifically includes the following steps:
in step S1, a substrate is provided.
Step S2, sequentially forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer on the substrate, wherein the semiconductor layer, the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, and the fifth metal layer are insulated from each other.
Specifically, the semiconductor layer includes: an active layer of a plurality of transistors, the first metal layer comprising: the gate line, the light emitting control line, the reset signal line, the first electrode of the storage capacitor and the gate electrodes of the plurality of transistors, the second metal layer includes: a second electrode of the initial signal line and the storage capacitor; the third metal layer includes: source drain electrodes of the plurality of transistors, the fourth metal layer includes: data line and power cord, the fifth metal layer includes: an anode of the light emitting device; the ith row of sub-pixels is connected with the ith row of data lines, and each row of data lines comprises: a first sub data line and a second sub data line; a first sub data line and a second sub data line in the ith row of data lines are respectively positioned at two sides of the ith row of sub pixels, and all sub data lines between every two adjacent rows of sub pixels are only the first sub data line or the second sub data line.
Wherein i is more than or equal to 1 and less than or equal to N, and N is the total column number of the sub-pixels.
The manufacturing method of the display substrate provided by the embodiment of the application is used for manufacturing the display substrate provided by the embodiment, and the implementation principle and the implementation effect are similar, and are not repeated here.
Optionally, step 200 comprises: forming a semiconductor layer and a first insulating layer on a substrate in sequence; sequentially forming a first metal layer and a second insulating layer on the first insulating layer; sequentially forming a second metal layer and a third insulating layer on the second insulating layer; sequentially forming a third metal layer and a fourth insulating layer on the third insulating layer; sequentially forming a fourth metal layer, a fifth insulating layer and a flat layer on the fourth insulating layer; and sequentially forming a fifth metal layer, an organic light-emitting layer of the light-emitting device and a cathode of the light-emitting device on the flat layer.
Fig. 12 is a first schematic view illustrating fabrication of a display substrate according to an embodiment of the present disclosure, fig. 13 is a second schematic view illustrating fabrication of a display substrate according to an embodiment of the present disclosure, fig. 14A is a third schematic view illustrating fabrication of a display substrate according to an embodiment of the present disclosure, fig. 14B is another third schematic view illustrating fabrication of a display substrate according to an embodiment of the present disclosure, fig. 15A is a fourth schematic view illustrating fabrication of a display substrate according to an embodiment of the present disclosure, fig. 15B is another fourth schematic view illustrating fabrication of a display substrate according to an embodiment of the present disclosure, fig. 16A is a schematic diagram illustrating a fifth manufacturing process of the display substrate according to the embodiment of the present application, and fig. 16B is a schematic diagram illustrating another fifth manufacturing process of the display substrate according to the embodiment of the present application, and the method for manufacturing the display substrate according to the embodiment of the present application is further described below with reference to fig. 12 to fig. 16, and specifically described below:
optionally, the patterning process comprises: photoresist coating, exposure, development, etching, photoresist stripping and the like.
Step 100, providing a substrate 10, depositing a semiconductor film on the substrate 10, and processing the semiconductor film by a patterning process to form a semiconductor layer 20, as shown in fig. 12.
The manufacturing schematic diagram of the active layer in the first embodiment is the same as that of the active layer in the second embodiment.
Step 200, depositing an insulating film on the semiconductor layer 20, processing the insulating film by a patterning process to form a first insulating layer, depositing a metal film on the first insulating layer, and processing the metal film by a patterning process to form a first metal layer 30, as shown in fig. 13.
Wherein the first metal layer 30 includes: a gate line G, a Reset signal line Reset, an emission control line EM, and a first electrode C1 of the storage capacitor.
The schematic diagram of the first metal layer in the first embodiment is the same as the schematic diagram of the first metal layer in the second embodiment.
Step 300, depositing an insulating film on the first metal layer 30, processing the insulating film by using a patterning process to form a second insulating layer, depositing a metal film on the second insulating layer, processing the metal film by using a patterning process to form an initial signal line Vinit and a second metal layer of the second electrode C2 of the storage capacitor, forming a deposited insulating film on the second metal layer, and processing the insulating film by using a patterning process to form a third insulating layer, as shown in fig. 14A and 14B.
The third insulating layer comprises a first via hole V1 exposing the second electrode and a via hole exposing the initial signal line Vinit, the second insulating layer and the third insulating layer are provided with via holes exposing the first electrode, and the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.
Fig. 14A is a manufacturing diagram of the first embodiment, and fig. 14B is a manufacturing diagram of the second embodiment.
Step 400, depositing a metal film on the third insulating layer, processing the metal film through a patterning process to form a third metal layer including source and drain electrodes of a plurality of transistors, depositing an insulating film on the third metal layer, and processing the insulating film through the patterning process to form a fourth insulating layer, as shown in fig. 15A and 15B.
The fourth insulating layer includes a first via hole V1 exposing the fifth transistor, a via hole exposing the second pole of the sixth transistor, and a via hole exposing the first pole of the fourth transistor.
Fig. 15A is a schematic diagram illustrating the fabrication of the first embodiment, and fig. 15B is a schematic diagram illustrating the fabrication of the second embodiment.
Step 500, depositing a metal film on the fourth insulating layer, processing the metal film through a composition process to form a fourth metal layer including the data line D, the power line VDD, and the connection electrode 61, depositing an insulating film on the fourth metal layer, processing the insulating film through the composition process to form a fifth insulating layer, coating a flat film on the fifth insulating layer, and processing the flat film through the composition process to form a flat layer, as shown in fig. 16A and 16B.
Specifically, the fifth insulating layer and the flat layer are provided with via holes for exposing the connecting electrodes to emit light.
Fig. 16A is a schematic diagram illustrating the fabrication of the first embodiment, and fig. 16B is a schematic diagram illustrating the fabrication of the second embodiment.
Step 600, depositing a metal film on the flat layer, processing the metal film through a composition process to form a fifth metal layer, coating an organic material film on the fifth metal layer, processing the organic material film through the composition process to form an organic material layer, depositing a conductive film on the organic material layer, and processing the conductive film through the composition process to perform a cathode.
Based on the same inventive concept, the embodiment of the present application further provides a display device, wherein the display device includes: a display substrate.
Optionally, the display substrate is an OLED display substrate.
Specifically, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, etc., but the embodiment of the present invention is not limited thereto.
The display substrate is provided in the foregoing embodiments, and the implementation principle and the implementation effect thereof are similar, and are not described herein again.
In the drawings used to describe embodiments of the invention, the thickness and dimensions of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (24)

1. A display substrate, comprising: the array-arranged sub-pixels comprise sub-pixels arranged in an array, a plurality of data lines and a plurality of power lines; at least one of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a storage capacitor; the storage capacitor includes: the first electrode and the second electrode that set up relatively, the display substrates includes: the semiconductor device comprises a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially stacked on the substrate;
the semiconductor layer includes: an active layer of transistors in at least one driver circuit;
the first metal layer includes: a first electrode of a storage capacitor;
the second metal layer includes: a second electrode of the storage capacitor;
a power line; the power cord includes: at least one sub-power line connected with each other, the sub-power line is connected with the sub-pixel and is located in the area where the sub-pixel is located, and the at least one sub-power line at least comprises three power parts: a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply part is connected with the first power supply part and the third power supply part; the data line is arranged in parallel with the extending direction of the first power supply part and the third power supply part.
2. The display substrate of claim 1, wherein the data line is located in the fourth metal layer.
3. A display substrate according to claim 1, wherein for at least one of the drive circuits, the second electrode of the storage capacitor is arranged to be written with a power supply signal, which is a signal of a sub-power supply line.
4. The display substrate of claim 1, further comprising: a fourth insulating layer and a fifth insulating layer, the fourth insulating layer being disposed between the third metal layer and the fourth metal layer, the fifth insulating layer being disposed on a side of the fourth metal layer away from the substrate, the fourth metal layer further including: connecting the electrodes;
the fifth insulating layer is provided with a through hole exposing the connecting electrode, and the fourth insulating layer is provided with a through hole exposing the third metal layer; and the orthographic projection of the via hole exposing the third metal layer on the substrate is at least partially overlapped with the orthographic projection of the connecting electrode on the substrate.
5. The display substrate according to claim 4, wherein an extending direction of the connection electrode is arranged in parallel with an extending direction of the first power supply portion.
6. The display substrate according to claim 4, wherein the extending direction of the dummy connection line of the via hole exposing the third metal layer and the via hole exposing the connection electrode is parallel to the extending direction of the data line.
7. The display substrate of claim 4, wherein an orthographic projection of the via exposing the connecting electrode on the substrate at least partially overlaps with an orthographic projection of the via exposing the third metal layer on the substrate.
8. The display substrate according to claim 4, wherein the virtual extension line of the first power supply portion passes through the via hole exposing the connection electrode.
9. The display substrate of claim 4, wherein the virtual extension line of the first power supply portion passes through the via hole exposing the third metal layer.
10. The display substrate of claim 1, further comprising: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer being disposed between a third metal layer and a semiconductor layer, the fourth insulating layer being disposed between a third metal layer and a fourth metal layer;
the fourth insulating layer is provided with a via hole exposing the third metal layer, the data line is connected with the third metal layer through the via hole exposing the third metal layer, and the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.
11. The display substrate of claim 10, wherein an orthographic projection of the via exposing the third metal layer on the substrate at least partially overlaps with an orthographic projection of the via exposing the semiconductor layer on the substrate.
12. The display substrate according to claim 10, wherein a virtual extension line of the third power supply portion passes through the via hole exposing the semiconductor layer.
13. The display substrate of claim 10, wherein the virtual extension line of the third power supply portion passes through the via hole exposing the third metal layer.
14. The display substrate according to claim 1, wherein an included angle between the first power supply portion and the second power supply portion is greater than or equal to 90 degrees and less than 180 degrees;
the included angle between the second power supply part and the third power supply part is larger than or equal to 90 degrees and smaller than 180 degrees.
15. The display substrate according to claim 1, wherein an average width of the first power supply portion is greater than or equal to an average width of the second power supply portion;
the average width of the second power supply part is greater than or equal to the average width of the third power supply part;
the average width of the third power supply part is greater than or equal to the average width of the data lines.
16. The display substrate according to claim 1, wherein the active layers of adjacent sub-pixels arranged along a first direction or a second direction are mirror-symmetrical, the first direction is perpendicular to the second direction, and the second direction is an extending direction of the data line.
17. The display substrate according to claim 1, wherein the driving circuit comprises: a second transistor, an orthographic projection of the first power supply part on the substrate and an orthographic projection of a part of the second transistor on the substrate at least partially overlap.
18. The display substrate according to claim 1, wherein the driving circuit comprises: a first transistor, wherein the orthographic projection of the second power supply part on the substrate at least partially overlaps with the orthographic projection of part of the first transistor on the substrate.
19. The display substrate according to claim 1, wherein an orthographic projection of the second power supply portion on the base at least partially overlaps with an orthographic projection of a portion of the second electrode on the base.
20. The display substrate of claim 1, wherein the first metal layer further comprises: and the orthographic projection of the second power supply part on the substrate is at least partially overlapped with the orthographic projection of the grid line on the substrate.
21. The display substrate according to claim 1, wherein an orthographic projection of the third power supply portion on the substrate at least partially overlaps with an orthographic projection of a portion of the at least one transistor on the substrate.
22. The display substrate according to claim 21, wherein the driving circuit comprises: and an orthographic projection of the third power supply part on the substrate is at least partially overlapped with an orthographic projection of a part of the fifth transistor on the substrate.
23. The display substrate according to claim 21, wherein the driving circuit comprises: and an orthographic projection of the third power supply part on the substrate is at least partially overlapped with an orthographic projection of a part of the sixth transistor on the substrate.
24. A display device, comprising: a display substrate according to any one of claims 1 to 23.
CN202111498970.5A 2019-11-07 2019-11-07 Display substrate and display device Pending CN114203784A (en)

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AU2020376100B2 (en) * 2019-10-29 2022-12-08 Boe Technology Group Co., Ltd. Display substrate and method for manufacturing same, and display apparatus
CN113096596A (en) * 2020-01-08 2021-07-09 京东方科技集团股份有限公司 Display substrate, driving method thereof and display device
CN111312771B (en) * 2020-02-25 2022-12-16 京东方科技集团股份有限公司 Display substrate and display device
CN114503272B (en) * 2020-03-25 2023-12-19 京东方科技集团股份有限公司 Display substrate and display device
CN111613658B (en) * 2020-06-02 2023-07-14 京东方科技集团股份有限公司 Display substrate and display device
CN114616616B (en) * 2020-08-31 2023-12-22 京东方科技集团股份有限公司 Display substrate, manufacturing method thereof and display device
CN112071882B (en) * 2020-09-16 2023-07-28 合肥京东方卓印科技有限公司 Display substrate, preparation method thereof and display device
CN112053661B (en) * 2020-09-28 2023-04-11 京东方科技集团股份有限公司 Pixel circuit, pixel driving method, display panel and display device
CN112259577A (en) * 2020-10-09 2021-01-22 武汉华星光电半导体显示技术有限公司 Pixel structure
CN112310044B (en) * 2020-10-29 2024-04-02 合肥京东方显示技术有限公司 Display substrate, preparation method thereof and display device
CN112289194B (en) * 2020-10-30 2022-06-14 合肥维信诺科技有限公司 Display panel and display device
GB2610513A (en) * 2020-12-15 2023-03-08 Boe Technology Group Co Ltd Display substrate and display device
CN113075826B (en) * 2021-03-16 2022-07-29 Tcl华星光电技术有限公司 Display panel and display device
US11947229B2 (en) 2021-03-16 2024-04-02 Tcl China Star Optoelectronics Technology Co., Ltd. Display panel and display device
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CN113793856B (en) * 2021-09-13 2024-05-07 京东方科技集团股份有限公司 Display substrate, preparation method thereof and display device

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